2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
31 #include <linux/cpu_pm.h>
33 #include <asm/cacheflush.h>
34 #include <asm/cputype.h>
35 #include <asm/current.h>
36 #include <asm/hw_breakpoint.h>
37 #include <asm/kdebug.h>
38 #include <asm/traps.h>
39 #include <asm/hardware/coresight.h>
41 /* Breakpoint currently in use for each BRP. */
42 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
44 /* Watchpoint currently in use for each WRP. */
45 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
47 /* Number of BRP/WRP registers on this CPU. */
48 static int core_num_brps;
49 static int core_num_wrps;
51 /* Debug architecture version. */
54 /* Does debug architecture support OS Save and Restore? */
57 /* Maximum supported watchpoint length. */
58 static u8 max_watchpoint_len;
60 #define READ_WB_REG_CASE(OP2, M, VAL) \
61 case ((OP2 << 4) + M): \
62 ARM_DBG_READ(c0, c ## M, OP2, VAL); \
65 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
66 case ((OP2 << 4) + M): \
67 ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \
70 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
71 READ_WB_REG_CASE(OP2, 0, VAL); \
72 READ_WB_REG_CASE(OP2, 1, VAL); \
73 READ_WB_REG_CASE(OP2, 2, VAL); \
74 READ_WB_REG_CASE(OP2, 3, VAL); \
75 READ_WB_REG_CASE(OP2, 4, VAL); \
76 READ_WB_REG_CASE(OP2, 5, VAL); \
77 READ_WB_REG_CASE(OP2, 6, VAL); \
78 READ_WB_REG_CASE(OP2, 7, VAL); \
79 READ_WB_REG_CASE(OP2, 8, VAL); \
80 READ_WB_REG_CASE(OP2, 9, VAL); \
81 READ_WB_REG_CASE(OP2, 10, VAL); \
82 READ_WB_REG_CASE(OP2, 11, VAL); \
83 READ_WB_REG_CASE(OP2, 12, VAL); \
84 READ_WB_REG_CASE(OP2, 13, VAL); \
85 READ_WB_REG_CASE(OP2, 14, VAL); \
86 READ_WB_REG_CASE(OP2, 15, VAL)
88 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
89 WRITE_WB_REG_CASE(OP2, 0, VAL); \
90 WRITE_WB_REG_CASE(OP2, 1, VAL); \
91 WRITE_WB_REG_CASE(OP2, 2, VAL); \
92 WRITE_WB_REG_CASE(OP2, 3, VAL); \
93 WRITE_WB_REG_CASE(OP2, 4, VAL); \
94 WRITE_WB_REG_CASE(OP2, 5, VAL); \
95 WRITE_WB_REG_CASE(OP2, 6, VAL); \
96 WRITE_WB_REG_CASE(OP2, 7, VAL); \
97 WRITE_WB_REG_CASE(OP2, 8, VAL); \
98 WRITE_WB_REG_CASE(OP2, 9, VAL); \
99 WRITE_WB_REG_CASE(OP2, 10, VAL); \
100 WRITE_WB_REG_CASE(OP2, 11, VAL); \
101 WRITE_WB_REG_CASE(OP2, 12, VAL); \
102 WRITE_WB_REG_CASE(OP2, 13, VAL); \
103 WRITE_WB_REG_CASE(OP2, 14, VAL); \
104 WRITE_WB_REG_CASE(OP2, 15, VAL)
106 static u32 read_wb_reg(int n)
111 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
112 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
113 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
114 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
116 pr_warning("attempt to read from unknown breakpoint "
123 static void write_wb_reg(int n, u32 val)
126 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
127 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
128 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
129 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
131 pr_warning("attempt to write to unknown breakpoint "
137 /* Determine debug architecture. */
138 static u8 get_debug_arch(void)
142 /* Do we implement the extended CPUID interface? */
143 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
144 pr_warn_once("CPUID feature registers not supported. "
145 "Assuming v6 debug is present.\n");
146 return ARM_DEBUG_ARCH_V6;
149 ARM_DBG_READ(c0, c0, 0, didr);
150 return (didr >> 16) & 0xf;
153 u8 arch_get_debug_arch(void)
158 static int debug_arch_supported(void)
160 u8 arch = get_debug_arch();
162 /* We don't support the memory-mapped interface. */
163 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
164 arch >= ARM_DEBUG_ARCH_V7_1;
167 /* Can we determine the watchpoint access type from the fsr? */
168 static int debug_exception_updates_fsr(void)
173 /* Determine number of WRP registers available. */
174 static int get_num_wrp_resources(void)
177 ARM_DBG_READ(c0, c0, 0, didr);
178 return ((didr >> 28) & 0xf) + 1;
181 /* Determine number of BRP registers available. */
182 static int get_num_brp_resources(void)
185 ARM_DBG_READ(c0, c0, 0, didr);
186 return ((didr >> 24) & 0xf) + 1;
189 /* Does this core support mismatch breakpoints? */
190 static int core_has_mismatch_brps(void)
192 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
193 get_num_brp_resources() > 1);
196 /* Determine number of usable WRPs available. */
197 static int get_num_wrps(void)
200 * On debug architectures prior to 7.1, when a watchpoint fires, the
201 * only way to work out which watchpoint it was is by disassembling
202 * the faulting instruction and working out the address of the memory
205 * Furthermore, we can only do this if the watchpoint was precise
206 * since imprecise watchpoints prevent us from calculating register
209 * Providing we have more than 1 breakpoint register, we only report
210 * a single watchpoint register for the time being. This way, we always
211 * know which watchpoint fired. In the future we can either add a
212 * disassembler and address generation emulator, or we can insert a
213 * check to see if the DFAR is set on watchpoint exception entry
214 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
215 * that it is set on some implementations].
217 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
220 return get_num_wrp_resources();
223 /* Determine number of usable BRPs available. */
224 static int get_num_brps(void)
226 int brps = get_num_brp_resources();
227 return core_has_mismatch_brps() ? brps - 1 : brps;
231 * In order to access the breakpoint/watchpoint control registers,
232 * we must be running in debug monitor mode. Unfortunately, we can
233 * be put into halting debug mode at any time by an external debugger
234 * but there is nothing we can do to prevent that.
236 static int monitor_mode_enabled(void)
239 ARM_DBG_READ(c0, c1, 0, dscr);
240 return !!(dscr & ARM_DSCR_MDBGEN);
243 static int enable_monitor_mode(void)
246 ARM_DBG_READ(c0, c1, 0, dscr);
248 /* If monitor mode is already enabled, just return. */
249 if (dscr & ARM_DSCR_MDBGEN)
252 /* Write to the corresponding DSCR. */
253 switch (get_debug_arch()) {
254 case ARM_DEBUG_ARCH_V6:
255 case ARM_DEBUG_ARCH_V6_1:
256 ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN));
258 case ARM_DEBUG_ARCH_V7_ECP14:
259 case ARM_DEBUG_ARCH_V7_1:
260 ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
267 /* Check that the write made it through. */
268 ARM_DBG_READ(c0, c1, 0, dscr);
269 if (!(dscr & ARM_DSCR_MDBGEN)) {
270 pr_warn_once("Failed to enable monitor mode on CPU %d.\n",
279 int hw_breakpoint_slots(int type)
281 if (!debug_arch_supported())
285 * We can be called early, so don't rely on
286 * our static variables being initialised.
290 return get_num_brps();
292 return get_num_wrps();
294 pr_warning("unknown slot type: %d\n", type);
300 * Check if 8-bit byte-address select is available.
301 * This clobbers WRP 0.
303 static u8 get_max_wp_len(void)
306 struct arch_hw_breakpoint_ctrl ctrl;
309 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
312 memset(&ctrl, 0, sizeof(ctrl));
313 ctrl.len = ARM_BREAKPOINT_LEN_8;
314 ctrl_reg = encode_ctrl_reg(ctrl);
316 write_wb_reg(ARM_BASE_WVR, 0);
317 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
318 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
325 u8 arch_get_max_wp_len(void)
327 return max_watchpoint_len;
331 * Install a perf counter breakpoint.
333 int arch_install_hw_breakpoint(struct perf_event *bp)
335 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
336 struct perf_event **slot, **slots;
337 int i, max_slots, ctrl_base, val_base;
340 addr = info->address;
341 ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
343 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
345 ctrl_base = ARM_BASE_BCR;
346 val_base = ARM_BASE_BVR;
347 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
348 max_slots = core_num_brps;
351 ctrl_base = ARM_BASE_WCR;
352 val_base = ARM_BASE_WVR;
353 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
354 max_slots = core_num_wrps;
357 for (i = 0; i < max_slots; ++i) {
366 if (i == max_slots) {
367 pr_warning("Can't find any breakpoint slot\n");
371 /* Override the breakpoint data with the step data. */
372 if (info->step_ctrl.enabled) {
373 addr = info->trigger & ~0x3;
374 ctrl = encode_ctrl_reg(info->step_ctrl);
375 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
377 ctrl_base = ARM_BASE_BCR + core_num_brps;
378 val_base = ARM_BASE_BVR + core_num_brps;
382 /* Setup the address register. */
383 write_wb_reg(val_base + i, addr);
385 /* Setup the control register. */
386 write_wb_reg(ctrl_base + i, ctrl);
390 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
392 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
393 struct perf_event **slot, **slots;
394 int i, max_slots, base;
396 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
399 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
400 max_slots = core_num_brps;
404 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
405 max_slots = core_num_wrps;
408 /* Remove the breakpoint. */
409 for (i = 0; i < max_slots; ++i) {
418 if (i == max_slots) {
419 pr_warning("Can't find any breakpoint slot\n");
423 /* Ensure that we disable the mismatch breakpoint. */
424 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
425 info->step_ctrl.enabled) {
427 base = ARM_BASE_BCR + core_num_brps;
430 /* Reset the control register. */
431 write_wb_reg(base + i, 0);
434 static int get_hbp_len(u8 hbp_len)
436 unsigned int len_in_bytes = 0;
439 case ARM_BREAKPOINT_LEN_1:
442 case ARM_BREAKPOINT_LEN_2:
445 case ARM_BREAKPOINT_LEN_4:
448 case ARM_BREAKPOINT_LEN_8:
457 * Check whether bp virtual address is in kernel space.
459 int arch_check_bp_in_kernelspace(struct perf_event *bp)
463 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
466 len = get_hbp_len(info->ctrl.len);
468 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
472 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
473 * Hopefully this will disappear when ptrace can bypass the conversion
474 * to generic breakpoint descriptions.
476 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
477 int *gen_len, int *gen_type)
481 case ARM_BREAKPOINT_EXECUTE:
482 *gen_type = HW_BREAKPOINT_X;
484 case ARM_BREAKPOINT_LOAD:
485 *gen_type = HW_BREAKPOINT_R;
487 case ARM_BREAKPOINT_STORE:
488 *gen_type = HW_BREAKPOINT_W;
490 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
491 *gen_type = HW_BREAKPOINT_RW;
499 case ARM_BREAKPOINT_LEN_1:
500 *gen_len = HW_BREAKPOINT_LEN_1;
502 case ARM_BREAKPOINT_LEN_2:
503 *gen_len = HW_BREAKPOINT_LEN_2;
505 case ARM_BREAKPOINT_LEN_4:
506 *gen_len = HW_BREAKPOINT_LEN_4;
508 case ARM_BREAKPOINT_LEN_8:
509 *gen_len = HW_BREAKPOINT_LEN_8;
519 * Construct an arch_hw_breakpoint from a perf_event.
521 static int arch_build_bp_info(struct perf_event *bp)
523 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
526 switch (bp->attr.bp_type) {
527 case HW_BREAKPOINT_X:
528 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
530 case HW_BREAKPOINT_R:
531 info->ctrl.type = ARM_BREAKPOINT_LOAD;
533 case HW_BREAKPOINT_W:
534 info->ctrl.type = ARM_BREAKPOINT_STORE;
536 case HW_BREAKPOINT_RW:
537 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
544 switch (bp->attr.bp_len) {
545 case HW_BREAKPOINT_LEN_1:
546 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
548 case HW_BREAKPOINT_LEN_2:
549 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
551 case HW_BREAKPOINT_LEN_4:
552 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
554 case HW_BREAKPOINT_LEN_8:
555 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
556 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
557 && max_watchpoint_len >= 8)
564 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
565 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
566 * by the hardware and must be aligned to the appropriate number of
569 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
570 info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
571 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
575 info->address = bp->attr.bp_addr;
578 info->ctrl.privilege = ARM_BREAKPOINT_USER;
579 if (arch_check_bp_in_kernelspace(bp))
580 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
583 info->ctrl.enabled = !bp->attr.disabled;
586 info->ctrl.mismatch = 0;
592 * Validate the arch-specific HW Breakpoint register settings.
594 int arch_validate_hwbkpt_settings(struct perf_event *bp)
596 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
598 u32 offset, alignment_mask = 0x3;
600 /* Ensure that we are in monitor debug mode. */
601 if (!monitor_mode_enabled())
604 /* Build the arch_hw_breakpoint. */
605 ret = arch_build_bp_info(bp);
609 /* Check address alignment. */
610 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
611 alignment_mask = 0x7;
612 offset = info->address & alignment_mask;
619 /* Allow halfword watchpoints and breakpoints. */
620 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
623 /* Allow single byte watchpoint. */
624 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
631 info->address &= ~alignment_mask;
632 info->ctrl.len <<= offset;
634 if (!bp->overflow_handler) {
636 * Mismatch breakpoints are required for single-stepping
639 if (!core_has_mismatch_brps())
642 /* We don't allow mismatch breakpoints in kernel space. */
643 if (arch_check_bp_in_kernelspace(bp))
647 * Per-cpu breakpoints are not supported by our stepping
650 if (!bp->hw.bp_target)
654 * We only support specific access types if the fsr
657 if (!debug_exception_updates_fsr() &&
658 (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
659 info->ctrl.type == ARM_BREAKPOINT_STORE))
668 * Enable/disable single-stepping over the breakpoint bp at address addr.
670 static void enable_single_step(struct perf_event *bp, u32 addr)
672 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
674 arch_uninstall_hw_breakpoint(bp);
675 info->step_ctrl.mismatch = 1;
676 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4;
677 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE;
678 info->step_ctrl.privilege = info->ctrl.privilege;
679 info->step_ctrl.enabled = 1;
680 info->trigger = addr;
681 arch_install_hw_breakpoint(bp);
684 static void disable_single_step(struct perf_event *bp)
686 arch_uninstall_hw_breakpoint(bp);
687 counter_arch_bp(bp)->step_ctrl.enabled = 0;
688 arch_install_hw_breakpoint(bp);
691 static void watchpoint_handler(unsigned long addr, unsigned int fsr,
692 struct pt_regs *regs)
695 u32 val, ctrl_reg, alignment_mask;
696 struct perf_event *wp, **slots;
697 struct arch_hw_breakpoint *info;
698 struct arch_hw_breakpoint_ctrl ctrl;
700 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
702 for (i = 0; i < core_num_wrps; ++i) {
710 info = counter_arch_bp(wp);
712 * The DFAR is an unknown value on debug architectures prior
713 * to 7.1. Since we only allow a single watchpoint on these
714 * older CPUs, we can set the trigger to the lowest possible
717 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
719 info->trigger = wp->attr.bp_addr;
721 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
722 alignment_mask = 0x7;
724 alignment_mask = 0x3;
726 /* Check if the watchpoint value matches. */
727 val = read_wb_reg(ARM_BASE_WVR + i);
728 if (val != (addr & ~alignment_mask))
731 /* Possible match, check the byte address select. */
732 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
733 decode_ctrl_reg(ctrl_reg, &ctrl);
734 if (!((1 << (addr & alignment_mask)) & ctrl.len))
737 /* Check that the access type matches. */
738 if (debug_exception_updates_fsr()) {
739 access = (fsr & ARM_FSR_ACCESS_MASK) ?
740 HW_BREAKPOINT_W : HW_BREAKPOINT_R;
741 if (!(access & hw_breakpoint_type(wp)))
745 /* We have a winner. */
746 info->trigger = addr;
749 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
750 perf_bp_event(wp, regs);
753 * If no overflow handler is present, insert a temporary
754 * mismatch breakpoint so we can single-step over the
755 * watchpoint trigger.
757 if (!wp->overflow_handler)
758 enable_single_step(wp, instruction_pointer(regs));
765 static void watchpoint_single_step_handler(unsigned long pc)
768 struct perf_event *wp, **slots;
769 struct arch_hw_breakpoint *info;
771 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
773 for (i = 0; i < core_num_wrps; ++i) {
781 info = counter_arch_bp(wp);
782 if (!info->step_ctrl.enabled)
786 * Restore the original watchpoint if we've completed the
789 if (info->trigger != pc)
790 disable_single_step(wp);
797 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
800 u32 ctrl_reg, val, addr;
801 struct perf_event *bp, **slots;
802 struct arch_hw_breakpoint *info;
803 struct arch_hw_breakpoint_ctrl ctrl;
805 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
807 /* The exception entry code places the amended lr in the PC. */
810 /* Check the currently installed breakpoints first. */
811 for (i = 0; i < core_num_brps; ++i) {
819 info = counter_arch_bp(bp);
821 /* Check if the breakpoint value matches. */
822 val = read_wb_reg(ARM_BASE_BVR + i);
823 if (val != (addr & ~0x3))
826 /* Possible match, check the byte address select to confirm. */
827 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
828 decode_ctrl_reg(ctrl_reg, &ctrl);
829 if ((1 << (addr & 0x3)) & ctrl.len) {
830 info->trigger = addr;
831 pr_debug("breakpoint fired: address = 0x%x\n", addr);
832 perf_bp_event(bp, regs);
833 if (!bp->overflow_handler)
834 enable_single_step(bp, addr);
839 /* If we're stepping a breakpoint, it can now be restored. */
840 if (info->step_ctrl.enabled)
841 disable_single_step(bp);
846 /* Handle any pending watchpoint single-step breakpoints. */
847 watchpoint_single_step_handler(addr);
851 * Called from either the Data Abort Handler [watchpoint] or the
852 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
854 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
855 struct pt_regs *regs)
862 if (interrupts_enabled(regs))
865 /* We only handle watchpoints and hardware breakpoints. */
866 ARM_DBG_READ(c0, c1, 0, dscr);
868 /* Perform perf callbacks. */
869 switch (ARM_DSCR_MOE(dscr)) {
870 case ARM_ENTRY_BREAKPOINT:
871 breakpoint_handler(addr, regs);
873 case ARM_ENTRY_ASYNC_WATCHPOINT:
874 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
875 case ARM_ENTRY_SYNC_WATCHPOINT:
876 watchpoint_handler(addr, fsr, regs);
879 ret = 1; /* Unhandled fault. */
888 * One-time initialisation.
890 static cpumask_t debug_err_mask;
892 static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
894 int cpu = smp_processor_id();
896 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
899 /* Set the error flag for this CPU and skip the faulting instruction. */
900 cpumask_set_cpu(cpu, &debug_err_mask);
901 instruction_pointer(regs) += 4;
905 static struct undef_hook debug_reg_hook = {
906 .instr_mask = 0x0fe80f10,
907 .instr_val = 0x0e000e10,
908 .fn = debug_reg_trap,
911 /* Does this core support OS Save and Restore? */
912 static bool core_has_os_save_restore(void)
916 switch (get_debug_arch()) {
917 case ARM_DEBUG_ARCH_V7_1:
919 case ARM_DEBUG_ARCH_V7_ECP14:
920 ARM_DBG_READ(c1, c1, 4, oslsr);
921 if (oslsr & ARM_OSLSR_OSLM0)
928 static void reset_ctrl_regs(void *unused)
930 int i, raw_num_brps, err = 0, cpu = smp_processor_id();
934 * v7 debug contains save and restore registers so that debug state
935 * can be maintained across low-power modes without leaving the debug
936 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
937 * the debug registers out of reset, so we must unlock the OS Lock
938 * Access Register to avoid taking undefined instruction exceptions
941 switch (debug_arch) {
942 case ARM_DEBUG_ARCH_V6:
943 case ARM_DEBUG_ARCH_V6_1:
944 /* ARMv6 cores clear the registers out of reset. */
946 case ARM_DEBUG_ARCH_V7_ECP14:
948 * Ensure sticky power-down is clear (i.e. debug logic is
951 ARM_DBG_READ(c1, c5, 4, val);
952 if ((val & 0x1) == 0)
958 case ARM_DEBUG_ARCH_V7_1:
960 * Ensure the OS double lock is clear.
962 ARM_DBG_READ(c1, c3, 4, val);
963 if ((val & 0x1) == 1)
969 pr_warn_once("CPU %d debug is powered down!\n", cpu);
970 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
975 * Unconditionally clear the OS lock by writing a value
976 * other than CS_LAR_KEY to the access register.
978 ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY);
982 * Clear any configured vector-catch events before
983 * enabling monitor mode.
986 ARM_DBG_WRITE(c0, c7, 0, 0);
989 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
990 pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
995 * The control/value register pairs are UNKNOWN out of reset so
996 * clear them to avoid spurious debug events.
998 raw_num_brps = get_num_brp_resources();
999 for (i = 0; i < raw_num_brps; ++i) {
1000 write_wb_reg(ARM_BASE_BCR + i, 0UL);
1001 write_wb_reg(ARM_BASE_BVR + i, 0UL);
1004 for (i = 0; i < core_num_wrps; ++i) {
1005 write_wb_reg(ARM_BASE_WCR + i, 0UL);
1006 write_wb_reg(ARM_BASE_WVR + i, 0UL);
1009 if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
1010 pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
1015 * Have a crack at enabling monitor mode. We don't actually need
1016 * it yet, but reporting an error early is useful if it fails.
1019 if (enable_monitor_mode())
1020 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
1023 static int __cpuinit dbg_reset_notify(struct notifier_block *self,
1024 unsigned long action, void *cpu)
1026 if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
1027 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
1032 static struct notifier_block __cpuinitdata dbg_reset_nb = {
1033 .notifier_call = dbg_reset_notify,
1036 #ifdef CONFIG_CPU_PM
1037 static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
1040 if (action == CPU_PM_EXIT)
1041 reset_ctrl_regs(NULL);
1046 static struct notifier_block dbg_cpu_pm_nb = {
1047 .notifier_call = dbg_cpu_pm_notify,
1050 static void __init pm_init(void)
1053 cpu_pm_register_notifier(&dbg_cpu_pm_nb);
1056 static inline void pm_init(void)
1061 static int __init arch_hw_breakpoint_init(void)
1063 debug_arch = get_debug_arch();
1065 if (!debug_arch_supported()) {
1066 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
1070 has_ossr = core_has_os_save_restore();
1072 /* Determine how many BRPs/WRPs are available. */
1073 core_num_brps = get_num_brps();
1074 core_num_wrps = get_num_wrps();
1077 * We need to tread carefully here because DBGSWENABLE may be
1078 * driven low on this core and there isn't an architected way to
1081 register_undef_hook(&debug_reg_hook);
1084 * Reset the breakpoint resources. We assume that a halting
1085 * debugger will leave the world in a nice state for us.
1087 on_each_cpu(reset_ctrl_regs, NULL, 1);
1088 unregister_undef_hook(&debug_reg_hook);
1089 if (!cpumask_empty(&debug_err_mask)) {
1095 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1096 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1099 /* Work out the maximum supported watchpoint length. */
1100 max_watchpoint_len = get_max_wp_len();
1101 pr_info("maximum watchpoint size is %u bytes.\n",
1102 max_watchpoint_len);
1104 /* Register debug fault handler. */
1105 hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1106 TRAP_HWBKPT, "watchpoint debug exception");
1107 hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
1108 TRAP_HWBKPT, "breakpoint debug exception");
1110 /* Register hotplug and PM notifiers. */
1111 register_cpu_notifier(&dbg_reset_nb);
1115 arch_initcall(arch_hw_breakpoint_init);
1117 void hw_breakpoint_pmu_read(struct perf_event *bp)
1122 * Dummy function to register with die_notifier.
1124 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
1125 unsigned long val, void *data)