1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
6 #define CPU_ARCH_UNKNOWN 0
7 #define CPU_ARCH_ARMv3 1
8 #define CPU_ARCH_ARMv4 2
9 #define CPU_ARCH_ARMv4T 3
10 #define CPU_ARCH_ARMv5 4
11 #define CPU_ARCH_ARMv5T 5
12 #define CPU_ARCH_ARMv5TE 6
13 #define CPU_ARCH_ARMv5TEJ 7
14 #define CPU_ARCH_ARMv6 8
15 #define CPU_ARCH_ARMv7 9
18 * This is used to ensure the compiler did actually allocate the register we
19 * asked it for some inline assembly sequences. Apparently we can't trust
20 * the compiler from one version to another so a bit of paranoia won't hurt.
21 * This string is meant to be concatenated with the inline asm string and
22 * will cause compilation to stop on mismatch.
23 * (for details, see gcc PR 15089)
25 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
29 #include <linux/compiler.h>
30 #include <linux/linkage.h>
31 #include <linux/irqflags.h>
33 #include <asm/outercache.h>
38 /* information about the system we're running on */
39 extern unsigned int system_rev;
40 extern unsigned int system_serial_low;
41 extern unsigned int system_serial_high;
42 extern unsigned int mem_fclk_21285;
46 void die(const char *msg, struct pt_regs *regs, int err);
49 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
50 unsigned long err, unsigned long trap);
52 #ifdef CONFIG_ARM_LPAE
53 #define FAULT_CODE_ALIGNMENT 33
54 #define FAULT_CODE_DEBUG 34
56 #define FAULT_CODE_ALIGNMENT 1
57 #define FAULT_CODE_DEBUG 2
60 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
62 int sig, int code, const char *name);
64 void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
66 int sig, int code, const char *name);
69 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
71 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
74 extern void show_pte(struct mm_struct *mm, unsigned long addr);
75 extern void __show_regs(struct pt_regs *);
77 extern int __pure cpu_architecture(void);
78 extern void cpu_init(void);
80 void soft_restart(unsigned long);
81 extern void (*arm_pm_restart)(char str, const char *cmd);
82 extern void (*arm_pm_idle)(void);
84 #define UDBG_UNDEFINED (1 << 0)
85 #define UDBG_SYSCALL (1 << 1)
86 #define UDBG_BADABORT (1 << 2)
87 #define UDBG_SEGV (1 << 3)
88 #define UDBG_BUS (1 << 4)
90 extern unsigned int user_debug;
92 #if __LINUX_ARM_ARCH__ >= 7 || \
93 (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
94 #define sev() __asm__ __volatile__ ("sev" : : : "memory")
95 #define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
96 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
99 #if __LINUX_ARM_ARCH__ >= 7
100 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
101 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
102 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
103 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
104 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
105 : : "r" (0) : "memory")
106 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
107 : : "r" (0) : "memory")
108 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
109 : : "r" (0) : "memory")
110 #elif defined(CONFIG_CPU_FA526)
111 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
112 : : "r" (0) : "memory")
113 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
114 : : "r" (0) : "memory")
115 #define dmb() __asm__ __volatile__ ("" : : : "memory")
117 #define isb() __asm__ __volatile__ ("" : : : "memory")
118 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
119 : : "r" (0) : "memory")
120 #define dmb() __asm__ __volatile__ ("" : : : "memory")
123 #ifdef CONFIG_ARCH_HAS_BARRIERS
124 #include <mach/barriers.h>
125 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
126 #define mb() do { dsb(); outer_sync(); } while (0)
130 #include <asm/memory.h>
131 #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
132 #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
133 #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
137 #define smp_mb() barrier()
138 #define smp_rmb() barrier()
139 #define smp_wmb() barrier()
141 #define smp_mb() dmb()
142 #define smp_rmb() dmb()
143 #define smp_wmb() dmb()
146 #define read_barrier_depends() do { } while(0)
147 #define smp_read_barrier_depends() do { } while(0)
149 #define set_mb(var, value) do { var = value; smp_mb(); } while (0)
150 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
153 * switch_mm() may do a full cache flush over the context switch,
154 * so enable interrupts over the context switch to avoid high
157 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
160 * switch_to(prev, next) should switch from task `prev' to `next'
161 * `prev' will never be the same as `next'. schedule() itself
162 * contains the memory barrier to tell GCC not to cache `current'.
164 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
166 #define switch_to(prev,next,last) \
168 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
171 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
173 * On the StrongARM, "swp" is terminally broken since it bypasses the
174 * cache totally. This means that the cache becomes inconsistent, and,
175 * since we use normal loads/stores as well, this is really bad.
176 * Typically, this causes oopsen in filp_close, but could have other,
177 * more disastrous effects. There are two work-arounds:
178 * 1. Disable interrupts and emulate the atomic swap
179 * 2. Clean the cache, perform atomic swap, flush the cache
181 * We choose (1) since its the "easiest" to achieve here and is not
182 * dependent on the processor type.
184 * NOTE that this solution won't work on an SMP system, so explcitly
190 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
192 extern void __bad_xchg(volatile void *, int);
197 #if __LINUX_ARM_ARCH__ >= 6
204 #if __LINUX_ARM_ARCH__ >= 6
206 asm volatile("@ __xchg1\n"
207 "1: ldrexb %0, [%3]\n"
208 " strexb %1, %2, [%3]\n"
211 : "=&r" (ret), "=&r" (tmp)
216 asm volatile("@ __xchg4\n"
217 "1: ldrex %0, [%3]\n"
218 " strex %1, %2, [%3]\n"
221 : "=&r" (ret), "=&r" (tmp)
225 #elif defined(swp_is_buggy)
227 #error SMP is not supported on this platform
230 raw_local_irq_save(flags);
231 ret = *(volatile unsigned char *)ptr;
232 *(volatile unsigned char *)ptr = x;
233 raw_local_irq_restore(flags);
237 raw_local_irq_save(flags);
238 ret = *(volatile unsigned long *)ptr;
239 *(volatile unsigned long *)ptr = x;
240 raw_local_irq_restore(flags);
244 asm volatile("@ __xchg1\n"
251 asm volatile("@ __xchg4\n"
259 __bad_xchg(ptr, size), ret = 0;
267 extern void disable_hlt(void);
268 extern void enable_hlt(void);
270 void cpu_idle_wait(void);
272 #include <asm-generic/cmpxchg-local.h>
274 #if __LINUX_ARM_ARCH__ < 6
275 /* min ARCH < ARMv6 */
278 #error "SMP is not supported on this platform"
282 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
285 #define cmpxchg_local(ptr, o, n) \
286 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
287 (unsigned long)(n), sizeof(*(ptr))))
288 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
291 #include <asm-generic/cmpxchg.h>
294 #else /* min ARCH >= ARMv6 */
296 extern void __bad_cmpxchg(volatile void *ptr, int size);
299 * cmpxchg only support 32-bits operands on ARMv6.
302 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
303 unsigned long new, int size)
305 unsigned long oldval, res;
308 #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
311 asm volatile("@ __cmpxchg1\n"
315 " strexbeq %0, %4, [%2]\n"
316 : "=&r" (res), "=&r" (oldval)
317 : "r" (ptr), "Ir" (old), "r" (new)
323 asm volatile("@ __cmpxchg1\n"
327 " strexheq %0, %4, [%2]\n"
328 : "=&r" (res), "=&r" (oldval)
329 : "r" (ptr), "Ir" (old), "r" (new)
336 asm volatile("@ __cmpxchg4\n"
340 " strexeq %0, %4, [%2]\n"
341 : "=&r" (res), "=&r" (oldval)
342 : "r" (ptr), "Ir" (old), "r" (new)
347 __bad_cmpxchg(ptr, size);
354 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
355 unsigned long new, int size)
360 ret = __cmpxchg(ptr, old, new, size);
366 #define cmpxchg(ptr,o,n) \
367 ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
368 (unsigned long)(o), \
369 (unsigned long)(n), \
372 static inline unsigned long __cmpxchg_local(volatile void *ptr,
374 unsigned long new, int size)
379 #ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
382 ret = __cmpxchg_local_generic(ptr, old, new, size);
386 ret = __cmpxchg(ptr, old, new, size);
392 #define cmpxchg_local(ptr,o,n) \
393 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
394 (unsigned long)(o), \
395 (unsigned long)(n), \
398 #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
401 * Note : ARMv7-M (currently unsupported by Linux) does not support
402 * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
403 * not be allowed to use __cmpxchg64.
405 static inline unsigned long long __cmpxchg64(volatile void *ptr,
406 unsigned long long old,
407 unsigned long long new)
409 register unsigned long long oldval asm("r0");
410 register unsigned long long __old asm("r2") = old;
411 register unsigned long long __new asm("r4") = new;
417 " ldrexd %1, %H1, [%2]\n"
421 " strexdeq %0, %4, %H4, [%2]\n"
422 : "=&r" (res), "=&r" (oldval)
423 : "r" (ptr), "Ir" (__old), "r" (__new)
430 static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
431 unsigned long long old,
432 unsigned long long new)
434 unsigned long long ret;
437 ret = __cmpxchg64(ptr, old, new);
443 #define cmpxchg64(ptr,o,n) \
444 ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
445 (unsigned long long)(o), \
446 (unsigned long long)(n)))
448 #define cmpxchg64_local(ptr,o,n) \
449 ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
450 (unsigned long long)(o), \
451 (unsigned long long)(n)))
453 #else /* min ARCH = ARMv6 */
455 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
459 #endif /* __LINUX_ARM_ARCH__ >= 6 */
461 #endif /* __ASSEMBLY__ */
463 #define arch_align_stack(x) (x)
465 #endif /* __KERNEL__ */