2 * arch/arm/include/asm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
16 #include <asm/shmparam.h>
17 #include <asm/cachetype.h>
19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
28 #if defined(CONFIG_CPU_CACHE_V3)
30 # define MULTI_CACHE 1
36 #if defined(CONFIG_CPU_CACHE_V4)
38 # define MULTI_CACHE 1
44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
46 # define MULTI_CACHE 1
49 #if defined(CONFIG_CPU_FA526)
51 # define MULTI_CACHE 1
57 #if defined(CONFIG_CPU_ARM926T)
59 # define MULTI_CACHE 1
61 # define _CACHE arm926
65 #if defined(CONFIG_CPU_ARM940T)
67 # define MULTI_CACHE 1
69 # define _CACHE arm940
73 #if defined(CONFIG_CPU_ARM946E)
75 # define MULTI_CACHE 1
77 # define _CACHE arm946
81 #if defined(CONFIG_CPU_CACHE_V4WB)
83 # define MULTI_CACHE 1
89 #if defined(CONFIG_CPU_XSCALE)
91 # define MULTI_CACHE 1
93 # define _CACHE xscale
97 #if defined(CONFIG_CPU_XSC3)
99 # define MULTI_CACHE 1
105 #if defined(CONFIG_CPU_MOHAWK)
107 # define MULTI_CACHE 1
109 # define _CACHE mohawk
113 #if defined(CONFIG_CPU_FEROCEON)
114 # define MULTI_CACHE 1
117 #if defined(CONFIG_CPU_V6)
119 # define MULTI_CACHE 1
125 #if defined(CONFIG_CPU_V7)
127 # define MULTI_CACHE 1
133 #if !defined(_CACHE) && !defined(MULTI_CACHE)
134 #error Unknown cache maintainence model
138 * This flag is used to indicate that the page pointed to by a pte
139 * is dirty and requires cleaning before returning it to the user.
141 #define PG_dcache_dirty PG_arch_1
144 * MM Cache Management
145 * ===================
147 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
148 * implement these methods.
150 * Start addresses are inclusive and end addresses are exclusive;
151 * start addresses should be rounded down, end addresses up.
153 * See Documentation/cachetlb.txt for more information.
154 * Please note that the implementation of these, and the required
155 * effects are cache-type (VIVT/VIPT/PIPT) specific.
157 * flush_cache_kern_all()
159 * Unconditionally clean and invalidate the entire cache.
161 * flush_cache_user_mm(mm)
163 * Clean and invalidate all user space cache entries
164 * before a change of page tables.
166 * flush_cache_user_range(start, end, flags)
168 * Clean and invalidate a range of cache entries in the
169 * specified address space before a change of page tables.
170 * - start - user start address (inclusive, page aligned)
171 * - end - user end address (exclusive, page aligned)
172 * - flags - vma->vm_flags field
174 * coherent_kern_range(start, end)
176 * Ensure coherency between the Icache and the Dcache in the
177 * region described by start, end. If you have non-snooping
178 * Harvard caches, you need to implement this function.
179 * - start - virtual start address
180 * - end - virtual end address
182 * DMA Cache Coherency
183 * ===================
185 * dma_flush_range(start, end)
187 * Clean and invalidate the specified virtual address range.
188 * - start - virtual start address
189 * - end - virtual end address
192 struct cpu_cache_fns {
193 void (*flush_kern_all)(void);
194 void (*flush_user_all)(void);
195 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
197 void (*coherent_kern_range)(unsigned long, unsigned long);
198 void (*coherent_user_range)(unsigned long, unsigned long);
199 void (*flush_kern_dcache_area)(void *, size_t);
201 void (*dma_map_area)(const void *, size_t, int);
202 void (*dma_unmap_area)(const void *, size_t, int);
204 void (*dma_flush_range)(const void *, const void *);
207 struct outer_cache_fns {
208 void (*inv_range)(unsigned long, unsigned long);
209 void (*clean_range)(unsigned long, unsigned long);
210 void (*flush_range)(unsigned long, unsigned long);
214 * Select the calling method
218 extern struct cpu_cache_fns cpu_cache;
220 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
221 #define __cpuc_flush_user_all cpu_cache.flush_user_all
222 #define __cpuc_flush_user_range cpu_cache.flush_user_range
223 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
224 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
225 #define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
228 * These are private to the dma-mapping API. Do not use directly.
229 * Their sole purpose is to ensure that data held in the cache
230 * is visible to DMA, or data written by DMA to system memory is
231 * visible to the CPU.
233 #define dmac_map_area cpu_cache.dma_map_area
234 #define dmac_unmap_area cpu_cache.dma_unmap_area
235 #define dmac_flush_range cpu_cache.dma_flush_range
239 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
240 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
241 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
242 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
243 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
244 #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
246 extern void __cpuc_flush_kern_all(void);
247 extern void __cpuc_flush_user_all(void);
248 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
249 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
250 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
251 extern void __cpuc_flush_dcache_area(void *, size_t);
254 * These are private to the dma-mapping API. Do not use directly.
255 * Their sole purpose is to ensure that data held in the cache
256 * is visible to DMA, or data written by DMA to system memory is
257 * visible to the CPU.
259 #define dmac_map_area __glue(_CACHE,_dma_map_area)
260 #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
261 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
263 extern void dmac_map_area(const void *, size_t, int);
264 extern void dmac_unmap_area(const void *, size_t, int);
265 extern void dmac_flush_range(const void *, const void *);
269 #ifdef CONFIG_OUTER_CACHE
271 extern struct outer_cache_fns outer_cache;
273 static inline void outer_inv_range(unsigned long start, unsigned long end)
275 if (outer_cache.inv_range)
276 outer_cache.inv_range(start, end);
278 static inline void outer_clean_range(unsigned long start, unsigned long end)
280 if (outer_cache.clean_range)
281 outer_cache.clean_range(start, end);
283 static inline void outer_flush_range(unsigned long start, unsigned long end)
285 if (outer_cache.flush_range)
286 outer_cache.flush_range(start, end);
291 static inline void outer_inv_range(unsigned long start, unsigned long end)
293 static inline void outer_clean_range(unsigned long start, unsigned long end)
295 static inline void outer_flush_range(unsigned long start, unsigned long end)
301 * Copy user data from/to a page which is mapped into a different
302 * processes address space. Really, we want to allow our "user
303 * space" model to handle this.
305 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
307 memcpy(dst, src, len); \
308 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
311 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
313 memcpy(dst, src, len); \
317 * Convert calls to our calling convention.
319 #define flush_cache_all() __cpuc_flush_kern_all()
321 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
323 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
324 __cpuc_flush_user_all();
328 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
330 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
331 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
336 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
338 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
339 unsigned long addr = user_addr & PAGE_MASK;
340 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
345 vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
346 unsigned long uaddr, void *kaddr,
347 unsigned long len, int write)
349 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
350 unsigned long addr = (unsigned long)kaddr;
351 __cpuc_coherent_kern_range(addr, addr + len);
355 #ifndef CONFIG_CPU_CACHE_VIPT
356 #define flush_cache_mm(mm) \
357 vivt_flush_cache_mm(mm)
358 #define flush_cache_range(vma,start,end) \
359 vivt_flush_cache_range(vma,start,end)
360 #define flush_cache_page(vma,addr,pfn) \
361 vivt_flush_cache_page(vma,addr,pfn)
362 #define flush_ptrace_access(vma,page,ua,ka,len,write) \
363 vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
365 extern void flush_cache_mm(struct mm_struct *mm);
366 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
367 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
368 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
369 unsigned long uaddr, void *kaddr,
370 unsigned long len, int write);
373 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
376 * flush_cache_user_range is used when we want to ensure that the
377 * Harvard caches are synchronised for the user space address range.
378 * This is used for the ARM private sys_cacheflush system call.
380 #define flush_cache_user_range(vma,start,end) \
381 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
384 * Perform necessary cache operations to ensure that data previously
385 * stored within this range of addresses can be executed by the CPU.
387 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
390 * Perform necessary cache operations to ensure that the TLB will
391 * see data written in the specified area.
393 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
396 * flush_dcache_page is used when the kernel has written to the page
397 * cache page at virtual address page->virtual.
399 * If this page isn't mapped (ie, page_mapping == NULL), or it might
400 * have userspace mappings, then we _must_ always clean + invalidate
401 * the dcache entries associated with the kernel mapping.
403 * Otherwise we can defer the operation, and clean the cache when we are
404 * about to change to user space. This is the same method as used on SPARC64.
405 * See update_mmu_cache for the user space part.
407 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
408 extern void flush_dcache_page(struct page *);
410 static inline void __flush_icache_all(void)
412 #ifdef CONFIG_ARM_ERRATA_411920
413 extern void v6_icache_inval_all(void);
414 v6_icache_inval_all();
416 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
422 #define ARCH_HAS_FLUSH_ANON_PAGE
423 static inline void flush_anon_page(struct vm_area_struct *vma,
424 struct page *page, unsigned long vmaddr)
426 extern void __flush_anon_page(struct vm_area_struct *vma,
427 struct page *, unsigned long);
429 __flush_anon_page(vma, page, vmaddr);
432 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
433 static inline void flush_kernel_dcache_page(struct page *page)
435 /* highmem pages are always flushed upon kunmap already */
436 if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
437 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
440 #define flush_dcache_mmap_lock(mapping) \
441 spin_lock_irq(&(mapping)->tree_lock)
442 #define flush_dcache_mmap_unlock(mapping) \
443 spin_unlock_irq(&(mapping)->tree_lock)
445 #define flush_icache_user_range(vma,page,addr,len) \
446 flush_dcache_page(page)
449 * We don't appear to need to do anything here. In fact, if we did, we'd
450 * duplicate cache flushing elsewhere performed by flush_dcache_page().
452 #define flush_icache_page(vma,page) do { } while (0)
455 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
456 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
457 * caches, since the direct-mappings of these pages may contain cached
458 * data, we need to do a full cache flush to ensure that writebacks
459 * don't corrupt data placed into these pages via the new mappings.
461 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
463 if (!cache_is_vipt_nonaliasing())
467 * set_pte_at() called from vmap_pte_range() does not
468 * have a DSB after cleaning the cache line.
473 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
475 if (!cache_is_vipt_nonaliasing())