2 * arch/arm/include/asm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/compiler.h>
15 #include <linux/prefetch.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18 #include <asm/barrier.h>
19 #include <asm/cmpxchg.h>
21 #define ATOMIC_INIT(i) { (i) }
26 * On ARM, ordinary assignment (str instruction) doesn't clear the local
27 * strex/ldrex monitor on some implementations. The reason we can use it for
28 * atomic_set() is the clrex or dummy strex done on every exception return.
30 #define atomic_read(v) (*(volatile int *)&(v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
33 #if __LINUX_ARM_ARCH__ >= 6
36 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
37 * store exclusive to ensure that these are atomic. We may loop
38 * to ensure that the update happens.
40 static inline void atomic_add(int i, atomic_t *v)
45 prefetchw(&v->counter);
46 __asm__ __volatile__("@ atomic_add\n"
49 " strex %1, %0, [%3]\n"
52 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
53 : "r" (&v->counter), "Ir" (i)
57 static inline int atomic_add_return(int i, atomic_t *v)
64 __asm__ __volatile__("@ atomic_add_return\n"
67 " strex %1, %0, [%3]\n"
70 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
71 : "r" (&v->counter), "Ir" (i)
79 static inline void atomic_sub(int i, atomic_t *v)
84 prefetchw(&v->counter);
85 __asm__ __volatile__("@ atomic_sub\n"
88 " strex %1, %0, [%3]\n"
91 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
92 : "r" (&v->counter), "Ir" (i)
96 static inline int atomic_sub_return(int i, atomic_t *v)
103 __asm__ __volatile__("@ atomic_sub_return\n"
104 "1: ldrex %0, [%3]\n"
106 " strex %1, %0, [%3]\n"
109 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
110 : "r" (&v->counter), "Ir" (i)
118 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
126 __asm__ __volatile__("@ atomic_cmpxchg\n"
130 "strexeq %0, %5, [%3]\n"
131 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
132 : "r" (&ptr->counter), "Ir" (old), "r" (new)
141 #else /* ARM_ARCH_6 */
144 #error SMP not supported on pre-ARMv6 CPUs
147 static inline int atomic_add_return(int i, atomic_t *v)
152 raw_local_irq_save(flags);
154 v->counter = val += i;
155 raw_local_irq_restore(flags);
159 #define atomic_add(i, v) (void) atomic_add_return(i, v)
161 static inline int atomic_sub_return(int i, atomic_t *v)
166 raw_local_irq_save(flags);
168 v->counter = val -= i;
169 raw_local_irq_restore(flags);
173 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
175 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
180 raw_local_irq_save(flags);
182 if (likely(ret == old))
184 raw_local_irq_restore(flags);
189 #endif /* __LINUX_ARM_ARCH__ */
191 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
193 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
198 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
203 #define atomic_inc(v) atomic_add(1, v)
204 #define atomic_dec(v) atomic_sub(1, v)
206 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
207 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
208 #define atomic_inc_return(v) (atomic_add_return(1, v))
209 #define atomic_dec_return(v) (atomic_sub_return(1, v))
210 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
212 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
214 #define smp_mb__before_atomic_dec() smp_mb()
215 #define smp_mb__after_atomic_dec() smp_mb()
216 #define smp_mb__before_atomic_inc() smp_mb()
217 #define smp_mb__after_atomic_inc() smp_mb()
219 #ifndef CONFIG_GENERIC_ATOMIC64
224 #define ATOMIC64_INIT(i) { (i) }
226 #ifdef CONFIG_ARM_LPAE
227 static inline long long atomic64_read(const atomic64_t *v)
231 __asm__ __volatile__("@ atomic64_read\n"
232 " ldrd %0, %H0, [%1]"
234 : "r" (&v->counter), "Qo" (v->counter)
240 static inline void atomic64_set(atomic64_t *v, long long i)
242 __asm__ __volatile__("@ atomic64_set\n"
243 " strd %2, %H2, [%1]"
245 : "r" (&v->counter), "r" (i)
249 static inline long long atomic64_read(const atomic64_t *v)
253 __asm__ __volatile__("@ atomic64_read\n"
254 " ldrexd %0, %H0, [%1]"
256 : "r" (&v->counter), "Qo" (v->counter)
262 static inline void atomic64_set(atomic64_t *v, long long i)
266 prefetchw(&v->counter);
267 __asm__ __volatile__("@ atomic64_set\n"
268 "1: ldrexd %0, %H0, [%2]\n"
269 " strexd %0, %3, %H3, [%2]\n"
272 : "=&r" (tmp), "=Qo" (v->counter)
273 : "r" (&v->counter), "r" (i)
278 static inline void atomic64_add(long long i, atomic64_t *v)
283 prefetchw(&v->counter);
284 __asm__ __volatile__("@ atomic64_add\n"
285 "1: ldrexd %0, %H0, [%3]\n"
286 " adds %Q0, %Q0, %Q4\n"
287 " adc %R0, %R0, %R4\n"
288 " strexd %1, %0, %H0, [%3]\n"
291 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
292 : "r" (&v->counter), "r" (i)
296 static inline long long atomic64_add_return(long long i, atomic64_t *v)
303 __asm__ __volatile__("@ atomic64_add_return\n"
304 "1: ldrexd %0, %H0, [%3]\n"
305 " adds %Q0, %Q0, %Q4\n"
306 " adc %R0, %R0, %R4\n"
307 " strexd %1, %0, %H0, [%3]\n"
310 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
311 : "r" (&v->counter), "r" (i)
319 static inline void atomic64_sub(long long i, atomic64_t *v)
324 prefetchw(&v->counter);
325 __asm__ __volatile__("@ atomic64_sub\n"
326 "1: ldrexd %0, %H0, [%3]\n"
327 " subs %Q0, %Q0, %Q4\n"
328 " sbc %R0, %R0, %R4\n"
329 " strexd %1, %0, %H0, [%3]\n"
332 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
333 : "r" (&v->counter), "r" (i)
337 static inline long long atomic64_sub_return(long long i, atomic64_t *v)
344 __asm__ __volatile__("@ atomic64_sub_return\n"
345 "1: ldrexd %0, %H0, [%3]\n"
346 " subs %Q0, %Q0, %Q4\n"
347 " sbc %R0, %R0, %R4\n"
348 " strexd %1, %0, %H0, [%3]\n"
351 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
352 : "r" (&v->counter), "r" (i)
360 static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
369 __asm__ __volatile__("@ atomic64_cmpxchg\n"
370 "ldrexd %1, %H1, [%3]\n"
374 "strexdeq %0, %5, %H5, [%3]"
375 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
376 : "r" (&ptr->counter), "r" (old), "r" (new)
385 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
392 __asm__ __volatile__("@ atomic64_xchg\n"
393 "1: ldrexd %0, %H0, [%3]\n"
394 " strexd %1, %4, %H4, [%3]\n"
397 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
398 : "r" (&ptr->counter), "r" (new)
406 static inline long long atomic64_dec_if_positive(atomic64_t *v)
413 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
414 "1: ldrexd %0, %H0, [%3]\n"
415 " subs %Q0, %Q0, #1\n"
416 " sbc %R0, %R0, #0\n"
419 " strexd %1, %0, %H0, [%3]\n"
423 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
432 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
440 __asm__ __volatile__("@ atomic64_add_unless\n"
441 "1: ldrexd %0, %H0, [%4]\n"
446 " adds %Q0, %Q0, %Q6\n"
447 " adc %R0, %R0, %R6\n"
448 " strexd %2, %0, %H0, [%4]\n"
452 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
453 : "r" (&v->counter), "r" (u), "r" (a)
462 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
463 #define atomic64_inc(v) atomic64_add(1LL, (v))
464 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
465 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
466 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
467 #define atomic64_dec(v) atomic64_sub(1LL, (v))
468 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
469 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
470 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
472 #endif /* !CONFIG_GENERIC_ATOMIC64 */