arch/arm/common/timer-sp.c

   1 /*
   2  *  linux/arch/arm/common/timer-sp.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/clk.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/clockchips.h>
  24 #include <linux/err.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/sched_clock.h>
  32
  33 #include <asm/hardware/arm_timer.h>
  34 #include <asm/hardware/timer-sp.h>
  35
  36 static long __init sp804_get_clock_rate(struct clk *clk)
  37 {
  38         long rate;
  39         int err;
  40
  41         err = clk_prepare(clk);
  42         if (err) {
  43                 pr_err("sp804: clock failed to prepare: %d\n", err);
  44                 clk_put(clk);
  45                 return err;
  46         }
  47
  48         err = clk_enable(clk);
  49         if (err) {
  50                 pr_err("sp804: clock failed to enable: %d\n", err);
  51                 clk_unprepare(clk);
  52                 clk_put(clk);
  53                 return err;
  54         }
  55
  56         rate = clk_get_rate(clk);
  57         if (rate < 0) {
  58                 pr_err("sp804: clock failed to get rate: %ld\n", rate);
  59                 clk_disable(clk);
  60                 clk_unprepare(clk);
  61                 clk_put(clk);
  62         }
  63
  64         return rate;
  65 }
  66
  67 static void __iomem *sched_clock_base;
  68
  69 static u64 notrace sp804_read(void)
  70 {
  71         return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
  72 }
  73
  74 void __init sp804_timer_disable(void __iomem *base)
  75 {
  76         writel(0, base + TIMER_CTRL);
  77 }
  78
  79 void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
  80                                                      const char *name,
  81                                                      struct clk *clk,
  82                                                      int use_sched_clock)
  83 {
  84         long rate;
  85
  86         if (!clk) {
  87                 clk = clk_get_sys("sp804", name);
  88                 if (IS_ERR(clk)) {
  89                         pr_err("sp804: clock not found: %d\n",
  90                                (int)PTR_ERR(clk));
  91                         return;
  92                 }
  93         }
  94
  95         rate = sp804_get_clock_rate(clk);
  96
  97         if (rate < 0)
  98                 return;
  99
 100         /* setup timer 0 as free-running clocksource */
 101         writel(0, base + TIMER_CTRL);
 102         writel(0xffffffff, base + TIMER_LOAD);
 103         writel(0xffffffff, base + TIMER_VALUE);
 104         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 105                 base + TIMER_CTRL);
 106
 107         clocksource_mmio_init(base + TIMER_VALUE, name,
 108                 rate, 200, 32, clocksource_mmio_readl_down);
 109
 110         if (use_sched_clock) {
 111                 sched_clock_base = base;
 112                 sched_clock_register(sp804_read, 32, rate);
 113         }
 114 }
 115
 116
 117 static void __iomem *clkevt_base;
 118 static unsigned long clkevt_reload;
 119
 120 /*
 121  * IRQ handler for the timer
 122  */
 123 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
 124 {
 125         struct clock_event_device *evt = dev_id;
 126
 127         /* clear the interrupt */
 128         writel(1, clkevt_base + TIMER_INTCLR);
 129
 130         evt->event_handler(evt);
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static void sp804_set_mode(enum clock_event_mode mode,
 136         struct clock_event_device *evt)
 137 {
 138         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 139
 140         writel(ctrl, clkevt_base + TIMER_CTRL);
 141
 142         switch (mode) {
 143         case CLOCK_EVT_MODE_PERIODIC:
 144                 writel(clkevt_reload, clkevt_base + TIMER_LOAD);
 145                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 146                 break;
 147
 148         case CLOCK_EVT_MODE_ONESHOT:
 149                 /* period set, and timer enabled in 'next_event' hook */
 150                 ctrl |= TIMER_CTRL_ONESHOT;
 151                 break;
 152
 153         case CLOCK_EVT_MODE_UNUSED:
 154         case CLOCK_EVT_MODE_SHUTDOWN:
 155         default:
 156                 break;
 157         }
 158
 159         writel(ctrl, clkevt_base + TIMER_CTRL);
 160 }
 161
 162 static int sp804_set_next_event(unsigned long next,
 163         struct clock_event_device *evt)
 164 {
 165         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 166
 167         writel(next, clkevt_base + TIMER_LOAD);
 168         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 169
 170         return 0;
 171 }
 172
 173 static struct clock_event_device sp804_clockevent = {
 174         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
 175                 CLOCK_EVT_FEAT_DYNIRQ,
 176         .set_mode       = sp804_set_mode,
 177         .set_next_event = sp804_set_next_event,
 178         .rating         = 300,
 179 };
 180
 181 static struct irqaction sp804_timer_irq = {
 182         .name           = "timer",
 183         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 184         .handler        = sp804_timer_interrupt,
 185         .dev_id         = &sp804_clockevent,
 186 };
 187
 188 void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
 189 {
 190         struct clock_event_device *evt = &sp804_clockevent;
 191         long rate;
 192
 193         if (!clk)
 194                 clk = clk_get_sys("sp804", name);
 195         if (IS_ERR(clk)) {
 196                 pr_err("sp804: %s clock not found: %d\n", name,
 197                         (int)PTR_ERR(clk));
 198                 return;
 199         }
 200
 201         rate = sp804_get_clock_rate(clk);
 202         if (rate < 0)
 203                 return;
 204
 205         clkevt_base = base;
 206         clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
 207         evt->name = name;
 208         evt->irq = irq;
 209         evt->cpumask = cpu_possible_mask;
 210
 211         writel(0, base + TIMER_CTRL);
 212
 213         setup_irq(irq, &sp804_timer_irq);
 214         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 215 }
 216
 217 static void __init sp804_of_init(struct device_node *np)
 218 {
 219         static bool initialized = false;
 220         void __iomem *base;
 221         int irq;
 222         u32 irq_num = 0;
 223         struct clk *clk1, *clk2;
 224         const char *name = of_get_property(np, "compatible", NULL);
 225
 226         base = of_iomap(np, 0);
 227         if (WARN_ON(!base))
 228                 return;
 229
 230         /* Ensure timers are disabled */
 231         writel(0, base + TIMER_CTRL);
 232         writel(0, base + TIMER_2_BASE + TIMER_CTRL);
 233
 234         if (initialized || !of_device_is_available(np))
 235                 goto err;
 236
 237         clk1 = of_clk_get(np, 0);
 238         if (IS_ERR(clk1))
 239                 clk1 = NULL;
 240
 241         /* Get the 2nd clock if the timer has 3 timer clocks */
 242         if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
 243                 clk2 = of_clk_get(np, 1);
 244                 if (IS_ERR(clk2)) {
 245                         pr_err("sp804: %s clock not found: %d\n", np->name,
 246                                 (int)PTR_ERR(clk2));
 247                         clk2 = NULL;
 248                 }
 249         } else
 250                 clk2 = clk1;
 251
 252         irq = irq_of_parse_and_map(np, 0);
 253         if (irq <= 0)
 254                 goto err;
 255
 256         of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
 257         if (irq_num == 2) {
 258                 __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
 259                 __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
 260         } else {
 261                 __sp804_clockevents_init(base, irq, clk1 , name);
 262                 __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
 263                                                          name, clk2, 1);
 264         }
 265         initialized = true;
 266
 267         return;
 268 err:
 269         iounmap(base);
 270 }
 271 CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
 272
 273 static void __init integrator_cp_of_init(struct device_node *np)
 274 {
 275         static int init_count = 0;
 276         void __iomem *base;
 277         int irq;
 278         const char *name = of_get_property(np, "compatible", NULL);
 279         struct clk *clk;
 280
 281         base = of_iomap(np, 0);
 282         if (WARN_ON(!base))
 283                 return;
 284         clk = of_clk_get(np, 0);
 285         if (WARN_ON(IS_ERR(clk)))
 286                 return;
 287
 288         /* Ensure timer is disabled */
 289         writel(0, base + TIMER_CTRL);
 290
 291         if (init_count == 2 || !of_device_is_available(np))
 292                 goto err;
 293
 294         if (!init_count)
 295                 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
 296         else {
 297                 irq = irq_of_parse_and_map(np, 0);
 298                 if (irq <= 0)
 299                         goto err;
 300
 301                 __sp804_clockevents_init(base, irq, clk, name);
 302         }
 303
 304         init_count++;
 305         return;
 306 err:
 307         iounmap(base);
 308 }
 309 CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);