2 * linux/arch/arm/common/it8152.c
4 * Copyright Compulab Ltd, 2002-2007
5 * Mike Rapoport <mike@compulab.co.il>
7 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
8 * (see this file for respective copyrights)
10 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/ptrace.h>
22 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/irq.h>
28 #include <linux/export.h>
30 #include <asm/mach/pci.h>
31 #include <asm/hardware/it8152.h>
35 static void it8152_mask_irq(struct irq_data *d)
37 unsigned int irq = d->irq;
39 if (irq >= IT8152_LD_IRQ(0)) {
40 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
41 (1 << (irq - IT8152_LD_IRQ(0)))),
43 } else if (irq >= IT8152_LP_IRQ(0)) {
44 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
45 (1 << (irq - IT8152_LP_IRQ(0)))),
47 } else if (irq >= IT8152_PD_IRQ(0)) {
48 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
49 (1 << (irq - IT8152_PD_IRQ(0)))),
54 static void it8152_unmask_irq(struct irq_data *d)
56 unsigned int irq = d->irq;
58 if (irq >= IT8152_LD_IRQ(0)) {
59 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
60 ~(1 << (irq - IT8152_LD_IRQ(0)))),
62 } else if (irq >= IT8152_LP_IRQ(0)) {
63 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
64 ~(1 << (irq - IT8152_LP_IRQ(0)))),
66 } else if (irq >= IT8152_PD_IRQ(0)) {
67 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
68 ~(1 << (irq - IT8152_PD_IRQ(0)))),
73 static struct irq_chip it8152_irq_chip = {
75 .irq_ack = it8152_mask_irq,
76 .irq_mask = it8152_mask_irq,
77 .irq_unmask = it8152_unmask_irq,
80 void it8152_init_irq(void)
84 __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
85 __raw_writel((0), IT8152_INTC_PDCNIRR);
86 __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
87 __raw_writel((0), IT8152_INTC_LPCNIRR);
88 __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
89 __raw_writel((0), IT8152_INTC_LDCNIRR);
91 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
92 irq_set_chip_and_handler(irq, &it8152_irq_chip,
94 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
98 void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
100 int bits_pd, bits_lp, bits_ld;
105 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
106 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
107 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
110 __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
111 __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
112 __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
114 if (!(bits_ld | bits_lp | bits_pd)) {
115 /* Re-read to guarantee, that there was a moment of
116 time, when they all three were 0. */
117 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
118 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
119 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
120 if (!(bits_ld | bits_lp | bits_pd))
124 bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
127 generic_handle_irq(IT8152_PD_IRQ(i));
128 bits_pd &= ~(1 << i);
131 bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
134 generic_handle_irq(IT8152_LP_IRQ(i));
135 bits_lp &= ~(1 << i);
138 bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
141 generic_handle_irq(IT8152_LD_IRQ(i));
142 bits_ld &= ~(1 << i);
147 /* mapping for on-chip devices */
148 int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
150 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
151 (dev->device == PCI_DEVICE_ID_ITE_8152)) {
152 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
153 return IT8152_AUDIO_INT;
154 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
155 return IT8152_USB_INT;
156 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
157 return IT8152_CDMA_INT;
163 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
166 unsigned long addr = 0;
168 if (bus->number == 0) {
169 if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
172 addr = (bus->number << 16) | (devfn << 8);
177 static int it8152_pci_read_config(struct pci_bus *bus,
178 unsigned int devfn, int where,
179 int size, u32 *value)
181 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
187 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
188 v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
192 return PCIBIOS_SUCCESSFUL;
195 static int it8152_pci_write_config(struct pci_bus *bus,
196 unsigned int devfn, int where,
199 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
200 u32 v, vtemp, mask = 0;
210 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
211 vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
214 vtemp &= ~(mask << (8 * shift));
218 v = (value << (8 * shift));
219 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
220 __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
222 return PCIBIOS_SUCCESSFUL;
225 struct pci_ops it8152_ops = {
226 .read = it8152_pci_read_config,
227 .write = it8152_pci_write_config,
230 static struct resource it8152_io = {
231 .name = "IT8152 PCI I/O region",
232 .flags = IORESOURCE_IO,
235 static struct resource it8152_mem = {
236 .name = "IT8152 PCI memory region",
239 .flags = IORESOURCE_MEM,
243 * The following functions are needed for DMA bouncing.
244 * ITE8152 chip can address up to 64MByte, so all the devices
245 * connected to ITE8152 (PCI and USB) should have limited DMA window
247 static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
249 dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
250 __func__, dma_addr, size);
251 return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
255 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
258 static int it8152_pci_platform_notify(struct device *dev)
260 if (dev->bus == &pci_bus_type) {
262 *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
263 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
264 dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
269 static int it8152_pci_platform_notify_remove(struct device *dev)
271 if (dev->bus == &pci_bus_type)
272 dmabounce_unregister_dev(dev);
277 int dma_set_coherent_mask(struct device *dev, u64 mask)
279 if (mask >= PHYS_OFFSET + SZ_64M - 1)
285 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
288 * FIXME: use pci_ioremap_io to remap the IO space here and
289 * move over to the generic io.h implementation.
290 * This requires solving the same problem for PXA PCMCIA
293 it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
294 it8152_io.end = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
296 sys->mem_offset = 0x10000000;
297 sys->io_offset = (unsigned long)IT8152_IO_BASE;
299 if (request_resource(&ioport_resource, &it8152_io)) {
300 printk(KERN_ERR "PCI: unable to allocate IO region\n");
303 if (request_resource(&iomem_resource, &it8152_mem)) {
304 printk(KERN_ERR "PCI: unable to allocate memory region\n");
308 pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
309 pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
311 if (platform_notify || platform_notify_remove) {
312 printk(KERN_ERR "PCI: Can't use platform_notify\n");
316 platform_notify = it8152_pci_platform_notify;
317 platform_notify_remove = it8152_pci_platform_notify_remove;
322 release_resource(&it8152_io);
324 release_resource(&it8152_mem);
329 /* ITE bridge requires setting latency timer to avoid early bus access
330 termination by PCI bus master devices
332 void pcibios_set_master(struct pci_dev *dev)
336 /* no need to update on-chip OHCI controller */
337 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
338 (dev->device == PCI_DEVICE_ID_ITE_8152) &&
339 ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
342 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
344 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
345 else if (lat > pcibios_max_latency)
346 lat = pcibios_max_latency;
349 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
351 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
355 EXPORT_SYMBOL(dma_set_coherent_mask);