2 * Copyright (C) 2011 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
23 compatible = "arm,cortex-a9";
36 compatible = "arm,cortex-a9";
44 compatible = "arm,cortex-a9-pmu";
45 interrupts = <0 5 4>, <0 6 4>;
46 interrupt-parent = <&intc>;
47 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
51 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
57 intc: interrupt-controller@f8f01000 {
58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
62 reg = <0xF8F01000 0x1000>,
66 L2: cache-controller {
67 compatible = "arm,pl310-cache";
68 reg = <0xF8F02000 0x1000>;
69 arm,data-latency = <3 2 2>;
70 arm,tag-latency = <2 2 2>;
75 uart0: uart@e0000000 {
76 compatible = "xlnx,xuartps";
78 clocks = <&clkc 23>, <&clkc 40>;
79 clock-names = "ref_clk", "aper_clk";
80 reg = <0xE0000000 0x1000>;
81 interrupts = <0 27 4>;
84 uart1: uart@e0001000 {
85 compatible = "xlnx,xuartps";
87 clocks = <&clkc 24>, <&clkc 41>;
88 clock-names = "ref_clk", "aper_clk";
89 reg = <0xE0001000 0x1000>;
90 interrupts = <0 50 4>;
93 gem0: ethernet@e000b000 {
94 compatible = "cdns,gem";
95 reg = <0xe000b000 0x4000>;
97 interrupts = <0 22 4>;
98 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
99 clock-names = "pclk", "hclk", "tx_clk";
102 gem1: ethernet@e000c000 {
103 compatible = "cdns,gem";
104 reg = <0xe000c000 0x4000>;
106 interrupts = <0 45 4>;
107 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
108 clock-names = "pclk", "hclk", "tx_clk";
111 sdhci0: ps7-sdhci@e0100000 {
112 compatible = "arasan,sdhci-8.9a";
114 clock-names = "clk_xin", "clk_ahb";
115 clocks = <&clkc 21>, <&clkc 32>;
116 interrupt-parent = <&intc>;
117 interrupts = <0 24 4>;
118 reg = <0xe0100000 0x1000>;
121 sdhci1: ps7-sdhci@e0101000 {
122 compatible = "arasan,sdhci-8.9a";
124 clock-names = "clk_xin", "clk_ahb";
125 clocks = <&clkc 22>, <&clkc 33>;
126 interrupt-parent = <&intc>;
127 interrupts = <0 47 4>;
128 reg = <0xe0101000 0x1000>;
131 slcr: slcr@f8000000 {
132 compatible = "xlnx,zynq-slcr";
133 reg = <0xF8000000 0x1000>;
136 #address-cells = <1>;
141 compatible = "xlnx,ps7-clkc";
142 ps-clk-frequency = <33333333>;
143 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
144 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
145 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
146 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
147 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
148 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
149 "gem1_aper", "sdio0_aper", "sdio1_aper",
150 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
151 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
152 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
153 "dbg_trc", "dbg_apb";
158 global_timer: timer@f8f00200 {
159 compatible = "arm,cortex-a9-global-timer";
160 reg = <0xf8f00200 0x20>;
161 interrupts = <1 11 0x301>;
162 interrupt-parent = <&intc>;
166 ttc0: ttc0@f8001000 {
167 interrupt-parent = <&intc>;
168 interrupts = < 0 10 4 0 11 4 0 12 4 >;
169 compatible = "cdns,ttc";
171 reg = <0xF8001000 0x1000>;
174 ttc1: ttc1@f8002000 {
175 interrupt-parent = <&intc>;
176 interrupts = < 0 37 4 0 38 4 0 39 4 >;
177 compatible = "cdns,ttc";
179 reg = <0xF8002000 0x1000>;
181 scutimer: scutimer@f8f00600 {
182 interrupt-parent = <&intc>;
183 interrupts = < 1 13 0x301 >;
184 compatible = "arm,cortex-a9-twd-timer";
185 reg = < 0xf8f00600 0x20 >;