arch/arm/boot/dts/zynq-7000.dtsi

   1 /*
   2  *  Copyright (C) 2011 - 2014 Xilinx
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         compatible = "xlnx,zynq-7000";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         compatible = "arm,cortex-a9";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         clocks = <&clkc 3>;
  27                         clock-latency = <1000>;
  28                         cpu0-supply = <&regulator_vccpint>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 666667  1000000
  32                                 333334  1000000
  33                                 222223  1000000
  34                         >;
  35                 };
  36
  37                 cpu@1 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         reg = <1>;
  41                         clocks = <&clkc 3>;
  42                 };
  43         };
  44
  45         pmu {
  46                 compatible = "arm,cortex-a9-pmu";
  47                 interrupts = <0 5 4>, <0 6 4>;
  48                 interrupt-parent = <&intc>;
  49                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  50         };
  51
  52         regulator_vccpint: fixedregulator@0 {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "VCCPINT";
  55                 regulator-min-microvolt = <1000000>;
  56                 regulator-max-microvolt = <1000000>;
  57                 regulator-boot-on;
  58                 regulator-always-on;
  59         };
  60
  61         amba {
  62                 compatible = "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 i2c0: i2c@e0004000 {
  69                         compatible = "cdns,i2c-r1p10";
  70                         status = "disabled";
  71                         clocks = <&clkc 38>;
  72                         interrupt-parent = <&intc>;
  73                         interrupts = <0 25 4>;
  74                         reg = <0xe0004000 0x1000>;
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                 };
  78
  79                 i2c1: i2c@e0005000 {
  80                         compatible = "cdns,i2c-r1p10";
  81                         status = "disabled";
  82                         clocks = <&clkc 39>;
  83                         interrupt-parent = <&intc>;
  84                         interrupts = <0 48 4>;
  85                         reg = <0xe0005000 0x1000>;
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                 };
  89
  90                 intc: interrupt-controller@f8f01000 {
  91                         compatible = "arm,cortex-a9-gic";
  92                         #interrupt-cells = <3>;
  93                         interrupt-controller;
  94                         reg = <0xF8F01000 0x1000>,
  95                               <0xF8F00100 0x100>;
  96                 };
  97
  98                 L2: cache-controller {
  99                         compatible = "arm,pl310-cache";
 100                         reg = <0xF8F02000 0x1000>;
 101                         arm,data-latency = <3 2 2>;
 102                         arm,tag-latency = <2 2 2>;
 103                         cache-unified;
 104                         cache-level = <2>;
 105                 };
 106
 107                 uart0: serial@e0000000 {
 108                         compatible = "xlnx,xuartps";
 109                         status = "disabled";
 110                         clocks = <&clkc 23>, <&clkc 40>;
 111                         clock-names = "ref_clk", "aper_clk";
 112                         reg = <0xE0000000 0x1000>;
 113                         interrupts = <0 27 4>;
 114                 };
 115
 116                 uart1: serial@e0001000 {
 117                         compatible = "xlnx,xuartps";
 118                         status = "disabled";
 119                         clocks = <&clkc 24>, <&clkc 41>;
 120                         clock-names = "ref_clk", "aper_clk";
 121                         reg = <0xE0001000 0x1000>;
 122                         interrupts = <0 50 4>;
 123                 };
 124
 125                 gem0: ethernet@e000b000 {
 126                         compatible = "cdns,gem";
 127                         reg = <0xe000b000 0x4000>;
 128                         status = "disabled";
 129                         interrupts = <0 22 4>;
 130                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 131                         clock-names = "pclk", "hclk", "tx_clk";
 132                 };
 133
 134                 gem1: ethernet@e000c000 {
 135                         compatible = "cdns,gem";
 136                         reg = <0xe000c000 0x4000>;
 137                         status = "disabled";
 138                         interrupts = <0 45 4>;
 139                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 140                         clock-names = "pclk", "hclk", "tx_clk";
 141                 };
 142
 143                 sdhci0: sdhci@e0100000 {
 144                         compatible = "arasan,sdhci-8.9a";
 145                         status = "disabled";
 146                         clock-names = "clk_xin", "clk_ahb";
 147                         clocks = <&clkc 21>, <&clkc 32>;
 148                         interrupt-parent = <&intc>;
 149                         interrupts = <0 24 4>;
 150                         reg = <0xe0100000 0x1000>;
 151                 } ;
 152
 153                 sdhci1: sdhci@e0101000 {
 154                         compatible = "arasan,sdhci-8.9a";
 155                         status = "disabled";
 156                         clock-names = "clk_xin", "clk_ahb";
 157                         clocks = <&clkc 22>, <&clkc 33>;
 158                         interrupt-parent = <&intc>;
 159                         interrupts = <0 47 4>;
 160                         reg = <0xe0101000 0x1000>;
 161                 } ;
 162
 163                 slcr: slcr@f8000000 {
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         compatible = "xlnx,zynq-slcr", "syscon";
 167                         reg = <0xF8000000 0x1000>;
 168                         ranges;
 169                         clkc: clkc@100 {
 170                                 #clock-cells = <1>;
 171                                 compatible = "xlnx,ps7-clkc";
 172                                 ps-clk-frequency = <33333333>;
 173                                 fclk-enable = <0>;
 174                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 175                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 176                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 177                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 178                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 179                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 180                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 181                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 182                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 183                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 184                                                 "dbg_trc", "dbg_apb";
 185                                 reg = <0x100 0x100>;
 186                         };
 187                 };
 188
 189                 devcfg: devcfg@f8007000 {
 190                         compatible = "xlnx,zynq-devcfg-1.0";
 191                         reg = <0xf8007000 0x100>;
 192                 } ;
 193
 194                 global_timer: timer@f8f00200 {
 195                         compatible = "arm,cortex-a9-global-timer";
 196                         reg = <0xf8f00200 0x20>;
 197                         interrupts = <1 11 0x301>;
 198                         interrupt-parent = <&intc>;
 199                         clocks = <&clkc 4>;
 200                 };
 201
 202                 ttc0: timer@f8001000 {
 203                         interrupt-parent = <&intc>;
 204                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 205                         compatible = "cdns,ttc";
 206                         clocks = <&clkc 6>;
 207                         reg = <0xF8001000 0x1000>;
 208                 };
 209
 210                 ttc1: timer@f8002000 {
 211                         interrupt-parent = <&intc>;
 212                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 213                         compatible = "cdns,ttc";
 214                         clocks = <&clkc 6>;
 215                         reg = <0xF8002000 0x1000>;
 216                 };
 217
 218                 scutimer: timer@f8f00600 {
 219                         interrupt-parent = <&intc>;
 220                         interrupts = <1 13 0x301>;
 221                         compatible = "arm,cortex-a9-twd-timer";
 222                         reg = <0xf8f00600 0x20>;
 223                         clocks = <&clkc 4>;
 224                 } ;
 225         };
 226 };