arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 cpu@0 {
  16                         compatible = "arm,arm926ejs";
  17                 };
  18         };
  19
  20         soc {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 compatible = "simple-bus";
  24                 ranges;
  25                 interrupt-parent = <&intc0>;
  26
  27                 intc0: interrupt-controller@d8140000 {
  28                         compatible = "via,vt8500-intc";
  29                         interrupt-controller;
  30                         reg = <0xd8140000 0x10000>;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 /* Secondary IC cascaded to intc0 */
  35                 intc1: interrupt-controller@d8150000 {
  36                         compatible = "via,vt8500-intc";
  37                         interrupt-controller;
  38                         #interrupt-cells = <1>;
  39                         reg = <0xD8150000 0x10000>;
  40                         interrupts = <56 57 58 59 60 61 62 63>;
  41                 };
  42
  43                 pinctrl: pinctrl@d8110000 {
  44                         compatible = "wm,wm8505-pinctrl";
  45                         reg = <0xd8110000 0x10000>;
  46                         interrupt-controller;
  47                         #interrupt-cells = <2>;
  48                         gpio-controller;
  49                         #gpio-cells = <2>;
  50                 };
  51
  52                 pmc@d8130000 {
  53                         compatible = "via,vt8500-pmc";
  54                         reg = <0xd8130000 0x1000>;
  55                         clocks {
  56                                 #address-cells = <1>;
  57                                 #size-cells = <0>;
  58
  59                                 ref24: ref24M {
  60                                         #clock-cells = <0>;
  61                                         compatible = "fixed-clock";
  62                                         clock-frequency = <24000000>;
  63                                 };
  64
  65                                 ref25: ref25M {
  66                                         #clock-cells = <0>;
  67                                         compatible = "fixed-clock";
  68                                         clock-frequency = <25000000>;
  69                                 };
  70
  71                                 pllb: pllb {
  72                                         #clock-cells = <0>;
  73                                         compatible = "via,vt8500-pll-clock";
  74                                         clocks = <&ref25>;
  75                                         reg = <0x204>;
  76                                 };
  77
  78                                 clkuart0: uart0 {
  79                                         #clock-cells = <0>;
  80                                         compatible = "via,vt8500-device-clock";
  81                                         clocks = <&ref24>;
  82                                         enable-reg = <0x250>;
  83                                         enable-bit = <1>;
  84                                 };
  85
  86                                 clkuart1: uart1 {
  87                                         #clock-cells = <0>;
  88                                         compatible = "via,vt8500-device-clock";
  89                                         clocks = <&ref24>;
  90                                         enable-reg = <0x250>;
  91                                         enable-bit = <2>;
  92                                 };
  93
  94                                 clkuart2: uart2 {
  95                                         #clock-cells = <0>;
  96                                         compatible = "via,vt8500-device-clock";
  97                                         clocks = <&ref24>;
  98                                         enable-reg = <0x250>;
  99                                         enable-bit = <3>;
 100                                 };
 101
 102                                 clkuart3: uart3 {
 103                                         #clock-cells = <0>;
 104                                         compatible = "via,vt8500-device-clock";
 105                                         clocks = <&ref24>;
 106                                         enable-reg = <0x250>;
 107                                         enable-bit = <4>;
 108                                 };
 109
 110                                 clkuart4: uart4 {
 111                                         #clock-cells = <0>;
 112                                         compatible = "via,vt8500-device-clock";
 113                                         clocks = <&ref24>;
 114                                         enable-reg = <0x250>;
 115                                         enable-bit = <22>;
 116                                 };
 117
 118                                 clkuart5: uart5 {
 119                                         #clock-cells = <0>;
 120                                         compatible = "via,vt8500-device-clock";
 121                                         clocks = <&ref24>;
 122                                         enable-reg = <0x250>;
 123                                         enable-bit = <23>;
 124                                 };
 125
 126                                 clksdhc: sdhc {
 127                                         #clock-cells = <0>;
 128                                         compatible = "via,vt8500-device-clock";
 129                                         clocks = <&pllb>;
 130                                         divisor-reg = <0x328>;
 131                                         divisor-mask = <0x3f>;
 132                                         enable-reg = <0x254>;
 133                                         enable-bit = <18>;
 134                                 };
 135                         };
 136                 };
 137
 138                 timer@d8130100 {
 139                         compatible = "via,vt8500-timer";
 140                         reg = <0xd8130100 0x28>;
 141                         interrupts = <36>;
 142                 };
 143
 144                 ehci@d8007100 {
 145                         compatible = "via,vt8500-ehci";
 146                         reg = <0xd8007100 0x200>;
 147                         interrupts = <1>;
 148                 };
 149
 150                 uhci@d8007300 {
 151                         compatible = "platform-uhci";
 152                         reg = <0xd8007300 0x200>;
 153                         interrupts = <0>;
 154                 };
 155
 156                 fb: fb@d8050800 {
 157                         compatible = "wm,wm8505-fb";
 158                         reg = <0xd8050800 0x200>;
 159                 };
 160
 161                 ge_rops@d8050400 {
 162                         compatible = "wm,prizm-ge-rops";
 163                         reg = <0xd8050400 0x100>;
 164                 };
 165
 166                 uart@d8200000 {
 167                         compatible = "via,vt8500-uart";
 168                         reg = <0xd8200000 0x1040>;
 169                         interrupts = <32>;
 170                         clocks = <&clkuart0>;
 171                 };
 172
 173                 uart@d82b0000 {
 174                         compatible = "via,vt8500-uart";
 175                         reg = <0xd82b0000 0x1040>;
 176                         interrupts = <33>;
 177                         clocks = <&clkuart1>;
 178                 };
 179
 180                 uart@d8210000 {
 181                         compatible = "via,vt8500-uart";
 182                         reg = <0xd8210000 0x1040>;
 183                         interrupts = <47>;
 184                         clocks = <&clkuart2>;
 185                 };
 186
 187                 uart@d82c0000 {
 188                         compatible = "via,vt8500-uart";
 189                         reg = <0xd82c0000 0x1040>;
 190                         interrupts = <50>;
 191                         clocks = <&clkuart3>;
 192                 };
 193
 194                 uart@d8370000 {
 195                         compatible = "via,vt8500-uart";
 196                         reg = <0xd8370000 0x1040>;
 197                         interrupts = <31>;
 198                         clocks = <&clkuart4>;
 199                 };
 200
 201                 uart@d8380000 {
 202                         compatible = "via,vt8500-uart";
 203                         reg = <0xd8380000 0x1040>;
 204                         interrupts = <30>;
 205                         clocks = <&clkuart5>;
 206                 };
 207
 208                 rtc@d8100000 {
 209                         compatible = "via,vt8500-rtc";
 210                         reg = <0xd8100000 0x10000>;
 211                         interrupts = <48>;
 212                 };
 213
 214                 sdhc@d800a000 {
 215                         compatible = "wm,wm8505-sdhc";
 216                         reg = <0xd800a000 0x1000>;
 217                         interrupts = <20 21>;
 218                         clocks = <&clksdhc>;
 219                         bus-width = <4>;
 220                 };
 221         };
 222 };