2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "skeleton.dtsi"
11 #include "vf610-pinfunc.h"
12 #include <dt-bindings/clock/vf610-clock.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
37 compatible = "arm,cortex-a5";
40 next-level-cache = <&L2>;
49 compatible = "fixed-clock";
51 clock-frequency = <32768>;
55 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
68 aips0: aips-bus@40000000 {
69 compatible = "fsl,aips-bus", "simple-bus";
72 interrupt-parent = <&intc>;
73 reg = <0x40000000 0x70000>;
76 intc: interrupt-controller@40002000 {
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
80 reg = <0x40003000 0x1000>,
84 L2: l2-cache@40006000 {
85 compatible = "arm,pl310-cache";
86 reg = <0x40006000 0x1000>;
89 arm,data-latency = <1 1 1>;
90 arm,tag-latency = <2 2 2>;
93 edma0: dma-controller@40018000 {
95 compatible = "fsl,vf610-edma";
96 reg = <0x40018000 0x2000>,
99 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
100 <0 9 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-names = "edma-tx", "edma-err";
103 clock-names = "dmamux0", "dmamux1";
104 clocks = <&clks VF610_CLK_DMAMUX0>,
105 <&clks VF610_CLK_DMAMUX1>;
108 can0: flexcan@40020000 {
109 compatible = "fsl,vf610-flexcan";
110 reg = <0x40020000 0x4000>;
111 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_FLEXCAN0>,
113 <&clks VF610_CLK_FLEXCAN0>;
114 clock-names = "ipg", "per";
118 uart0: serial@40027000 {
119 compatible = "fsl,vf610-lpuart";
120 reg = <0x40027000 0x1000>;
121 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&clks VF610_CLK_UART0>;
126 dma-names = "rx","tx";
130 uart1: serial@40028000 {
131 compatible = "fsl,vf610-lpuart";
132 reg = <0x40028000 0x1000>;
133 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clks VF610_CLK_UART1>;
138 dma-names = "rx","tx";
142 uart2: serial@40029000 {
143 compatible = "fsl,vf610-lpuart";
144 reg = <0x40029000 0x1000>;
145 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks VF610_CLK_UART2>;
150 dma-names = "rx","tx";
154 uart3: serial@4002a000 {
155 compatible = "fsl,vf610-lpuart";
156 reg = <0x4002a000 0x1000>;
157 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks VF610_CLK_UART3>;
162 dma-names = "rx","tx";
166 dspi0: dspi0@4002c000 {
167 #address-cells = <1>;
169 compatible = "fsl,vf610-dspi";
170 reg = <0x4002c000 0x1000>;
171 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clks VF610_CLK_DSPI0>;
173 clock-names = "dspi";
174 spi-num-chipselects = <5>;
179 compatible = "fsl,vf610-sai";
180 reg = <0x40031000 0x1000>;
181 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks VF610_CLK_SAI2>;
184 dma-names = "tx", "rx";
185 dmas = <&edma0 0 21>,
191 compatible = "fsl,vf610-pit";
192 reg = <0x40037000 0x1000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks VF610_CLK_PIT>;
199 compatible = "fsl,vf610-ftm-pwm";
201 reg = <0x40038000 0x1000>;
202 clock-names = "ftm_sys", "ftm_ext",
203 "ftm_fix", "ftm_cnt_clk_en";
204 clocks = <&clks VF610_CLK_FTM0>,
205 <&clks VF610_CLK_FTM0_EXT_SEL>,
206 <&clks VF610_CLK_FTM0_FIX_SEL>,
207 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
212 compatible = "fsl,vf610-adc";
213 reg = <0x4003b000 0x1000>;
214 interrupts = <0 53 0x04>;
215 clocks = <&clks VF610_CLK_ADC0>;
221 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
222 reg = <0x4003e000 0x1000>;
223 clocks = <&clks VF610_CLK_WDT>;
224 clock-names = "wdog";
227 qspi0: quadspi@40044000 {
228 #address-cells = <1>;
230 compatible = "fsl,vf610-qspi";
231 reg = <0x40044000 0x1000>;
232 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks VF610_CLK_QSPI0_EN>,
234 <&clks VF610_CLK_QSPI0>;
235 clock-names = "qspi_en", "qspi";
239 iomuxc: iomuxc@40048000 {
240 compatible = "fsl,vf610-iomuxc";
241 reg = <0x40048000 0x1000>;
242 #gpio-range-cells = <3>;
245 gpio1: gpio@40049000 {
246 compatible = "fsl,vf610-gpio";
247 reg = <0x40049000 0x1000 0x400ff000 0x40>;
248 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 gpio-ranges = <&iomuxc 0 0 32>;
256 gpio2: gpio@4004a000 {
257 compatible = "fsl,vf610-gpio";
258 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
259 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 gpio-ranges = <&iomuxc 0 32 32>;
267 gpio3: gpio@4004b000 {
268 compatible = "fsl,vf610-gpio";
269 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
270 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 gpio-ranges = <&iomuxc 0 64 32>;
278 gpio4: gpio@4004c000 {
279 compatible = "fsl,vf610-gpio";
280 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
281 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 gpio-ranges = <&iomuxc 0 96 32>;
289 gpio5: gpio@4004d000 {
290 compatible = "fsl,vf610-gpio";
291 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
292 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 gpio-ranges = <&iomuxc 0 128 7>;
301 compatible = "fsl,vf610-anatop";
302 reg = <0x40050000 0x1000>;
306 #address-cells = <1>;
308 compatible = "fsl,vf610-i2c";
309 reg = <0x40066000 0x1000>;
310 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks VF610_CLK_I2C0>;
313 dmas = <&edma0 0 50>,
315 dma-names = "rx","tx";
320 compatible = "fsl,vf610-ccm";
321 reg = <0x4006b000 0x1000>;
326 aips1: aips-bus@40080000 {
327 compatible = "fsl,aips-bus", "simple-bus";
328 #address-cells = <1>;
330 reg = <0x40080000 0x80000>;
333 edma1: dma-controller@40098000 {
335 compatible = "fsl,vf610-edma";
336 reg = <0x40098000 0x2000>,
339 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
340 <0 11 IRQ_TYPE_LEVEL_HIGH>;
341 interrupt-names = "edma-tx", "edma-err";
343 clock-names = "dmamux0", "dmamux1";
344 clocks = <&clks VF610_CLK_DMAMUX2>,
345 <&clks VF610_CLK_DMAMUX3>;
348 uart4: serial@400a9000 {
349 compatible = "fsl,vf610-lpuart";
350 reg = <0x400a9000 0x1000>;
351 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clks VF610_CLK_UART4>;
357 uart5: serial@400aa000 {
358 compatible = "fsl,vf610-lpuart";
359 reg = <0x400aa000 0x1000>;
360 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks VF610_CLK_UART5>;
367 compatible = "fsl,vf610-adc";
368 reg = <0x400bb000 0x1000>;
369 interrupts = <0 54 0x04>;
370 clocks = <&clks VF610_CLK_ADC1>;
375 esdhc1: esdhc@400b2000 {
376 compatible = "fsl,imx53-esdhc";
377 reg = <0x400b2000 0x1000>;
378 interrupts = <0 28 0x04>;
379 clocks = <&clks VF610_CLK_IPG_BUS>,
380 <&clks VF610_CLK_PLATFORM_BUS>,
381 <&clks VF610_CLK_ESDHC1>;
382 clock-names = "ipg", "ahb", "per";
387 compatible = "fsl,ftm-timer";
388 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
389 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
390 clock-names = "ftm-evt", "ftm-src",
391 "ftm-evt-counter-en", "ftm-src-counter-en";
392 clocks = <&clks VF610_CLK_FTM2>,
393 <&clks VF610_CLK_FTM3>,
394 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
395 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
399 fec0: ethernet@400d0000 {
400 compatible = "fsl,mvf600-fec";
401 reg = <0x400d0000 0x1000>;
402 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks VF610_CLK_ENET0>,
404 <&clks VF610_CLK_ENET0>,
405 <&clks VF610_CLK_ENET>;
406 clock-names = "ipg", "ahb", "ptp";
410 fec1: ethernet@400d1000 {
411 compatible = "fsl,mvf600-fec";
412 reg = <0x400d1000 0x1000>;
413 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clks VF610_CLK_ENET1>,
415 <&clks VF610_CLK_ENET1>,
416 <&clks VF610_CLK_ENET>;
417 clock-names = "ipg", "ahb", "ptp";
421 can1: flexcan@400d4000 {
422 compatible = "fsl,vf610-flexcan";
423 reg = <0x400d4000 0x4000>;
424 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clks VF610_CLK_FLEXCAN1>,
426 <&clks VF610_CLK_FLEXCAN1>;
427 clock-names = "ipg", "per";