arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "VF610 Tower Board";
  15         compatible = "fsl,vf610-twr", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP1,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x8000000>;
  23         };
  24
  25         clocks {
  26                 audio_ext {
  27                         compatible = "fixed-clock";
  28                         clock-frequency = <24576000>;
  29                 };
  30
  31                 enet_ext {
  32                         compatible = "fixed-clock";
  33                         clock-frequency = <50000000>;
  34                 };
  35         };
  36
  37 };
  38
  39 &dspi0 {
  40         bus-num = <0>;
  41         pinctrl-names = "default";
  42         pinctrl-0 = <&pinctrl_dspi0>;
  43         status = "okay";
  44
  45         sflash: at26df081a@0 {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "atmel,at26df081a";
  49                 spi-max-frequency = <16000000>;
  50                 spi-cpol;
  51                 spi-cpha;
  52                 reg = <0>;
  53         };
  54 };
  55
  56 &fec0 {
  57         phy-mode = "rmii";
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_fec0>;
  60         status = "okay";
  61 };
  62
  63 &fec1 {
  64         phy-mode = "rmii";
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_fec1>;
  67         status = "okay";
  68 };
  69
  70 &i2c0 {
  71         clock-frequency = <100000>;
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_i2c0>;
  74         status = "okay";
  75 };
  76
  77 &iomuxc {
  78         vf610-twr {
  79                 pinctrl_dspi0: dspi0grp {
  80                         fsl,pins = <
  81                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
  82                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
  83                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
  84                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
  85                         >;
  86                 };
  87
  88                 pinctrl_fec0: fec0grp {
  89                         fsl,pins = <
  90                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
  91                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
  92                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
  93                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
  94                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
  95                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
  96                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
  97                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
  98                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
  99                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 100                         >;
 101                 };
 102
 103                 pinctrl_fec1: fec1grp {
 104                         fsl,pins = <
 105                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 106                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 107                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 108                                 VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
 109                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 110                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 111                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 112                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 113                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 114                         >;
 115                 };
 116
 117                 pinctrl_i2c0: i2c0grp {
 118                         fsl,pins = <
 119                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 120                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 121                         >;
 122                 };
 123
 124                 pinctrl_uart1: uart1grp {
 125                         fsl,pins = <
 126                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 127                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 128                         >;
 129                 };
 130         };
 131 };
 132
 133 &uart1 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_uart1>;
 136         status = "okay";
 137 };