arch/arm/boot/dts/vexpress-v2p-ca9.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A9x4
   5  * Cortex-A9 MPCore (V2P-CA9)
   6  *
   7  * HBI-0191B
   8  */
   9
  10 /dts-v1/;
  11
  12 /include/ "clcd-panels.dtsi"
  13
  14 / {
  15         model = "V2P-CA9";
  16         arm,hbi = <0x191>;
  17         arm,vexpress,site = <0xf>;
  18         compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         chosen { };
  24
  25         aliases {
  26                 serial0 = &v2m_serial0;
  27                 serial1 = &v2m_serial1;
  28                 serial2 = &v2m_serial2;
  29                 serial3 = &v2m_serial3;
  30                 i2c0 = &v2m_i2c_dvi;
  31                 i2c1 = &v2m_i2c_pcie;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <0>;
  42                         next-level-cache = <&L2>;
  43                 };
  44
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         reg = <1>;
  49                         next-level-cache = <&L2>;
  50                 };
  51
  52                 cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                 };
  58
  59                 cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a9";
  62                         reg = <3>;
  63                         next-level-cache = <&L2>;
  64                 };
  65         };
  66
  67         memory@60000000 {
  68                 device_type = "memory";
  69                 reg = <0x60000000 0x40000000>;
  70         };
  71
  72         clcd@10020000 {
  73                 compatible = "arm,pl111", "arm,primecell";
  74                 reg = <0x10020000 0x1000>;
  75                 interrupts = <0 44 4>;
  76                 clocks = <&oscclk1>, <&oscclk2>;
  77                 clock-names = "clcdclk", "apb_pclk";
  78                 mode = "XVGA";
  79                 use_dma = <1>;
  80         };
  81
  82         memory-controller@100e0000 {
  83                 compatible = "arm,pl341", "arm,primecell";
  84                 reg = <0x100e0000 0x1000>;
  85                 clocks = <&oscclk2>;
  86                 clock-names = "apb_pclk";
  87         };
  88
  89         memory-controller@100e1000 {
  90                 compatible = "arm,pl354", "arm,primecell";
  91                 reg = <0x100e1000 0x1000>;
  92                 interrupts = <0 45 4>,
  93                              <0 46 4>;
  94                 clocks = <&oscclk2>;
  95                 clock-names = "apb_pclk";
  96         };
  97
  98         timer@100e4000 {
  99                 compatible = "arm,sp804", "arm,primecell";
 100                 reg = <0x100e4000 0x1000>;
 101                 interrupts = <0 48 4>,
 102                              <0 49 4>;
 103                 clocks = <&oscclk2>, <&oscclk2>;
 104                 clock-names = "timclk", "apb_pclk";
 105                 status = "disabled";
 106         };
 107
 108         watchdog@100e5000 {
 109                 compatible = "arm,sp805", "arm,primecell";
 110                 reg = <0x100e5000 0x1000>;
 111                 interrupts = <0 51 4>;
 112                 clocks = <&oscclk2>, <&oscclk2>;
 113                 clock-names = "wdogclk", "apb_pclk";
 114         };
 115
 116         scu@1e000000 {
 117                 compatible = "arm,cortex-a9-scu";
 118                 reg = <0x1e000000 0x58>;
 119         };
 120
 121         timer@1e000600 {
 122                 compatible = "arm,cortex-a9-twd-timer";
 123                 reg = <0x1e000600 0x20>;
 124                 interrupts = <1 13 0xf04>;
 125         };
 126
 127         watchdog@1e000620 {
 128                 compatible = "arm,cortex-a9-twd-wdt";
 129                 reg = <0x1e000620 0x20>;
 130                 interrupts = <1 14 0xf04>;
 131         };
 132
 133         gic: interrupt-controller@1e001000 {
 134                 compatible = "arm,cortex-a9-gic";
 135                 #interrupt-cells = <3>;
 136                 #address-cells = <0>;
 137                 interrupt-controller;
 138                 reg = <0x1e001000 0x1000>,
 139                       <0x1e000100 0x100>;
 140         };
 141
 142         L2: cache-controller@1e00a000 {
 143                 compatible = "arm,pl310-cache";
 144                 reg = <0x1e00a000 0x1000>;
 145                 interrupts = <0 43 4>;
 146                 cache-level = <2>;
 147                 arm,data-latency = <1 1 1>;
 148                 arm,tag-latency = <1 1 1>;
 149         };
 150
 151         pmu {
 152                 compatible = "arm,cortex-a9-pmu";
 153                 interrupts = <0 60 4>,
 154                              <0 61 4>,
 155                              <0 62 4>,
 156                              <0 63 4>;
 157         };
 158
 159         dcc {
 160                 compatible = "arm,vexpress,config-bus";
 161                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 162
 163                 osc@0 {
 164                         /* ACLK clock to the AXI master port on the test chip */
 165                         compatible = "arm,vexpress-osc";
 166                         arm,vexpress-sysreg,func = <1 0>;
 167                         freq-range = <30000000 50000000>;
 168                         #clock-cells = <0>;
 169                         clock-output-names = "extsaxiclk";
 170                 };
 171
 172                 oscclk1: osc@1 {
 173                         /* Reference clock for the CLCD */
 174                         compatible = "arm,vexpress-osc";
 175                         arm,vexpress-sysreg,func = <1 1>;
 176                         freq-range = <10000000 80000000>;
 177                         #clock-cells = <0>;
 178                         clock-output-names = "clcdclk";
 179                 };
 180
 181                 smbclk: oscclk2: osc@2 {
 182                         /* Reference clock for the test chip internal PLLs */
 183                         compatible = "arm,vexpress-osc";
 184                         arm,vexpress-sysreg,func = <1 2>;
 185                         freq-range = <33000000 100000000>;
 186                         #clock-cells = <0>;
 187                         clock-output-names = "tcrefclk";
 188                 };
 189
 190                 volt@0 {
 191                         /* Test Chip internal logic voltage */
 192                         compatible = "arm,vexpress-volt";
 193                         arm,vexpress-sysreg,func = <2 0>;
 194                         regulator-name = "VD10";
 195                         regulator-always-on;
 196                         label = "VD10";
 197                 };
 198
 199                 volt@1 {
 200                         /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 201                         compatible = "arm,vexpress-volt";
 202                         arm,vexpress-sysreg,func = <2 1>;
 203                         regulator-name = "VD10_S2";
 204                         regulator-always-on;
 205                         label = "VD10_S2";
 206                 };
 207
 208                 volt@2 {
 209                         /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 210                         compatible = "arm,vexpress-volt";
 211                         arm,vexpress-sysreg,func = <2 2>;
 212                         regulator-name = "VD10_S3";
 213                         regulator-always-on;
 214                         label = "VD10_S3";
 215                 };
 216
 217                 volt@3 {
 218                         /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
 219                         compatible = "arm,vexpress-volt";
 220                         arm,vexpress-sysreg,func = <2 3>;
 221                         regulator-name = "VCC1V8";
 222                         regulator-always-on;
 223                         label = "VCC1V8";
 224                 };
 225
 226                 volt@4 {
 227                         /* DDR2 SDRAM VTT termination voltage */
 228                         compatible = "arm,vexpress-volt";
 229                         arm,vexpress-sysreg,func = <2 4>;
 230                         regulator-name = "DDR2VTT";
 231                         regulator-always-on;
 232                         label = "DDR2VTT";
 233                 };
 234
 235                 volt@5 {
 236                         /* Local board supply for miscellaneous logic external to the Test Chip */
 237                         arm,vexpress-sysreg,func = <2 5>;
 238                         compatible = "arm,vexpress-volt";
 239                         regulator-name = "VCC3V3";
 240                         regulator-always-on;
 241                         label = "VCC3V3";
 242                 };
 243
 244                 amp@0 {
 245                         /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 246                         compatible = "arm,vexpress-amp";
 247                         arm,vexpress-sysreg,func = <3 0>;
 248                         label = "VD10_S2";
 249                 };
 250
 251                 amp@1 {
 252                         /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 253                         compatible = "arm,vexpress-amp";
 254                         arm,vexpress-sysreg,func = <3 1>;
 255                         label = "VD10_S3";
 256                 };
 257
 258                 power@0 {
 259                         /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 260                         compatible = "arm,vexpress-power";
 261                         arm,vexpress-sysreg,func = <12 0>;
 262                         label = "PVD10_S2";
 263                 };
 264
 265                 power@1 {
 266                         /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 267                         compatible = "arm,vexpress-power";
 268                         arm,vexpress-sysreg,func = <12 1>;
 269                         label = "PVD10_S3";
 270                 };
 271         };
 272
 273         smb {
 274                 compatible = "simple-bus";
 275
 276                 #address-cells = <2>;
 277                 #size-cells = <1>;
 278                 ranges = <0 0 0x40000000 0x04000000>,
 279                          <1 0 0x44000000 0x04000000>,
 280                          <2 0 0x48000000 0x04000000>,
 281                          <3 0 0x4c000000 0x04000000>,
 282                          <7 0 0x10000000 0x00020000>;
 283
 284                 #interrupt-cells = <1>;
 285                 interrupt-map-mask = <0 0 63>;
 286                 interrupt-map = <0 0  0 &gic 0  0 4>,
 287                                 <0 0  1 &gic 0  1 4>,
 288                                 <0 0  2 &gic 0  2 4>,
 289                                 <0 0  3 &gic 0  3 4>,
 290                                 <0 0  4 &gic 0  4 4>,
 291                                 <0 0  5 &gic 0  5 4>,
 292                                 <0 0  6 &gic 0  6 4>,
 293                                 <0 0  7 &gic 0  7 4>,
 294                                 <0 0  8 &gic 0  8 4>,
 295                                 <0 0  9 &gic 0  9 4>,
 296                                 <0 0 10 &gic 0 10 4>,
 297                                 <0 0 11 &gic 0 11 4>,
 298                                 <0 0 12 &gic 0 12 4>,
 299                                 <0 0 13 &gic 0 13 4>,
 300                                 <0 0 14 &gic 0 14 4>,
 301                                 <0 0 15 &gic 0 15 4>,
 302                                 <0 0 16 &gic 0 16 4>,
 303                                 <0 0 17 &gic 0 17 4>,
 304                                 <0 0 18 &gic 0 18 4>,
 305                                 <0 0 19 &gic 0 19 4>,
 306                                 <0 0 20 &gic 0 20 4>,
 307                                 <0 0 21 &gic 0 21 4>,
 308                                 <0 0 22 &gic 0 22 4>,
 309                                 <0 0 23 &gic 0 23 4>,
 310                                 <0 0 24 &gic 0 24 4>,
 311                                 <0 0 25 &gic 0 25 4>,
 312                                 <0 0 26 &gic 0 26 4>,
 313                                 <0 0 27 &gic 0 27 4>,
 314                                 <0 0 28 &gic 0 28 4>,
 315                                 <0 0 29 &gic 0 29 4>,
 316                                 <0 0 30 &gic 0 30 4>,
 317                                 <0 0 31 &gic 0 31 4>,
 318                                 <0 0 32 &gic 0 32 4>,
 319                                 <0 0 33 &gic 0 33 4>,
 320                                 <0 0 34 &gic 0 34 4>,
 321                                 <0 0 35 &gic 0 35 4>,
 322                                 <0 0 36 &gic 0 36 4>,
 323                                 <0 0 37 &gic 0 37 4>,
 324                                 <0 0 38 &gic 0 38 4>,
 325                                 <0 0 39 &gic 0 39 4>,
 326                                 <0 0 40 &gic 0 40 4>,
 327                                 <0 0 41 &gic 0 41 4>,
 328                                 <0 0 42 &gic 0 42 4>;
 329
 330                 /include/ "vexpress-v2m.dtsi"
 331         };
 332 };