2 * ARM Ltd. Versatile Express
4 * CoreTile Express A9x4
5 * Cortex-A9 MPCore (V2P-CA9)
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
17 interrupt-parent = <&gic>;
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9";
47 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
59 compatible = "arm,cortex-a9";
61 next-level-cache = <&L2>;
66 device_type = "memory";
67 reg = <0x60000000 0x40000000>;
71 compatible = "arm,pl111", "arm,primecell";
72 reg = <0x10020000 0x1000>;
73 interrupt-names = "combined";
74 interrupts = <0 44 4>;
75 clocks = <&oscclk1>, <&oscclk2>;
76 clock-names = "clcdclk", "apb_pclk";
77 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
81 remote-endpoint = <&clcd_panel>;
82 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
87 compatible = "panel-dpi";
90 clcd_panel: endpoint {
91 remote-endpoint = <&clcd_pads>;
96 clock-frequency = <63500127>;
109 memory-controller@100e0000 {
110 compatible = "arm,pl341", "arm,primecell";
111 reg = <0x100e0000 0x1000>;
113 clock-names = "apb_pclk";
116 memory-controller@100e1000 {
117 compatible = "arm,pl354", "arm,primecell";
118 reg = <0x100e1000 0x1000>;
119 interrupts = <0 45 4>,
122 clock-names = "apb_pclk";
126 compatible = "arm,sp804", "arm,primecell";
127 reg = <0x100e4000 0x1000>;
128 interrupts = <0 48 4>,
130 clocks = <&oscclk2>, <&oscclk2>;
131 clock-names = "timclk", "apb_pclk";
136 compatible = "arm,sp805", "arm,primecell";
137 reg = <0x100e5000 0x1000>;
138 interrupts = <0 51 4>;
139 clocks = <&oscclk2>, <&oscclk2>;
140 clock-names = "wdogclk", "apb_pclk";
144 compatible = "arm,cortex-a9-scu";
145 reg = <0x1e000000 0x58>;
149 compatible = "arm,cortex-a9-twd-timer";
150 reg = <0x1e000600 0x20>;
151 interrupts = <1 13 0xf04>;
155 compatible = "arm,cortex-a9-twd-wdt";
156 reg = <0x1e000620 0x20>;
157 interrupts = <1 14 0xf04>;
160 gic: interrupt-controller@1e001000 {
161 compatible = "arm,cortex-a9-gic";
162 #interrupt-cells = <3>;
163 #address-cells = <0>;
164 interrupt-controller;
165 reg = <0x1e001000 0x1000>,
169 L2: cache-controller@1e00a000 {
170 compatible = "arm,pl310-cache";
171 reg = <0x1e00a000 0x1000>;
172 interrupts = <0 43 4>;
174 arm,data-latency = <1 1 1>;
175 arm,tag-latency = <1 1 1>;
179 compatible = "arm,cortex-a9-pmu";
180 interrupts = <0 60 4>,
187 compatible = "arm,vexpress,config-bus";
188 arm,vexpress,config-bridge = <&v2m_sysreg>;
191 /* ACLK clock to the AXI master port on the test chip */
192 compatible = "arm,vexpress-osc";
193 arm,vexpress-sysreg,func = <1 0>;
194 freq-range = <30000000 50000000>;
196 clock-output-names = "extsaxiclk";
200 /* Reference clock for the CLCD */
201 compatible = "arm,vexpress-osc";
202 arm,vexpress-sysreg,func = <1 1>;
203 freq-range = <10000000 80000000>;
205 clock-output-names = "clcdclk";
208 smbclk: oscclk2: osc@2 {
209 /* Reference clock for the test chip internal PLLs */
210 compatible = "arm,vexpress-osc";
211 arm,vexpress-sysreg,func = <1 2>;
212 freq-range = <33000000 100000000>;
214 clock-output-names = "tcrefclk";
218 /* Test Chip internal logic voltage */
219 compatible = "arm,vexpress-volt";
220 arm,vexpress-sysreg,func = <2 0>;
221 regulator-name = "VD10";
227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
228 compatible = "arm,vexpress-volt";
229 arm,vexpress-sysreg,func = <2 1>;
230 regulator-name = "VD10_S2";
236 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
237 compatible = "arm,vexpress-volt";
238 arm,vexpress-sysreg,func = <2 2>;
239 regulator-name = "VD10_S3";
245 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
246 compatible = "arm,vexpress-volt";
247 arm,vexpress-sysreg,func = <2 3>;
248 regulator-name = "VCC1V8";
254 /* DDR2 SDRAM VTT termination voltage */
255 compatible = "arm,vexpress-volt";
256 arm,vexpress-sysreg,func = <2 4>;
257 regulator-name = "DDR2VTT";
263 /* Local board supply for miscellaneous logic external to the Test Chip */
264 arm,vexpress-sysreg,func = <2 5>;
265 compatible = "arm,vexpress-volt";
266 regulator-name = "VCC3V3";
272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
273 compatible = "arm,vexpress-amp";
274 arm,vexpress-sysreg,func = <3 0>;
279 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
280 compatible = "arm,vexpress-amp";
281 arm,vexpress-sysreg,func = <3 1>;
286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
287 compatible = "arm,vexpress-power";
288 arm,vexpress-sysreg,func = <12 0>;
293 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
294 compatible = "arm,vexpress-power";
295 arm,vexpress-sysreg,func = <12 1>;
301 compatible = "simple-bus";
303 #address-cells = <2>;
305 ranges = <0 0 0x40000000 0x04000000>,
306 <1 0 0x44000000 0x04000000>,
307 <2 0 0x48000000 0x04000000>,
308 <3 0 0x4c000000 0x04000000>,
309 <7 0 0x10000000 0x00020000>;
311 #interrupt-cells = <1>;
312 interrupt-map-mask = <0 0 63>;
313 interrupt-map = <0 0 0 &gic 0 0 4>,
323 <0 0 10 &gic 0 10 4>,
324 <0 0 11 &gic 0 11 4>,
325 <0 0 12 &gic 0 12 4>,
326 <0 0 13 &gic 0 13 4>,
327 <0 0 14 &gic 0 14 4>,
328 <0 0 15 &gic 0 15 4>,
329 <0 0 16 &gic 0 16 4>,
330 <0 0 17 &gic 0 17 4>,
331 <0 0 18 &gic 0 18 4>,
332 <0 0 19 &gic 0 19 4>,
333 <0 0 20 &gic 0 20 4>,
334 <0 0 21 &gic 0 21 4>,
335 <0 0 22 &gic 0 22 4>,
336 <0 0 23 &gic 0 23 4>,
337 <0 0 24 &gic 0 24 4>,
338 <0 0 25 &gic 0 25 4>,
339 <0 0 26 &gic 0 26 4>,
340 <0 0 27 &gic 0 27 4>,
341 <0 0 28 &gic 0 28 4>,
342 <0 0 29 &gic 0 29 4>,
343 <0 0 30 &gic 0 30 4>,
344 <0 0 31 &gic 0 31 4>,
345 <0 0 32 &gic 0 32 4>,
346 <0 0 33 &gic 0 33 4>,
347 <0 0 34 &gic 0 34 4>,
348 <0 0 35 &gic 0 35 4>,
349 <0 0 36 &gic 0 36 4>,
350 <0 0 37 &gic 0 37 4>,
351 <0 0 38 &gic 0 38 4>,
352 <0 0 39 &gic 0 39 4>,
353 <0 0 40 &gic 0 40 4>,
354 <0 0 41 &gic 0 41 4>,
355 <0 0 42 &gic 0 42 4>;
357 /include/ "vexpress-v2m.dtsi"