2 * ARM Ltd. Versatile Express
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
12 /memreserve/ 0xff000000 0x01000000;
15 model = "V2P-CA15_CA7";
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress", "arm,generic";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
82 compatible = "arm,cortex-a7";
84 cluster = <&cluster1>;
86 clock-frequency = <800000000>;
87 cci-control-port = <&cci_control2>;
92 compatible = "arm,cortex-a7";
94 cluster = <&cluster1>;
96 clock-frequency = <800000000>;
97 cci-control-port = <&cci_control2>;
102 compatible = "arm,cortex-a7";
104 cluster = <&cluster1>;
106 clock-frequency = <800000000>;
107 cci-control-port = <&cci_control2>;
112 compatible = "arm,cortex-a15";
114 cluster = <&cluster0>;
116 clock-frequency = <1000000000>;
117 cci-control-port = <&cci_control1>;
122 compatible = "arm,cortex-a15";
124 cluster = <&cluster0>;
126 clock-frequency = <1000000000>;
127 cci-control-port = <&cci_control1>;
132 device_type = "memory";
133 reg = <0 0x80000000 0 0x80000000>;
137 compatible = "arm,sp805", "arm,primecell";
138 reg = <0 0x2a490000 0 0x1000>;
139 interrupts = <0 98 4>;
140 clocks = <&oscclk6a>, <&oscclk6a>;
141 clock-names = "wdogclk", "apb_pclk";
145 compatible = "arm,hdlcd";
146 reg = <0 0x2b000000 0 0x1000>;
147 interrupts = <0 85 4>;
148 mode = "1024x768-16@60";
149 framebuffer = <0 0xff000000 0 0x01000000>;
151 clock-names = "pxlclk";
154 memory-controller@2b0a0000 {
155 compatible = "arm,pl341", "arm,primecell";
156 reg = <0 0x2b0a0000 0 0x1000>;
157 clocks = <&oscclk6a>;
158 clock-names = "apb_pclk";
161 gic: interrupt-controller@2c001000 {
162 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
163 #interrupt-cells = <3>;
164 #address-cells = <0>;
165 interrupt-controller;
166 reg = <0 0x2c001000 0 0x1000>,
167 <0 0x2c002000 0 0x1000>,
168 <0 0x2c004000 0 0x2000>,
169 <0 0x2c006000 0 0x2000>;
170 interrupts = <1 9 0xf04>;
173 compatible = "arm,gic-cpuif";
178 compatible = "arm,gic-cpuif";
183 compatible = "arm,gic-cpuif";
189 compatible = "arm,gic-cpuif";
195 compatible = "arm,gic-cpuif";
202 compatible = "arm,cci-400";
203 #address-cells = <1>;
205 reg = <0 0x2c090000 0 0x1000>;
206 ranges = <0x0 0x0 0x2c090000 0x10000>;
208 cci_control1: slave-if@4000 {
209 compatible = "arm,cci-400-ctrl-if";
210 interface-type = "ace";
211 reg = <0x4000 0x1000>;
214 cci_control2: slave-if@5000 {
215 compatible = "arm,cci-400-ctrl-if";
216 interface-type = "ace";
217 reg = <0x5000 0x1000>;
222 compatible = "arm,cci-400-pmu";
223 reg = <0 0x2c099000 0 0x6000>;
224 interrupts = <0 101 4>,
231 memory-controller@7ffd0000 {
232 compatible = "arm,pl354", "arm,primecell";
233 reg = <0 0x7ffd0000 0 0x1000>;
234 interrupts = <0 86 4>,
236 clocks = <&oscclk6a>;
237 clock-names = "apb_pclk";
241 compatible = "arm,pl330", "arm,primecell";
242 reg = <0 0x7ff00000 0 0x1000>;
243 interrupts = <0 92 4>,
248 clocks = <&oscclk6a>;
249 clock-names = "apb_pclk";
253 compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
254 reg = <0 0x7fff0000 0 0x1000>;
255 interrupts = <0 95 4>;
259 compatible = "arm,armv7-timer";
260 interrupts = <1 13 0xf08>,
267 compatible = "arm,cortex-a15-pmu";
268 cluster = <&cluster0>;
269 interrupts = <0 68 4>,
274 compatible = "arm,cortex-a7-pmu";
275 cluster = <&cluster1>;
276 interrupts = <0 128 4>,
282 /* Reference 24MHz clock */
283 compatible = "fixed-clock";
285 clock-frequency = <24000000>;
286 clock-output-names = "oscclk6a";
290 compatible = "arm,psci";
292 cpu_suspend = <0x80100001>;
293 cpu_off = <0x80100002>;
294 cpu_on = <0x80100003>;
295 migrate = <0x80100004>;
299 compatible = "arm,vexpress,config-bus";
300 arm,vexpress,config-bridge = <&v2m_sysreg>;
303 /* A15 PLL 0 reference clock */
304 compatible = "arm,vexpress-osc";
305 arm,vexpress-sysreg,func = <1 0>;
306 freq-range = <17000000 50000000>;
308 clock-output-names = "oscclk0";
312 /* A15 PLL 1 reference clock */
313 compatible = "arm,vexpress-osc";
314 arm,vexpress-sysreg,func = <1 1>;
315 freq-range = <17000000 50000000>;
317 clock-output-names = "oscclk1";
321 /* A7 PLL 0 reference clock */
322 compatible = "arm,vexpress-osc";
323 arm,vexpress-sysreg,func = <1 2>;
324 freq-range = <17000000 50000000>;
326 clock-output-names = "oscclk2";
330 /* A7 PLL 1 reference clock */
331 compatible = "arm,vexpress-osc";
332 arm,vexpress-sysreg,func = <1 3>;
333 freq-range = <17000000 50000000>;
335 clock-output-names = "oscclk3";
339 /* External AXI master clock */
340 compatible = "arm,vexpress-osc";
341 arm,vexpress-sysreg,func = <1 4>;
342 freq-range = <20000000 40000000>;
344 clock-output-names = "oscclk4";
348 /* HDLCD PLL reference clock */
349 compatible = "arm,vexpress-osc";
350 arm,vexpress-sysreg,func = <1 5>;
351 freq-range = <23750000 165000000>;
353 clock-output-names = "oscclk5";
357 /* Static memory controller clock */
358 compatible = "arm,vexpress-osc";
359 arm,vexpress-sysreg,func = <1 6>;
360 freq-range = <20000000 40000000>;
362 clock-output-names = "oscclk6";
366 /* SYS PLL reference clock */
367 compatible = "arm,vexpress-osc";
368 arm,vexpress-sysreg,func = <1 7>;
369 freq-range = <17000000 50000000>;
371 clock-output-names = "oscclk7";
375 /* DDR2 PLL reference clock */
376 compatible = "arm,vexpress-osc";
377 arm,vexpress-sysreg,func = <1 8>;
378 freq-range = <20000000 50000000>;
380 clock-output-names = "oscclk8";
384 /* A15 CPU core voltage */
385 compatible = "arm,vexpress-volt";
386 arm,vexpress-sysreg,func = <2 0>;
387 regulator-name = "A15 Vcore";
388 regulator-min-microvolt = <800000>;
389 regulator-max-microvolt = <1050000>;
395 /* A7 CPU core voltage */
396 compatible = "arm,vexpress-volt";
397 arm,vexpress-sysreg,func = <2 1>;
398 regulator-name = "A7 Vcore";
399 regulator-min-microvolt = <800000>;
400 regulator-max-microvolt = <1050000>;
406 /* Total current for the two A15 cores */
407 compatible = "arm,vexpress-amp";
408 arm,vexpress-sysreg,func = <3 0>;
413 /* Total current for the three A7 cores */
414 compatible = "arm,vexpress-amp";
415 arm,vexpress-sysreg,func = <3 1>;
420 /* DCC internal temperature */
421 compatible = "arm,vexpress-temp";
422 arm,vexpress-sysreg,func = <4 0>;
427 /* Total power for the two A15 cores */
428 compatible = "arm,vexpress-power";
429 arm,vexpress-sysreg,func = <12 0>;
433 /* Total power for the three A7 cores */
434 compatible = "arm,vexpress-power";
435 arm,vexpress-sysreg,func = <12 1>;
440 /* Total energy for the two A15 cores */
441 compatible = "arm,vexpress-energy";
442 arm,vexpress-sysreg,func = <13 0>;
447 /* Total energy for the three A7 cores */
448 compatible = "arm,vexpress-energy";
449 arm,vexpress-sysreg,func = <13 2>;
455 compatible = "simple-bus";
457 #address-cells = <2>;
459 ranges = <0 0 0 0x08000000 0x04000000>,
460 <1 0 0 0x14000000 0x04000000>,
461 <2 0 0 0x18000000 0x04000000>,
462 <3 0 0 0x1c000000 0x04000000>,
463 <4 0 0 0x0c000000 0x04000000>,
464 <5 0 0 0x10000000 0x04000000>;
466 #interrupt-cells = <1>;
467 interrupt-map-mask = <0 0 63>;
468 interrupt-map = <0 0 0 &gic 0 0 4>,
478 <0 0 10 &gic 0 10 4>,
479 <0 0 11 &gic 0 11 4>,
480 <0 0 12 &gic 0 12 4>,
481 <0 0 13 &gic 0 13 4>,
482 <0 0 14 &gic 0 14 4>,
483 <0 0 15 &gic 0 15 4>,
484 <0 0 16 &gic 0 16 4>,
485 <0 0 17 &gic 0 17 4>,
486 <0 0 18 &gic 0 18 4>,
487 <0 0 19 &gic 0 19 4>,
488 <0 0 20 &gic 0 20 4>,
489 <0 0 21 &gic 0 21 4>,
490 <0 0 22 &gic 0 22 4>,
491 <0 0 23 &gic 0 23 4>,
492 <0 0 24 &gic 0 24 4>,
493 <0 0 25 &gic 0 25 4>,
494 <0 0 26 &gic 0 26 4>,
495 <0 0 27 &gic 0 27 4>,
496 <0 0 28 &gic 0 28 4>,
497 <0 0 29 &gic 0 29 4>,
498 <0 0 30 &gic 0 30 4>,
499 <0 0 31 &gic 0 31 4>,
500 <0 0 32 &gic 0 32 4>,
501 <0 0 33 &gic 0 33 4>,
502 <0 0 34 &gic 0 34 4>,
503 <0 0 35 &gic 0 35 4>,
504 <0 0 36 &gic 0 36 4>,
505 <0 0 37 &gic 0 37 4>,
506 <0 0 38 &gic 0 38 4>,
507 <0 0 39 &gic 0 39 4>,
508 <0 0 40 &gic 0 40 4>,
509 <0 0 41 &gic 0 41 4>,
510 <0 0 42 &gic 0 42 4>;
512 /include/ "vexpress-v2m-rs1.dtsi"