2 * ARM Ltd. Versatile Express
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
12 /memreserve/ 0xbf000000 0x01000000;
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
40 compatible = "arm,cortex-a15";
46 compatible = "arm,cortex-a15";
52 device_type = "memory";
53 reg = <0 0x80000000 0 0x40000000>;
57 compatible = "arm,hdlcd";
58 reg = <0 0x2b000000 0 0x1000>;
59 interrupts = <0 85 4>;
61 clock-names = "pxlclk";
62 mode = "1024x768-16@60";
63 framebuffer = <0 0xff000000 0 0x01000000>;
66 memory-controller@2b0a0000 {
67 compatible = "arm,pl341", "arm,primecell";
68 reg = <0 0x2b0a0000 0 0x1000>;
70 clock-names = "apb_pclk";
74 compatible = "arm,sp805", "arm,primecell";
76 reg = <0 0x2b060000 0 0x1000>;
77 interrupts = <0 98 4>;
79 clock-names = "apb_pclk";
82 gic: interrupt-controller@2c001000 {
83 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
87 reg = <0 0x2c001000 0 0x1000>,
88 <0 0x2c002000 0 0x1000>,
89 <0 0x2c004000 0 0x2000>,
90 <0 0x2c006000 0 0x2000>;
91 interrupts = <1 9 0xf04>;
94 memory-controller@7ffd0000 {
95 compatible = "arm,pl354", "arm,primecell";
96 reg = <0 0x7ffd0000 0 0x1000>;
97 interrupts = <0 86 4>,
100 clock-names = "apb_pclk";
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0 0x7ffb0000 0 0x1000>;
106 interrupts = <0 92 4>,
112 clock-names = "apb_pclk";
116 compatible = "arm,armv7-timer";
117 interrupts = <1 13 0xf08>,
124 compatible = "arm,cortex-a15-pmu";
125 interrupts = <0 68 4>,
130 compatible = "arm,vexpress,config-bus";
131 arm,vexpress,config-bridge = <&v2m_sysreg>;
134 /* CPU PLL reference clock */
135 compatible = "arm,vexpress-osc";
136 arm,vexpress-sysreg,func = <1 0>;
137 freq-range = <50000000 60000000>;
139 clock-output-names = "oscclk0";
143 /* Multiplexed AXI master clock */
144 compatible = "arm,vexpress-osc";
145 arm,vexpress-sysreg,func = <1 4>;
146 freq-range = <20000000 40000000>;
148 clock-output-names = "oscclk4";
152 /* HDLCD PLL reference clock */
153 compatible = "arm,vexpress-osc";
154 arm,vexpress-sysreg,func = <1 5>;
155 freq-range = <23750000 165000000>;
157 clock-output-names = "oscclk5";
162 compatible = "arm,vexpress-osc";
163 arm,vexpress-sysreg,func = <1 6>;
164 freq-range = <20000000 50000000>;
166 clock-output-names = "oscclk6";
170 /* SYS PLL reference clock */
171 compatible = "arm,vexpress-osc";
172 arm,vexpress-sysreg,func = <1 7>;
173 freq-range = <20000000 60000000>;
175 clock-output-names = "oscclk7";
179 /* DDR2 PLL reference clock */
180 compatible = "arm,vexpress-osc";
181 arm,vexpress-sysreg,func = <1 8>;
182 freq-range = <40000000 40000000>;
184 clock-output-names = "oscclk8";
188 /* CPU core voltage */
189 compatible = "arm,vexpress-volt";
190 arm,vexpress-sysreg,func = <2 0>;
191 regulator-name = "Cores";
192 regulator-min-microvolt = <800000>;
193 regulator-max-microvolt = <1050000>;
199 /* Total current for the two cores */
200 compatible = "arm,vexpress-amp";
201 arm,vexpress-sysreg,func = <3 0>;
206 /* DCC internal temperature */
207 compatible = "arm,vexpress-temp";
208 arm,vexpress-sysreg,func = <4 0>;
214 compatible = "arm,vexpress-power";
215 arm,vexpress-sysreg,func = <12 0>;
221 compatible = "arm,vexpress-energy";
222 arm,vexpress-sysreg,func = <13 0>;
228 compatible = "simple-bus";
230 #address-cells = <2>;
232 ranges = <0 0 0 0x08000000 0x04000000>,
233 <1 0 0 0x14000000 0x04000000>,
234 <2 0 0 0x18000000 0x04000000>,
235 <3 0 0 0x1c000000 0x04000000>,
236 <4 0 0 0x0c000000 0x04000000>,
237 <5 0 0 0x10000000 0x04000000>;
239 #interrupt-cells = <1>;
240 interrupt-map-mask = <0 0 63>;
241 interrupt-map = <0 0 0 &gic 0 0 4>,
251 <0 0 10 &gic 0 10 4>,
252 <0 0 11 &gic 0 11 4>,
253 <0 0 12 &gic 0 12 4>,
254 <0 0 13 &gic 0 13 4>,
255 <0 0 14 &gic 0 14 4>,
256 <0 0 15 &gic 0 15 4>,
257 <0 0 16 &gic 0 16 4>,
258 <0 0 17 &gic 0 17 4>,
259 <0 0 18 &gic 0 18 4>,
260 <0 0 19 &gic 0 19 4>,
261 <0 0 20 &gic 0 20 4>,
262 <0 0 21 &gic 0 21 4>,
263 <0 0 22 &gic 0 22 4>,
264 <0 0 23 &gic 0 23 4>,
265 <0 0 24 &gic 0 24 4>,
266 <0 0 25 &gic 0 25 4>,
267 <0 0 26 &gic 0 26 4>,
268 <0 0 27 &gic 0 27 4>,
269 <0 0 28 &gic 0 28 4>,
270 <0 0 29 &gic 0 29 4>,
271 <0 0 30 &gic 0 30 4>,
272 <0 0 31 &gic 0 31 4>,
273 <0 0 32 &gic 0 32 4>,
274 <0 0 33 &gic 0 33 4>,
275 <0 0 34 &gic 0 34 4>,
276 <0 0 35 &gic 0 35 4>,
277 <0 0 36 &gic 0 36 4>,
278 <0 0 37 &gic 0 37 4>,
279 <0 0 38 &gic 0 38 4>,
280 <0 0 39 &gic 0 39 4>,
281 <0 0 40 &gic 0 40 4>,
282 <0 0 41 &gic 0 41 4>,
283 <0 0 42 &gic 0 42 4>;
285 /include/ "vexpress-v2m-rs1.dtsi"