1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
20 pcie-controller@00003000 {
21 compatible = "nvidia,tegra30-pcie";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
40 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
41 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
42 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
43 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
44 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
46 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
47 <&tegra_car TEGRA30_CLK_AFI>,
48 <&tegra_car TEGRA30_CLK_PLL_E>,
49 <&tegra_car TEGRA30_CLK_CML0>;
50 clock-names = "pex", "afi", "pll_e", "cml";
51 resets = <&tegra_car 70>,
54 reset-names = "pex", "afi", "pcie_x";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
80 nvidia,num-lanes = <2>;
85 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
86 reg = <0x001800 0 0 0 0>;
93 nvidia,num-lanes = <2>;
98 compatible = "nvidia,tegra30-host1x", "simple-bus";
99 reg = <0x50000000 0x00024000>;
100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
101 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
102 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
103 resets = <&tegra_car 28>;
104 reset-names = "host1x";
106 #address-cells = <1>;
109 ranges = <0x54000000 0x54000000 0x04000000>;
112 compatible = "nvidia,tegra30-mpe";
113 reg = <0x54040000 0x00040000>;
114 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA30_CLK_MPE>;
116 resets = <&tegra_car 60>;
121 compatible = "nvidia,tegra30-vi";
122 reg = <0x54080000 0x00040000>;
123 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&tegra_car TEGRA30_CLK_VI>;
125 resets = <&tegra_car 20>;
130 compatible = "nvidia,tegra30-epp";
131 reg = <0x540c0000 0x00040000>;
132 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA30_CLK_EPP>;
134 resets = <&tegra_car 19>;
139 compatible = "nvidia,tegra30-isp";
140 reg = <0x54100000 0x00040000>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA30_CLK_ISP>;
143 resets = <&tegra_car 23>;
148 compatible = "nvidia,tegra30-gr2d";
149 reg = <0x54140000 0x00040000>;
150 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 resets = <&tegra_car 21>;
157 compatible = "nvidia,tegra30-gr3d";
158 reg = <0x54180000 0x00040000>;
159 clocks = <&tegra_car TEGRA30_CLK_GR3D
160 &tegra_car TEGRA30_CLK_GR3D2>;
161 clock-names = "3d", "3d2";
162 resets = <&tegra_car 24>,
164 reset-names = "3d", "3d2";
168 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
169 reg = <0x54200000 0x00040000>;
170 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
172 <&tegra_car TEGRA30_CLK_PLL_P>;
173 clock-names = "dc", "parent";
174 resets = <&tegra_car 27>;
185 compatible = "nvidia,tegra30-dc";
186 reg = <0x54240000 0x00040000>;
187 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
189 <&tegra_car TEGRA30_CLK_PLL_P>;
190 clock-names = "dc", "parent";
191 resets = <&tegra_car 26>;
202 compatible = "nvidia,tegra30-hdmi";
203 reg = <0x54280000 0x00040000>;
204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
206 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
207 clock-names = "hdmi", "parent";
208 resets = <&tegra_car 51>;
209 reset-names = "hdmi";
214 compatible = "nvidia,tegra30-tvo";
215 reg = <0x542c0000 0x00040000>;
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&tegra_car TEGRA30_CLK_TVO>;
222 compatible = "nvidia,tegra30-dsi";
223 reg = <0x54300000 0x00040000>;
224 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
225 resets = <&tegra_car 48>;
232 compatible = "arm,cortex-a9-twd-timer";
233 reg = <0x50040600 0x20>;
234 interrupts = <GIC_PPI 13
235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
236 clocks = <&tegra_car TEGRA30_CLK_TWD>;
239 intc: interrupt-controller@50041000 {
240 compatible = "arm,cortex-a9-gic";
241 reg = <0x50041000 0x1000
243 interrupt-controller;
244 #interrupt-cells = <3>;
247 cache-controller@50043000 {
248 compatible = "arm,pl310-cache";
249 reg = <0x50043000 0x1000>;
250 arm,data-latency = <6 6 2>;
251 arm,tag-latency = <5 5 2>;
257 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
258 reg = <0x60005000 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
268 tegra_car: clock@60006000 {
269 compatible = "nvidia,tegra30-car";
270 reg = <0x60006000 0x1000>;
275 flow-controller@60007000 {
276 compatible = "nvidia,tegra30-flowctrl";
277 reg = <0x60007000 0x1000>;
280 apbdma: dma@6000a000 {
281 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
282 reg = <0x6000a000 0x1400>;
283 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
316 resets = <&tegra_car 34>;
322 compatible = "nvidia,tegra30-ahb";
323 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
326 gpio: gpio@6000d000 {
327 compatible = "nvidia,tegra30-gpio";
328 reg = <0x6000d000 0x1000>;
329 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
339 #interrupt-cells = <2>;
340 interrupt-controller;
344 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
345 reg = <0x70000800 0x64 /* Chip revision */
346 0x70000008 0x04>; /* Strapping options */
349 pinmux: pinmux@70000868 {
350 compatible = "nvidia,tegra30-pinmux";
351 reg = <0x70000868 0xd4 /* Pad control registers */
352 0x70003000 0x3e4>; /* Mux registers */
356 * There are two serial driver i.e. 8250 based simple serial
357 * driver and APB DMA based serial driver for higher baudrate
358 * and performace. To enable the 8250 based driver, the compatible
359 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
360 * the APB DMA based serial driver, the comptible is
361 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
363 uarta: serial@70006000 {
364 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
365 reg = <0x70006000 0x40>;
367 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
369 resets = <&tegra_car 6>;
370 reset-names = "serial";
371 dmas = <&apbdma 8>, <&apbdma 8>;
372 dma-names = "rx", "tx";
376 uartb: serial@70006040 {
377 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
378 reg = <0x70006040 0x40>;
380 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
382 resets = <&tegra_car 7>;
383 reset-names = "serial";
384 dmas = <&apbdma 9>, <&apbdma 9>;
385 dma-names = "rx", "tx";
389 uartc: serial@70006200 {
390 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
391 reg = <0x70006200 0x100>;
393 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
395 resets = <&tegra_car 55>;
396 reset-names = "serial";
397 dmas = <&apbdma 10>, <&apbdma 10>;
398 dma-names = "rx", "tx";
402 uartd: serial@70006300 {
403 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
404 reg = <0x70006300 0x100>;
406 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
408 resets = <&tegra_car 65>;
409 reset-names = "serial";
410 dmas = <&apbdma 19>, <&apbdma 19>;
411 dma-names = "rx", "tx";
415 uarte: serial@70006400 {
416 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
417 reg = <0x70006400 0x100>;
419 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
421 resets = <&tegra_car 66>;
422 reset-names = "serial";
423 dmas = <&apbdma 20>, <&apbdma 20>;
424 dma-names = "rx", "tx";
429 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
430 reg = <0x7000a000 0x100>;
432 clocks = <&tegra_car TEGRA30_CLK_PWM>;
433 resets = <&tegra_car 17>;
439 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
440 reg = <0x7000e000 0x100>;
441 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&tegra_car TEGRA30_CLK_RTC>;
446 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
447 reg = <0x7000c000 0x100>;
448 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
451 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
452 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
453 clock-names = "div-clk", "fast-clk";
454 resets = <&tegra_car 12>;
456 dmas = <&apbdma 21>, <&apbdma 21>;
457 dma-names = "rx", "tx";
462 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
463 reg = <0x7000c400 0x100>;
464 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
467 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
468 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
469 clock-names = "div-clk", "fast-clk";
470 resets = <&tegra_car 54>;
472 dmas = <&apbdma 22>, <&apbdma 22>;
473 dma-names = "rx", "tx";
478 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
479 reg = <0x7000c500 0x100>;
480 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
483 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
484 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
485 clock-names = "div-clk", "fast-clk";
486 resets = <&tegra_car 67>;
488 dmas = <&apbdma 23>, <&apbdma 23>;
489 dma-names = "rx", "tx";
494 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
495 reg = <0x7000c700 0x100>;
496 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
499 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
500 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
501 resets = <&tegra_car 103>;
503 clock-names = "div-clk", "fast-clk";
504 dmas = <&apbdma 26>, <&apbdma 26>;
505 dma-names = "rx", "tx";
510 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
511 reg = <0x7000d000 0x100>;
512 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
515 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
516 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
517 clock-names = "div-clk", "fast-clk";
518 resets = <&tegra_car 47>;
520 dmas = <&apbdma 24>, <&apbdma 24>;
521 dma-names = "rx", "tx";
526 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
527 reg = <0x7000d400 0x200>;
528 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
531 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
532 resets = <&tegra_car 41>;
534 dmas = <&apbdma 15>, <&apbdma 15>;
535 dma-names = "rx", "tx";
540 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
541 reg = <0x7000d600 0x200>;
542 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
545 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
546 resets = <&tegra_car 44>;
548 dmas = <&apbdma 16>, <&apbdma 16>;
549 dma-names = "rx", "tx";
554 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
555 reg = <0x7000d800 0x200>;
556 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
559 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
560 resets = <&tegra_car 46>;
562 dmas = <&apbdma 17>, <&apbdma 17>;
563 dma-names = "rx", "tx";
568 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
569 reg = <0x7000da00 0x200>;
570 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
571 #address-cells = <1>;
573 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
574 resets = <&tegra_car 68>;
576 dmas = <&apbdma 18>, <&apbdma 18>;
577 dma-names = "rx", "tx";
582 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
583 reg = <0x7000dc00 0x200>;
584 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
585 #address-cells = <1>;
587 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
588 resets = <&tegra_car 104>;
590 dmas = <&apbdma 27>, <&apbdma 27>;
591 dma-names = "rx", "tx";
596 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
597 reg = <0x7000de00 0x200>;
598 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
599 #address-cells = <1>;
601 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
602 resets = <&tegra_car 106>;
604 dmas = <&apbdma 28>, <&apbdma 28>;
605 dma-names = "rx", "tx";
610 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
611 reg = <0x7000e200 0x100>;
612 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&tegra_car TEGRA30_CLK_KBC>;
614 resets = <&tegra_car 36>;
620 compatible = "nvidia,tegra30-pmc";
621 reg = <0x7000e400 0x400>;
622 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
623 clock-names = "pclk", "clk32k_in";
626 memory-controller@7000f000 {
627 compatible = "nvidia,tegra30-mc";
628 reg = <0x7000f000 0x010
632 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
636 compatible = "nvidia,tegra30-smmu";
637 reg = <0x7000f010 0x02c
640 nvidia,#asids = <4>; /* # of ASIDs */
641 dma-window = <0 0x40000000>; /* IOVA start & length */
646 compatible = "nvidia,tegra30-efuse";
647 reg = <0x7000f800 0x400>;
648 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
649 clock-names = "fuse";
650 resets = <&tegra_car 39>;
651 reset-names = "fuse";
655 compatible = "nvidia,tegra30-ahub";
656 reg = <0x70080000 0x200
658 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
660 <&tegra_car TEGRA30_CLK_APBIF>;
661 clock-names = "d_audio", "apbif";
662 resets = <&tegra_car 106>, /* d_audio */
663 <&tegra_car 107>, /* apbif */
664 <&tegra_car 30>, /* i2s0 */
665 <&tegra_car 11>, /* i2s1 */
666 <&tegra_car 18>, /* i2s2 */
667 <&tegra_car 101>, /* i2s3 */
668 <&tegra_car 102>, /* i2s4 */
669 <&tegra_car 108>, /* dam0 */
670 <&tegra_car 109>, /* dam1 */
671 <&tegra_car 110>, /* dam2 */
672 <&tegra_car 10>; /* spdif */
673 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
674 "i2s3", "i2s4", "dam0", "dam1", "dam2",
676 dmas = <&apbdma 1>, <&apbdma 1>,
677 <&apbdma 2>, <&apbdma 2>,
678 <&apbdma 3>, <&apbdma 3>,
679 <&apbdma 4>, <&apbdma 4>;
680 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
683 #address-cells = <1>;
686 tegra_i2s0: i2s@70080300 {
687 compatible = "nvidia,tegra30-i2s";
688 reg = <0x70080300 0x100>;
689 nvidia,ahub-cif-ids = <4 4>;
690 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
691 resets = <&tegra_car 30>;
696 tegra_i2s1: i2s@70080400 {
697 compatible = "nvidia,tegra30-i2s";
698 reg = <0x70080400 0x100>;
699 nvidia,ahub-cif-ids = <5 5>;
700 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
701 resets = <&tegra_car 11>;
706 tegra_i2s2: i2s@70080500 {
707 compatible = "nvidia,tegra30-i2s";
708 reg = <0x70080500 0x100>;
709 nvidia,ahub-cif-ids = <6 6>;
710 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
711 resets = <&tegra_car 18>;
716 tegra_i2s3: i2s@70080600 {
717 compatible = "nvidia,tegra30-i2s";
718 reg = <0x70080600 0x100>;
719 nvidia,ahub-cif-ids = <7 7>;
720 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
721 resets = <&tegra_car 101>;
726 tegra_i2s4: i2s@70080700 {
727 compatible = "nvidia,tegra30-i2s";
728 reg = <0x70080700 0x100>;
729 nvidia,ahub-cif-ids = <8 8>;
730 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
731 resets = <&tegra_car 102>;
738 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
739 reg = <0x78000000 0x200>;
740 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
742 resets = <&tegra_car 14>;
743 reset-names = "sdhci";
748 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
749 reg = <0x78000200 0x200>;
750 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
752 resets = <&tegra_car 9>;
753 reset-names = "sdhci";
758 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
759 reg = <0x78000400 0x200>;
760 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
762 resets = <&tegra_car 69>;
763 reset-names = "sdhci";
768 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
769 reg = <0x78000600 0x200>;
770 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
772 resets = <&tegra_car 15>;
773 reset-names = "sdhci";
778 compatible = "nvidia,tegra30-ehci", "usb-ehci";
779 reg = <0x7d000000 0x4000>;
780 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&tegra_car TEGRA30_CLK_USBD>;
783 resets = <&tegra_car 22>;
785 nvidia,needs-double-reset;
786 nvidia,phy = <&phy1>;
790 phy1: usb-phy@7d000000 {
791 compatible = "nvidia,tegra30-usb-phy";
792 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
794 clocks = <&tegra_car TEGRA30_CLK_USBD>,
795 <&tegra_car TEGRA30_CLK_PLL_U>,
796 <&tegra_car TEGRA30_CLK_USBD>;
797 clock-names = "reg", "pll_u", "utmi-pads";
798 resets = <&tegra_car 22>, <&tegra_car 22>;
799 reset-names = "usb", "utmi-pads";
800 nvidia,hssync-start-delay = <9>;
801 nvidia,idle-wait-delay = <17>;
802 nvidia,elastic-limit = <16>;
803 nvidia,term-range-adj = <6>;
804 nvidia,xcvr-setup = <51>;
805 nvidia.xcvr-setup-use-fuses;
806 nvidia,xcvr-lsfslew = <1>;
807 nvidia,xcvr-lsrslew = <1>;
808 nvidia,xcvr-hsslew = <32>;
809 nvidia,hssquelch-level = <2>;
810 nvidia,hsdiscon-level = <5>;
811 nvidia,has-utmi-pad-registers;
816 compatible = "nvidia,tegra30-ehci", "usb-ehci";
817 reg = <0x7d004000 0x4000>;
818 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&tegra_car TEGRA30_CLK_USB2>;
821 resets = <&tegra_car 58>;
823 nvidia,phy = <&phy2>;
827 phy2: usb-phy@7d004000 {
828 compatible = "nvidia,tegra30-usb-phy";
829 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
831 clocks = <&tegra_car TEGRA30_CLK_USB2>,
832 <&tegra_car TEGRA30_CLK_PLL_U>,
833 <&tegra_car TEGRA30_CLK_USBD>;
834 clock-names = "reg", "pll_u", "utmi-pads";
835 resets = <&tegra_car 58>, <&tegra_car 22>;
836 reset-names = "usb", "utmi-pads";
837 nvidia,hssync-start-delay = <9>;
838 nvidia,idle-wait-delay = <17>;
839 nvidia,elastic-limit = <16>;
840 nvidia,term-range-adj = <6>;
841 nvidia,xcvr-setup = <51>;
842 nvidia.xcvr-setup-use-fuses;
843 nvidia,xcvr-lsfslew = <2>;
844 nvidia,xcvr-lsrslew = <2>;
845 nvidia,xcvr-hsslew = <32>;
846 nvidia,hssquelch-level = <2>;
847 nvidia,hsdiscon-level = <5>;
852 compatible = "nvidia,tegra30-ehci", "usb-ehci";
853 reg = <0x7d008000 0x4000>;
854 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&tegra_car TEGRA30_CLK_USB3>;
857 resets = <&tegra_car 59>;
859 nvidia,phy = <&phy3>;
863 phy3: usb-phy@7d008000 {
864 compatible = "nvidia,tegra30-usb-phy";
865 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
867 clocks = <&tegra_car TEGRA30_CLK_USB3>,
868 <&tegra_car TEGRA30_CLK_PLL_U>,
869 <&tegra_car TEGRA30_CLK_USBD>;
870 clock-names = "reg", "pll_u", "utmi-pads";
871 resets = <&tegra_car 59>, <&tegra_car 22>;
872 reset-names = "usb", "utmi-pads";
873 nvidia,hssync-start-delay = <0>;
874 nvidia,idle-wait-delay = <17>;
875 nvidia,elastic-limit = <16>;
876 nvidia,term-range-adj = <6>;
877 nvidia,xcvr-setup = <51>;
878 nvidia.xcvr-setup-use-fuses;
879 nvidia,xcvr-lsfslew = <2>;
880 nvidia,xcvr-lsrslew = <2>;
881 nvidia,xcvr-hsslew = <32>;
882 nvidia,hssquelch-level = <2>;
883 nvidia,hsdiscon-level = <5>;
888 #address-cells = <1>;
893 compatible = "arm,cortex-a9";
899 compatible = "arm,cortex-a9";
905 compatible = "arm,cortex-a9";
911 compatible = "arm,cortex-a9";
917 compatible = "arm,cortex-a9-pmu";
918 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;