1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
20 pcie-controller@00003000 {
21 compatible = "nvidia,tegra30-pcie";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
40 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
41 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
42 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
43 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
44 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
46 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
47 <&tegra_car TEGRA30_CLK_AFI>,
48 <&tegra_car TEGRA30_CLK_PLL_E>,
49 <&tegra_car TEGRA30_CLK_CML0>;
50 clock-names = "pex", "afi", "pll_e", "cml";
51 resets = <&tegra_car 70>,
54 reset-names = "pex", "afi", "pcie_x";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
80 nvidia,num-lanes = <2>;
85 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
86 reg = <0x001800 0 0 0 0>;
93 nvidia,num-lanes = <2>;
98 compatible = "nvidia,tegra30-host1x", "simple-bus";
99 reg = <0x50000000 0x00024000>;
100 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
101 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
102 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
103 resets = <&tegra_car 28>;
104 reset-names = "host1x";
106 #address-cells = <1>;
109 ranges = <0x54000000 0x54000000 0x04000000>;
112 compatible = "nvidia,tegra30-mpe";
113 reg = <0x54040000 0x00040000>;
114 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA30_CLK_MPE>;
116 resets = <&tegra_car 60>;
121 compatible = "nvidia,tegra30-vi";
122 reg = <0x54080000 0x00040000>;
123 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&tegra_car TEGRA30_CLK_VI>;
125 resets = <&tegra_car 20>;
130 compatible = "nvidia,tegra30-epp";
131 reg = <0x540c0000 0x00040000>;
132 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA30_CLK_EPP>;
134 resets = <&tegra_car 19>;
139 compatible = "nvidia,tegra30-isp";
140 reg = <0x54100000 0x00040000>;
141 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA30_CLK_ISP>;
143 resets = <&tegra_car 23>;
148 compatible = "nvidia,tegra30-gr2d";
149 reg = <0x54140000 0x00040000>;
150 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
152 resets = <&tegra_car 21>;
157 compatible = "nvidia,tegra30-gr3d";
158 reg = <0x54180000 0x00040000>;
159 clocks = <&tegra_car TEGRA30_CLK_GR3D
160 &tegra_car TEGRA30_CLK_GR3D2>;
161 clock-names = "3d", "3d2";
162 resets = <&tegra_car 24>,
164 reset-names = "3d", "3d2";
168 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
169 reg = <0x54200000 0x00040000>;
170 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
172 <&tegra_car TEGRA30_CLK_PLL_P>;
173 clock-names = "dc", "parent";
174 resets = <&tegra_car 27>;
185 compatible = "nvidia,tegra30-dc";
186 reg = <0x54240000 0x00040000>;
187 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
189 <&tegra_car TEGRA30_CLK_PLL_P>;
190 clock-names = "dc", "parent";
191 resets = <&tegra_car 26>;
202 compatible = "nvidia,tegra30-hdmi";
203 reg = <0x54280000 0x00040000>;
204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
206 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
207 clock-names = "hdmi", "parent";
208 resets = <&tegra_car 51>;
209 reset-names = "hdmi";
214 compatible = "nvidia,tegra30-tvo";
215 reg = <0x542c0000 0x00040000>;
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&tegra_car TEGRA30_CLK_TVO>;
222 compatible = "nvidia,tegra30-dsi";
223 reg = <0x54300000 0x00040000>;
224 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
225 resets = <&tegra_car 48>;
232 compatible = "arm,cortex-a9-twd-timer";
233 reg = <0x50040600 0x20>;
234 interrupts = <GIC_PPI 13
235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
236 clocks = <&tegra_car TEGRA30_CLK_TWD>;
239 intc: interrupt-controller@50041000 {
240 compatible = "arm,cortex-a9-gic";
241 reg = <0x50041000 0x1000
243 interrupt-controller;
244 #interrupt-cells = <3>;
247 cache-controller@50043000 {
248 compatible = "arm,pl310-cache";
249 reg = <0x50043000 0x1000>;
250 arm,data-latency = <6 6 2>;
251 arm,tag-latency = <5 5 2>;
257 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
258 reg = <0x60005000 0x400>;
259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
268 tegra_car: clock@60006000 {
269 compatible = "nvidia,tegra30-car";
270 reg = <0x60006000 0x1000>;
275 apbdma: dma@6000a000 {
276 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
277 reg = <0x6000a000 0x1400>;
278 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
311 resets = <&tegra_car 34>;
317 compatible = "nvidia,tegra30-ahb";
318 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
321 gpio: gpio@6000d000 {
322 compatible = "nvidia,tegra30-gpio";
323 reg = <0x6000d000 0x1000>;
324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
334 #interrupt-cells = <2>;
335 interrupt-controller;
339 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
340 reg = <0x70000800 0x64 /* Chip revision */
341 0x70000008 0x04>; /* Strapping options */
344 pinmux: pinmux@70000868 {
345 compatible = "nvidia,tegra30-pinmux";
346 reg = <0x70000868 0xd4 /* Pad control registers */
347 0x70003000 0x3e4>; /* Mux registers */
351 * There are two serial driver i.e. 8250 based simple serial
352 * driver and APB DMA based serial driver for higher baudrate
353 * and performace. To enable the 8250 based driver, the compatible
354 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
355 * the APB DMA based serial driver, the comptible is
356 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
358 uarta: serial@70006000 {
359 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
360 reg = <0x70006000 0x40>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
364 resets = <&tegra_car 6>;
365 reset-names = "serial";
366 dmas = <&apbdma 8>, <&apbdma 8>;
367 dma-names = "rx", "tx";
371 uartb: serial@70006040 {
372 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
373 reg = <0x70006040 0x40>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
377 resets = <&tegra_car 7>;
378 reset-names = "serial";
379 dmas = <&apbdma 9>, <&apbdma 9>;
380 dma-names = "rx", "tx";
384 uartc: serial@70006200 {
385 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
386 reg = <0x70006200 0x100>;
388 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
390 resets = <&tegra_car 55>;
391 reset-names = "serial";
392 dmas = <&apbdma 10>, <&apbdma 10>;
393 dma-names = "rx", "tx";
397 uartd: serial@70006300 {
398 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
399 reg = <0x70006300 0x100>;
401 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
403 resets = <&tegra_car 65>;
404 reset-names = "serial";
405 dmas = <&apbdma 19>, <&apbdma 19>;
406 dma-names = "rx", "tx";
410 uarte: serial@70006400 {
411 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
412 reg = <0x70006400 0x100>;
414 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
416 resets = <&tegra_car 66>;
417 reset-names = "serial";
418 dmas = <&apbdma 20>, <&apbdma 20>;
419 dma-names = "rx", "tx";
424 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
425 reg = <0x7000a000 0x100>;
427 clocks = <&tegra_car TEGRA30_CLK_PWM>;
428 resets = <&tegra_car 17>;
434 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
435 reg = <0x7000e000 0x100>;
436 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&tegra_car TEGRA30_CLK_RTC>;
441 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
442 reg = <0x7000c000 0x100>;
443 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
446 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
447 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
448 clock-names = "div-clk", "fast-clk";
449 resets = <&tegra_car 12>;
451 dmas = <&apbdma 21>, <&apbdma 21>;
452 dma-names = "rx", "tx";
457 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
458 reg = <0x7000c400 0x100>;
459 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
462 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
463 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
464 clock-names = "div-clk", "fast-clk";
465 resets = <&tegra_car 54>;
467 dmas = <&apbdma 22>, <&apbdma 22>;
468 dma-names = "rx", "tx";
473 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
474 reg = <0x7000c500 0x100>;
475 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
479 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
480 clock-names = "div-clk", "fast-clk";
481 resets = <&tegra_car 67>;
483 dmas = <&apbdma 23>, <&apbdma 23>;
484 dma-names = "rx", "tx";
489 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
490 reg = <0x7000c700 0x100>;
491 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
494 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
495 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
496 resets = <&tegra_car 103>;
498 clock-names = "div-clk", "fast-clk";
499 dmas = <&apbdma 26>, <&apbdma 26>;
500 dma-names = "rx", "tx";
505 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
506 reg = <0x7000d000 0x100>;
507 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
510 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
511 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
512 clock-names = "div-clk", "fast-clk";
513 resets = <&tegra_car 47>;
515 dmas = <&apbdma 24>, <&apbdma 24>;
516 dma-names = "rx", "tx";
521 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
522 reg = <0x7000d400 0x200>;
523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>;
526 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
527 resets = <&tegra_car 41>;
529 dmas = <&apbdma 15>, <&apbdma 15>;
530 dma-names = "rx", "tx";
535 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
536 reg = <0x7000d600 0x200>;
537 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
538 #address-cells = <1>;
540 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
541 resets = <&tegra_car 44>;
543 dmas = <&apbdma 16>, <&apbdma 16>;
544 dma-names = "rx", "tx";
549 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
550 reg = <0x7000d800 0x200>;
551 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>;
554 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
555 resets = <&tegra_car 46>;
557 dmas = <&apbdma 17>, <&apbdma 17>;
558 dma-names = "rx", "tx";
563 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
564 reg = <0x7000da00 0x200>;
565 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
569 resets = <&tegra_car 68>;
571 dmas = <&apbdma 18>, <&apbdma 18>;
572 dma-names = "rx", "tx";
577 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
578 reg = <0x7000dc00 0x200>;
579 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
582 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
583 resets = <&tegra_car 104>;
585 dmas = <&apbdma 27>, <&apbdma 27>;
586 dma-names = "rx", "tx";
591 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
592 reg = <0x7000de00 0x200>;
593 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
594 #address-cells = <1>;
596 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
597 resets = <&tegra_car 106>;
599 dmas = <&apbdma 28>, <&apbdma 28>;
600 dma-names = "rx", "tx";
605 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
606 reg = <0x7000e200 0x100>;
607 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&tegra_car TEGRA30_CLK_KBC>;
609 resets = <&tegra_car 36>;
615 compatible = "nvidia,tegra30-pmc";
616 reg = <0x7000e400 0x400>;
617 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
618 clock-names = "pclk", "clk32k_in";
621 memory-controller@7000f000 {
622 compatible = "nvidia,tegra30-mc";
623 reg = <0x7000f000 0x010
627 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
631 compatible = "nvidia,tegra30-smmu";
632 reg = <0x7000f010 0x02c
635 nvidia,#asids = <4>; /* # of ASIDs */
636 dma-window = <0 0x40000000>; /* IOVA start & length */
641 compatible = "nvidia,tegra30-efuse";
642 reg = <0x7000f800 0x400>;
643 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
644 clock-names = "fuse";
645 resets = <&tegra_car 39>;
646 reset-names = "fuse";
650 compatible = "nvidia,tegra30-ahub";
651 reg = <0x70080000 0x200
653 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
655 <&tegra_car TEGRA30_CLK_APBIF>;
656 clock-names = "d_audio", "apbif";
657 resets = <&tegra_car 106>, /* d_audio */
658 <&tegra_car 107>, /* apbif */
659 <&tegra_car 30>, /* i2s0 */
660 <&tegra_car 11>, /* i2s1 */
661 <&tegra_car 18>, /* i2s2 */
662 <&tegra_car 101>, /* i2s3 */
663 <&tegra_car 102>, /* i2s4 */
664 <&tegra_car 108>, /* dam0 */
665 <&tegra_car 109>, /* dam1 */
666 <&tegra_car 110>, /* dam2 */
667 <&tegra_car 10>; /* spdif */
668 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
669 "i2s3", "i2s4", "dam0", "dam1", "dam2",
671 dmas = <&apbdma 1>, <&apbdma 1>,
672 <&apbdma 2>, <&apbdma 2>,
673 <&apbdma 3>, <&apbdma 3>,
674 <&apbdma 4>, <&apbdma 4>;
675 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
678 #address-cells = <1>;
681 tegra_i2s0: i2s@70080300 {
682 compatible = "nvidia,tegra30-i2s";
683 reg = <0x70080300 0x100>;
684 nvidia,ahub-cif-ids = <4 4>;
685 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
686 resets = <&tegra_car 30>;
691 tegra_i2s1: i2s@70080400 {
692 compatible = "nvidia,tegra30-i2s";
693 reg = <0x70080400 0x100>;
694 nvidia,ahub-cif-ids = <5 5>;
695 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
696 resets = <&tegra_car 11>;
701 tegra_i2s2: i2s@70080500 {
702 compatible = "nvidia,tegra30-i2s";
703 reg = <0x70080500 0x100>;
704 nvidia,ahub-cif-ids = <6 6>;
705 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
706 resets = <&tegra_car 18>;
711 tegra_i2s3: i2s@70080600 {
712 compatible = "nvidia,tegra30-i2s";
713 reg = <0x70080600 0x100>;
714 nvidia,ahub-cif-ids = <7 7>;
715 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
716 resets = <&tegra_car 101>;
721 tegra_i2s4: i2s@70080700 {
722 compatible = "nvidia,tegra30-i2s";
723 reg = <0x70080700 0x100>;
724 nvidia,ahub-cif-ids = <8 8>;
725 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
726 resets = <&tegra_car 102>;
733 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
734 reg = <0x78000000 0x200>;
735 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
737 resets = <&tegra_car 14>;
738 reset-names = "sdhci";
743 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
744 reg = <0x78000200 0x200>;
745 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
747 resets = <&tegra_car 9>;
748 reset-names = "sdhci";
753 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
754 reg = <0x78000400 0x200>;
755 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
757 resets = <&tegra_car 69>;
758 reset-names = "sdhci";
763 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
764 reg = <0x78000600 0x200>;
765 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
767 resets = <&tegra_car 15>;
768 reset-names = "sdhci";
773 compatible = "nvidia,tegra30-ehci", "usb-ehci";
774 reg = <0x7d000000 0x4000>;
775 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&tegra_car TEGRA30_CLK_USBD>;
778 resets = <&tegra_car 22>;
780 nvidia,needs-double-reset;
781 nvidia,phy = <&phy1>;
785 phy1: usb-phy@7d000000 {
786 compatible = "nvidia,tegra30-usb-phy";
787 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
789 clocks = <&tegra_car TEGRA30_CLK_USBD>,
790 <&tegra_car TEGRA30_CLK_PLL_U>,
791 <&tegra_car TEGRA30_CLK_USBD>;
792 clock-names = "reg", "pll_u", "utmi-pads";
793 resets = <&tegra_car 22>, <&tegra_car 22>;
794 reset-names = "usb", "utmi-pads";
795 nvidia,hssync-start-delay = <9>;
796 nvidia,idle-wait-delay = <17>;
797 nvidia,elastic-limit = <16>;
798 nvidia,term-range-adj = <6>;
799 nvidia,xcvr-setup = <51>;
800 nvidia.xcvr-setup-use-fuses;
801 nvidia,xcvr-lsfslew = <1>;
802 nvidia,xcvr-lsrslew = <1>;
803 nvidia,xcvr-hsslew = <32>;
804 nvidia,hssquelch-level = <2>;
805 nvidia,hsdiscon-level = <5>;
806 nvidia,has-utmi-pad-registers;
811 compatible = "nvidia,tegra30-ehci", "usb-ehci";
812 reg = <0x7d004000 0x4000>;
813 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&tegra_car TEGRA30_CLK_USB2>;
816 resets = <&tegra_car 58>;
818 nvidia,phy = <&phy2>;
822 phy2: usb-phy@7d004000 {
823 compatible = "nvidia,tegra30-usb-phy";
824 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
826 clocks = <&tegra_car TEGRA30_CLK_USB2>,
827 <&tegra_car TEGRA30_CLK_PLL_U>,
828 <&tegra_car TEGRA30_CLK_USBD>;
829 clock-names = "reg", "pll_u", "utmi-pads";
830 resets = <&tegra_car 58>, <&tegra_car 22>;
831 reset-names = "usb", "utmi-pads";
832 nvidia,hssync-start-delay = <9>;
833 nvidia,idle-wait-delay = <17>;
834 nvidia,elastic-limit = <16>;
835 nvidia,term-range-adj = <6>;
836 nvidia,xcvr-setup = <51>;
837 nvidia.xcvr-setup-use-fuses;
838 nvidia,xcvr-lsfslew = <2>;
839 nvidia,xcvr-lsrslew = <2>;
840 nvidia,xcvr-hsslew = <32>;
841 nvidia,hssquelch-level = <2>;
842 nvidia,hsdiscon-level = <5>;
847 compatible = "nvidia,tegra30-ehci", "usb-ehci";
848 reg = <0x7d008000 0x4000>;
849 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&tegra_car TEGRA30_CLK_USB3>;
852 resets = <&tegra_car 59>;
854 nvidia,phy = <&phy3>;
858 phy3: usb-phy@7d008000 {
859 compatible = "nvidia,tegra30-usb-phy";
860 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
862 clocks = <&tegra_car TEGRA30_CLK_USB3>,
863 <&tegra_car TEGRA30_CLK_PLL_U>,
864 <&tegra_car TEGRA30_CLK_USBD>;
865 clock-names = "reg", "pll_u", "utmi-pads";
866 resets = <&tegra_car 59>, <&tegra_car 22>;
867 reset-names = "usb", "utmi-pads";
868 nvidia,hssync-start-delay = <0>;
869 nvidia,idle-wait-delay = <17>;
870 nvidia,elastic-limit = <16>;
871 nvidia,term-range-adj = <6>;
872 nvidia,xcvr-setup = <51>;
873 nvidia.xcvr-setup-use-fuses;
874 nvidia,xcvr-lsfslew = <2>;
875 nvidia,xcvr-lsrslew = <2>;
876 nvidia,xcvr-hsslew = <32>;
877 nvidia,hssquelch-level = <2>;
878 nvidia,hsdiscon-level = <5>;
883 #address-cells = <1>;
888 compatible = "arm,cortex-a9";
894 compatible = "arm,cortex-a9";
900 compatible = "arm,cortex-a9";
906 compatible = "arm,cortex-a9";
912 compatible = "arm,cortex-a9-pmu";
913 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;