1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include "skeleton.dtsi"
13 compatible = "nvidia,tegra124";
14 interrupt-parent = <&lic>;
18 pcie-controller@0,01003000 {
19 compatible = "nvidia,tegra124-pcie";
21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi";
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
43 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
44 <&tegra_car TEGRA124_CLK_AFI>,
45 <&tegra_car TEGRA124_CLK_PLL_E>,
46 <&tegra_car TEGRA124_CLK_CML0>;
47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>,
51 reset-names = "pex", "afi", "pcie_x";
54 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
67 nvidia,num-lanes = <2>;
72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
73 reg = <0x001000 0 0 0 0>;
80 nvidia,num-lanes = <1>;
85 compatible = "nvidia,tegra124-host1x", "simple-bus";
86 reg = <0x0 0x50000000 0x0 0x00034000>;
87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 resets = <&tegra_car 28>;
91 reset-names = "host1x";
96 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
99 compatible = "nvidia,tegra124-dc";
100 reg = <0x0 0x54200000 0x0 0x00040000>;
101 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
103 <&tegra_car TEGRA124_CLK_PLL_P>;
104 clock-names = "dc", "parent";
105 resets = <&tegra_car 27>;
108 iommus = <&mc TEGRA_SWGROUP_DC>;
114 compatible = "nvidia,tegra124-dc";
115 reg = <0x0 0x54240000 0x0 0x00040000>;
116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
118 <&tegra_car TEGRA124_CLK_PLL_P>;
119 clock-names = "dc", "parent";
120 resets = <&tegra_car 26>;
123 iommus = <&mc TEGRA_SWGROUP_DCB>;
129 compatible = "nvidia,tegra124-hdmi";
130 reg = <0x0 0x54280000 0x0 0x00040000>;
131 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
133 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
134 clock-names = "hdmi", "parent";
135 resets = <&tegra_car 51>;
136 reset-names = "hdmi";
141 compatible = "nvidia,tegra124-sor";
142 reg = <0x0 0x54540000 0x0 0x00040000>;
143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
146 <&tegra_car TEGRA124_CLK_PLL_DP>,
147 <&tegra_car TEGRA124_CLK_CLK_M>;
148 clock-names = "sor", "parent", "dp", "safe";
149 resets = <&tegra_car 182>;
154 dpaux: dpaux@0,545c0000 {
155 compatible = "nvidia,tegra124-dpaux";
156 reg = <0x0 0x545c0000 0x0 0x00040000>;
157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
159 <&tegra_car TEGRA124_CLK_PLL_DP>;
160 clock-names = "dpaux", "parent";
161 resets = <&tegra_car 181>;
162 reset-names = "dpaux";
167 gic: interrupt-controller@0,50041000 {
168 compatible = "arm,cortex-a15-gic";
169 #interrupt-cells = <3>;
170 interrupt-controller;
171 reg = <0x0 0x50041000 0x0 0x1000>,
172 <0x0 0x50042000 0x0 0x1000>,
173 <0x0 0x50044000 0x0 0x2000>,
174 <0x0 0x50046000 0x0 0x2000>;
175 interrupts = <GIC_PPI 9
176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 interrupt-parent = <&gic>;
181 compatible = "nvidia,gk20a";
182 reg = <0x0 0x57000000 0x0 0x01000000>,
183 <0x0 0x58000000 0x0 0x01000000>;
184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "stall", "nonstall";
187 clocks = <&tegra_car TEGRA124_CLK_GPU>,
188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
189 clock-names = "gpu", "pwr";
190 resets = <&tegra_car 184>;
193 iommus = <&mc TEGRA_SWGROUP_GPU>;
198 lic: interrupt-controller@60004000 {
199 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
200 reg = <0x0 0x60004000 0x0 0x100>,
201 <0x0 0x60004100 0x0 0x100>,
202 <0x0 0x60004200 0x0 0x100>,
203 <0x0 0x60004300 0x0 0x100>,
204 <0x0 0x60004400 0x0 0x100>;
205 interrupt-controller;
206 #interrupt-cells = <3>;
207 interrupt-parent = <&gic>;
211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
212 reg = <0x0 0x60005000 0x0 0x400>;
213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
222 tegra_car: clock@0,60006000 {
223 compatible = "nvidia,tegra124-car";
224 reg = <0x0 0x60006000 0x0 0x1000>;
227 nvidia,external-memory-controller = <&emc>;
230 flow-controller@0,60007000 {
231 compatible = "nvidia,tegra124-flowctrl";
232 reg = <0x0 0x60007000 0x0 0x1000>;
236 compatible = "nvidia,tegra124-actmon";
237 reg = <0x0 0x6000c800 0x0 0x400>;
238 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
240 <&tegra_car TEGRA124_CLK_EMC>;
241 clock-names = "actmon", "emc";
242 resets = <&tegra_car 119>;
243 reset-names = "actmon";
246 gpio: gpio@0,6000d000 {
247 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
248 reg = <0x0 0x6000d000 0x0 0x1000>;
249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 gpio-ranges = <&pinmux 0 0 251>;
264 apbdma: dma@0,60020000 {
265 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
266 reg = <0x0 0x60020000 0x0 0x1400>;
267 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
300 resets = <&tegra_car 34>;
306 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
307 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
308 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
311 pinmux: pinmux@0,70000868 {
312 compatible = "nvidia,tegra124-pinmux";
313 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
314 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
315 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
319 * There are two serial driver i.e. 8250 based simple serial
320 * driver and APB DMA based serial driver for higher baudrate
321 * and performace. To enable the 8250 based driver, the compatible
322 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
323 * the APB DMA based serial driver, the comptible is
324 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
326 uarta: serial@0,70006000 {
327 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
328 reg = <0x0 0x70006000 0x0 0x40>;
330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
332 resets = <&tegra_car 6>;
333 reset-names = "serial";
334 dmas = <&apbdma 8>, <&apbdma 8>;
335 dma-names = "rx", "tx";
339 uartb: serial@0,70006040 {
340 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
341 reg = <0x0 0x70006040 0x0 0x40>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
345 resets = <&tegra_car 7>;
346 reset-names = "serial";
347 dmas = <&apbdma 9>, <&apbdma 9>;
348 dma-names = "rx", "tx";
352 uartc: serial@0,70006200 {
353 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
354 reg = <0x0 0x70006200 0x0 0x40>;
356 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
358 resets = <&tegra_car 55>;
359 reset-names = "serial";
360 dmas = <&apbdma 10>, <&apbdma 10>;
361 dma-names = "rx", "tx";
365 uartd: serial@0,70006300 {
366 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
367 reg = <0x0 0x70006300 0x0 0x40>;
369 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
371 resets = <&tegra_car 65>;
372 reset-names = "serial";
373 dmas = <&apbdma 19>, <&apbdma 19>;
374 dma-names = "rx", "tx";
378 pwm: pwm@0,7000a000 {
379 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
380 reg = <0x0 0x7000a000 0x0 0x100>;
382 clocks = <&tegra_car TEGRA124_CLK_PWM>;
383 resets = <&tegra_car 17>;
389 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
390 reg = <0x0 0x7000c000 0x0 0x100>;
391 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
394 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
395 clock-names = "div-clk";
396 resets = <&tegra_car 12>;
398 dmas = <&apbdma 21>, <&apbdma 21>;
399 dma-names = "rx", "tx";
404 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
405 reg = <0x0 0x7000c400 0x0 0x100>;
406 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
409 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
410 clock-names = "div-clk";
411 resets = <&tegra_car 54>;
413 dmas = <&apbdma 22>, <&apbdma 22>;
414 dma-names = "rx", "tx";
419 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
420 reg = <0x0 0x7000c500 0x0 0x100>;
421 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
422 #address-cells = <1>;
424 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
425 clock-names = "div-clk";
426 resets = <&tegra_car 67>;
428 dmas = <&apbdma 23>, <&apbdma 23>;
429 dma-names = "rx", "tx";
434 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
435 reg = <0x0 0x7000c700 0x0 0x100>;
436 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <1>;
439 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
440 clock-names = "div-clk";
441 resets = <&tegra_car 103>;
443 dmas = <&apbdma 26>, <&apbdma 26>;
444 dma-names = "rx", "tx";
449 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
450 reg = <0x0 0x7000d000 0x0 0x100>;
451 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
454 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
455 clock-names = "div-clk";
456 resets = <&tegra_car 47>;
458 dmas = <&apbdma 24>, <&apbdma 24>;
459 dma-names = "rx", "tx";
464 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
465 reg = <0x0 0x7000d100 0x0 0x100>;
466 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
469 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
470 clock-names = "div-clk";
471 resets = <&tegra_car 166>;
473 dmas = <&apbdma 30>, <&apbdma 30>;
474 dma-names = "rx", "tx";
479 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
480 reg = <0x0 0x7000d400 0x0 0x200>;
481 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
484 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
486 resets = <&tegra_car 41>;
488 dmas = <&apbdma 15>, <&apbdma 15>;
489 dma-names = "rx", "tx";
494 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
495 reg = <0x0 0x7000d600 0x0 0x200>;
496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
499 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
501 resets = <&tegra_car 44>;
503 dmas = <&apbdma 16>, <&apbdma 16>;
504 dma-names = "rx", "tx";
509 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
510 reg = <0x0 0x7000d800 0x0 0x200>;
511 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
514 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
516 resets = <&tegra_car 46>;
518 dmas = <&apbdma 17>, <&apbdma 17>;
519 dma-names = "rx", "tx";
524 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
525 reg = <0x0 0x7000da00 0x0 0x200>;
526 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
529 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
531 resets = <&tegra_car 68>;
533 dmas = <&apbdma 18>, <&apbdma 18>;
534 dma-names = "rx", "tx";
539 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
540 reg = <0x0 0x7000dc00 0x0 0x200>;
541 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
542 #address-cells = <1>;
544 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
546 resets = <&tegra_car 104>;
548 dmas = <&apbdma 27>, <&apbdma 27>;
549 dma-names = "rx", "tx";
554 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
555 reg = <0x0 0x7000de00 0x0 0x200>;
556 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
559 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
561 resets = <&tegra_car 105>;
563 dmas = <&apbdma 28>, <&apbdma 28>;
564 dma-names = "rx", "tx";
569 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
570 reg = <0x0 0x7000e000 0x0 0x100>;
571 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&tegra_car TEGRA124_CLK_RTC>;
576 compatible = "nvidia,tegra124-pmc";
577 reg = <0x0 0x7000e400 0x0 0x400>;
578 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
579 clock-names = "pclk", "clk32k_in";
583 compatible = "nvidia,tegra124-efuse";
584 reg = <0x0 0x7000f800 0x0 0x400>;
585 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
586 clock-names = "fuse";
587 resets = <&tegra_car 39>;
588 reset-names = "fuse";
591 mc: memory-controller@0,70019000 {
592 compatible = "nvidia,tegra124-mc";
593 reg = <0x0 0x70019000 0x0 0x1000>;
594 clocks = <&tegra_car TEGRA124_CLK_MC>;
597 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
602 emc: emc@0,7001b000 {
603 compatible = "nvidia,tegra124-emc";
604 reg = <0x0 0x7001b000 0x0 0x1000>;
606 nvidia,memory-controller = <&mc>;
610 compatible = "nvidia,tegra124-ahci";
611 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
612 <0x0 0x70020000 0x0 0x7000>; /* SATA */
613 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&tegra_car TEGRA124_CLK_SATA>,
615 <&tegra_car TEGRA124_CLK_SATA_OOB>,
616 <&tegra_car TEGRA124_CLK_CML1>,
617 <&tegra_car TEGRA124_CLK_PLL_E>;
618 clock-names = "sata", "sata-oob", "cml1", "pll_e";
619 resets = <&tegra_car 124>,
622 reset-names = "sata", "sata-oob", "sata-cold";
623 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
624 phy-names = "sata-phy";
629 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
630 reg = <0x0 0x70030000 0x0 0x10000>;
631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA124_CLK_HDA>,
633 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
634 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
635 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
636 resets = <&tegra_car 125>, /* hda */
637 <&tegra_car 128>, /* hda2hdmi */
638 <&tegra_car 111>; /* hda2codec_2x */
639 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
643 padctl: padctl@0,7009f000 {
644 compatible = "nvidia,tegra124-xusb-padctl";
645 reg = <0x0 0x7009f000 0x0 0x1000>;
646 resets = <&tegra_car 142>;
647 reset-names = "padctl";
653 compatible = "nvidia,tegra124-sdhci";
654 reg = <0x0 0x700b0000 0x0 0x200>;
655 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
657 resets = <&tegra_car 14>;
658 reset-names = "sdhci";
663 compatible = "nvidia,tegra124-sdhci";
664 reg = <0x0 0x700b0200 0x0 0x200>;
665 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
667 resets = <&tegra_car 9>;
668 reset-names = "sdhci";
673 compatible = "nvidia,tegra124-sdhci";
674 reg = <0x0 0x700b0400 0x0 0x200>;
675 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
677 resets = <&tegra_car 69>;
678 reset-names = "sdhci";
683 compatible = "nvidia,tegra124-sdhci";
684 reg = <0x0 0x700b0600 0x0 0x200>;
685 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
687 resets = <&tegra_car 15>;
688 reset-names = "sdhci";
692 soctherm: thermal-sensor@0,700e2000 {
693 compatible = "nvidia,tegra124-soctherm";
694 reg = <0x0 0x700e2000 0x0 0x1000>;
695 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
697 <&tegra_car TEGRA124_CLK_SOC_THERM>;
698 clock-names = "tsensor", "soctherm";
699 resets = <&tegra_car 78>;
700 reset-names = "soctherm";
701 #thermal-sensor-cells = <1>;
704 dfll: clock@0,70110000 {
705 compatible = "nvidia,tegra124-dfll";
706 reg = <0 0x70110000 0 0x100>, /* DFLL control */
707 <0 0x70110000 0 0x100>, /* I2C output control */
708 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
709 <0 0x70110200 0 0x100>; /* Look-up table RAM */
710 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
712 <&tegra_car TEGRA124_CLK_DFLL_REF>,
713 <&tegra_car TEGRA124_CLK_I2C5>;
714 clock-names = "soc", "ref", "i2c";
715 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
716 reset-names = "dvco";
718 clock-output-names = "dfllCPU_out";
719 nvidia,sample-rate = <12500>;
720 nvidia,droop-ctrl = <0x00000f00>;
721 nvidia,force-mode = <1>;
729 compatible = "nvidia,tegra124-ahub";
730 reg = <0x0 0x70300000 0x0 0x200>,
731 <0x0 0x70300800 0x0 0x800>,
732 <0x0 0x70300200 0x0 0x600>;
733 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
735 <&tegra_car TEGRA124_CLK_APBIF>;
736 clock-names = "d_audio", "apbif";
737 resets = <&tegra_car 106>, /* d_audio */
738 <&tegra_car 107>, /* apbif */
739 <&tegra_car 30>, /* i2s0 */
740 <&tegra_car 11>, /* i2s1 */
741 <&tegra_car 18>, /* i2s2 */
742 <&tegra_car 101>, /* i2s3 */
743 <&tegra_car 102>, /* i2s4 */
744 <&tegra_car 108>, /* dam0 */
745 <&tegra_car 109>, /* dam1 */
746 <&tegra_car 110>, /* dam2 */
747 <&tegra_car 10>, /* spdif */
748 <&tegra_car 153>, /* amx */
749 <&tegra_car 185>, /* amx1 */
750 <&tegra_car 154>, /* adx */
751 <&tegra_car 180>, /* adx1 */
752 <&tegra_car 186>, /* afc0 */
753 <&tegra_car 187>, /* afc1 */
754 <&tegra_car 188>, /* afc2 */
755 <&tegra_car 189>, /* afc3 */
756 <&tegra_car 190>, /* afc4 */
757 <&tegra_car 191>; /* afc5 */
758 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
759 "i2s3", "i2s4", "dam0", "dam1", "dam2",
760 "spdif", "amx", "amx1", "adx", "adx1",
761 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
762 dmas = <&apbdma 1>, <&apbdma 1>,
763 <&apbdma 2>, <&apbdma 2>,
764 <&apbdma 3>, <&apbdma 3>,
765 <&apbdma 4>, <&apbdma 4>,
766 <&apbdma 6>, <&apbdma 6>,
767 <&apbdma 7>, <&apbdma 7>,
768 <&apbdma 12>, <&apbdma 12>,
769 <&apbdma 13>, <&apbdma 13>,
770 <&apbdma 14>, <&apbdma 14>,
771 <&apbdma 29>, <&apbdma 29>;
772 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
773 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
774 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
777 #address-cells = <2>;
780 tegra_i2s0: i2s@0,70301000 {
781 compatible = "nvidia,tegra124-i2s";
782 reg = <0x0 0x70301000 0x0 0x100>;
783 nvidia,ahub-cif-ids = <4 4>;
784 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
785 resets = <&tegra_car 30>;
790 tegra_i2s1: i2s@0,70301100 {
791 compatible = "nvidia,tegra124-i2s";
792 reg = <0x0 0x70301100 0x0 0x100>;
793 nvidia,ahub-cif-ids = <5 5>;
794 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
795 resets = <&tegra_car 11>;
800 tegra_i2s2: i2s@0,70301200 {
801 compatible = "nvidia,tegra124-i2s";
802 reg = <0x0 0x70301200 0x0 0x100>;
803 nvidia,ahub-cif-ids = <6 6>;
804 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
805 resets = <&tegra_car 18>;
810 tegra_i2s3: i2s@0,70301300 {
811 compatible = "nvidia,tegra124-i2s";
812 reg = <0x0 0x70301300 0x0 0x100>;
813 nvidia,ahub-cif-ids = <7 7>;
814 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
815 resets = <&tegra_car 101>;
820 tegra_i2s4: i2s@0,70301400 {
821 compatible = "nvidia,tegra124-i2s";
822 reg = <0x0 0x70301400 0x0 0x100>;
823 nvidia,ahub-cif-ids = <8 8>;
824 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
825 resets = <&tegra_car 102>;
832 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
833 reg = <0x0 0x7d000000 0x0 0x4000>;
834 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA124_CLK_USBD>;
837 resets = <&tegra_car 22>;
839 nvidia,phy = <&phy1>;
843 phy1: usb-phy@0,7d000000 {
844 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
845 reg = <0x0 0x7d000000 0x0 0x4000>,
846 <0x0 0x7d000000 0x0 0x4000>;
848 clocks = <&tegra_car TEGRA124_CLK_USBD>,
849 <&tegra_car TEGRA124_CLK_PLL_U>,
850 <&tegra_car TEGRA124_CLK_USBD>;
851 clock-names = "reg", "pll_u", "utmi-pads";
852 resets = <&tegra_car 22>, <&tegra_car 22>;
853 reset-names = "usb", "utmi-pads";
854 nvidia,hssync-start-delay = <0>;
855 nvidia,idle-wait-delay = <17>;
856 nvidia,elastic-limit = <16>;
857 nvidia,term-range-adj = <6>;
858 nvidia,xcvr-setup = <9>;
859 nvidia,xcvr-lsfslew = <0>;
860 nvidia,xcvr-lsrslew = <3>;
861 nvidia,hssquelch-level = <2>;
862 nvidia,hsdiscon-level = <5>;
863 nvidia,xcvr-hsslew = <12>;
864 nvidia,has-utmi-pad-registers;
869 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
870 reg = <0x0 0x7d004000 0x0 0x4000>;
871 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&tegra_car TEGRA124_CLK_USB2>;
874 resets = <&tegra_car 58>;
876 nvidia,phy = <&phy2>;
880 phy2: usb-phy@0,7d004000 {
881 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
882 reg = <0x0 0x7d004000 0x0 0x4000>,
883 <0x0 0x7d000000 0x0 0x4000>;
885 clocks = <&tegra_car TEGRA124_CLK_USB2>,
886 <&tegra_car TEGRA124_CLK_PLL_U>,
887 <&tegra_car TEGRA124_CLK_USBD>;
888 clock-names = "reg", "pll_u", "utmi-pads";
889 resets = <&tegra_car 58>, <&tegra_car 22>;
890 reset-names = "usb", "utmi-pads";
891 nvidia,hssync-start-delay = <0>;
892 nvidia,idle-wait-delay = <17>;
893 nvidia,elastic-limit = <16>;
894 nvidia,term-range-adj = <6>;
895 nvidia,xcvr-setup = <9>;
896 nvidia,xcvr-lsfslew = <0>;
897 nvidia,xcvr-lsrslew = <3>;
898 nvidia,hssquelch-level = <2>;
899 nvidia,hsdiscon-level = <5>;
900 nvidia,xcvr-hsslew = <12>;
905 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
906 reg = <0x0 0x7d008000 0x0 0x4000>;
907 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&tegra_car TEGRA124_CLK_USB3>;
910 resets = <&tegra_car 59>;
912 nvidia,phy = <&phy3>;
916 phy3: usb-phy@0,7d008000 {
917 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
918 reg = <0x0 0x7d008000 0x0 0x4000>,
919 <0x0 0x7d000000 0x0 0x4000>;
921 clocks = <&tegra_car TEGRA124_CLK_USB3>,
922 <&tegra_car TEGRA124_CLK_PLL_U>,
923 <&tegra_car TEGRA124_CLK_USBD>;
924 clock-names = "reg", "pll_u", "utmi-pads";
925 resets = <&tegra_car 59>, <&tegra_car 22>;
926 reset-names = "usb", "utmi-pads";
927 nvidia,hssync-start-delay = <0>;
928 nvidia,idle-wait-delay = <17>;
929 nvidia,elastic-limit = <16>;
930 nvidia,term-range-adj = <6>;
931 nvidia,xcvr-setup = <9>;
932 nvidia,xcvr-lsfslew = <0>;
933 nvidia,xcvr-lsrslew = <3>;
934 nvidia,hssquelch-level = <2>;
935 nvidia,hsdiscon-level = <5>;
936 nvidia,xcvr-hsslew = <12>;
941 #address-cells = <1>;
946 compatible = "arm,cortex-a15";
949 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
950 <&tegra_car TEGRA124_CLK_CCLK_LP>,
951 <&tegra_car TEGRA124_CLK_PLL_X>,
952 <&tegra_car TEGRA124_CLK_PLL_P>,
954 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
955 /* FIXME: what's the actual transition time? */
956 clock-latency = <300000>;
961 compatible = "arm,cortex-a15";
967 compatible = "arm,cortex-a15";
973 compatible = "arm,cortex-a15";
979 compatible = "arm,cortex-a15-pmu";
980 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-affinity = <&{/cpus/cpu@0}>,
992 polling-delay-passive = <1000>;
993 polling-delay = <1000>;
996 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1000 polling-delay-passive = <1000>;
1001 polling-delay = <1000>;
1004 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1008 polling-delay-passive = <1000>;
1009 polling-delay = <1000>;
1012 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1016 polling-delay-passive = <1000>;
1017 polling-delay = <1000>;
1020 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1025 compatible = "arm,armv7-timer";
1026 interrupts = <GIC_PPI 13
1027 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1029 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1034 interrupt-parent = <&gic>;