arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         compatible = "nvidia,tegra124";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         host1x@0,50000000 {
  16                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  17                 reg = <0x0 0x50000000 0x0 0x00034000>;
  18                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  19                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  20                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  21                 resets = <&tegra_car 28>;
  22                 reset-names = "host1x";
  23
  24                 #address-cells = <2>;
  25                 #size-cells = <2>;
  26
  27                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  28
  29                 dc@0,54200000 {
  30                         compatible = "nvidia,tegra124-dc";
  31                         reg = <0x0 0x54200000 0x0 0x00040000>;
  32                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  33                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
  34                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  35                         clock-names = "dc", "parent";
  36                         resets = <&tegra_car 27>;
  37                         reset-names = "dc";
  38
  39                         nvidia,head = <0>;
  40                 };
  41
  42                 dc@0,54240000 {
  43                         compatible = "nvidia,tegra124-dc";
  44                         reg = <0x0 0x54240000 0x0 0x00040000>;
  45                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  46                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
  47                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  48                         clock-names = "dc", "parent";
  49                         resets = <&tegra_car 26>;
  50                         reset-names = "dc";
  51
  52                         nvidia,head = <1>;
  53                 };
  54
  55                 hdmi@0,54280000 {
  56                         compatible = "nvidia,tegra124-hdmi";
  57                         reg = <0x0 0x54280000 0x0 0x00040000>;
  58                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  59                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
  60                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
  61                         clock-names = "hdmi", "parent";
  62                         resets = <&tegra_car 51>;
  63                         reset-names = "hdmi";
  64                         status = "disabled";
  65                 };
  66
  67                 sor@0,54540000 {
  68                         compatible = "nvidia,tegra124-sor";
  69                         reg = <0x0 0x54540000 0x0 0x00040000>;
  70                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
  72                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
  73                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
  74                                  <&tegra_car TEGRA124_CLK_CLK_M>;
  75                         clock-names = "sor", "parent", "dp", "safe";
  76                         resets = <&tegra_car 182>;
  77                         reset-names = "sor";
  78                         status = "disabled";
  79                 };
  80
  81                 dpaux@0,545c0000 {
  82                         compatible = "nvidia,tegra124-dpaux";
  83                         reg = <0x0 0x545c0000 0x0 0x00040000>;
  84                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  85                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
  86                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
  87                         clock-names = "dpaux", "parent";
  88                         resets = <&tegra_car 181>;
  89                         reset-names = "dpaux";
  90                         status = "disabled";
  91                 };
  92         };
  93
  94         gic: interrupt-controller@0,50041000 {
  95                 compatible = "arm,cortex-a15-gic";
  96                 #interrupt-cells = <3>;
  97                 interrupt-controller;
  98                 reg = <0x0 0x50041000 0x0 0x1000>,
  99                       <0x0 0x50042000 0x0 0x1000>,
 100                       <0x0 0x50044000 0x0 0x2000>,
 101                       <0x0 0x50046000 0x0 0x2000>;
 102                 interrupts = <GIC_PPI 9
 103                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 104         };
 105
 106         gpu@0,57000000 {
 107                 compatible = "nvidia,gk20a";
 108                 reg = <0x0 0x57000000 0x0 0x01000000>,
 109                       <0x0 0x58000000 0x0 0x01000000>;
 110                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 112                 interrupt-names = "stall", "nonstall";
 113                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 114                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 115                 clock-names = "gpu", "pwr";
 116                 resets = <&tegra_car 184>;
 117                 reset-names = "gpu";
 118                 status = "disabled";
 119         };
 120
 121         timer@0,60005000 {
 122                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 123                 reg = <0x0 0x60005000 0x0 0x400>;
 124                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 127                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 128                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 130                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 131         };
 132
 133         tegra_car: clock@0,60006000 {
 134                 compatible = "nvidia,tegra124-car";
 135                 reg = <0x0 0x60006000 0x0 0x1000>;
 136                 #clock-cells = <1>;
 137                 #reset-cells = <1>;
 138         };
 139
 140         flow-controller@0,60007000 {
 141                 compatible = "nvidia,tegra124-flowctrl";
 142                 reg = <0x0 0x60007000 0x0 0x1000>;
 143         };
 144
 145         gpio: gpio@0,6000d000 {
 146                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 147                 reg = <0x0 0x6000d000 0x0 0x1000>;
 148                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 156                 #gpio-cells = <2>;
 157                 gpio-controller;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160         };
 161
 162         apbdma: dma@0,60020000 {
 163                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 164                 reg = <0x0 0x60020000 0x0 0x1400>;
 165                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 198                 resets = <&tegra_car 34>;
 199                 reset-names = "dma";
 200                 #dma-cells = <1>;
 201         };
 202
 203         apbmisc@0,70000800 {
 204                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 205                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 206                       <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
 207         };
 208
 209         pinmux: pinmux@0,70000868 {
 210                 compatible = "nvidia,tegra124-pinmux";
 211                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 212                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 213         };
 214
 215         /*
 216          * There are two serial driver i.e. 8250 based simple serial
 217          * driver and APB DMA based serial driver for higher baudrate
 218          * and performace. To enable the 8250 based driver, the compatible
 219          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 220          * the APB DMA based serial driver, the comptible is
 221          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 222          */
 223         serial@0,70006000 {
 224                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 225                 reg = <0x0 0x70006000 0x0 0x40>;
 226                 reg-shift = <2>;
 227                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 229                 resets = <&tegra_car 6>;
 230                 reset-names = "serial";
 231                 dmas = <&apbdma 8>, <&apbdma 8>;
 232                 dma-names = "rx", "tx";
 233                 status = "disabled";
 234         };
 235
 236         serial@0,70006040 {
 237                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 238                 reg = <0x0 0x70006040 0x0 0x40>;
 239                 reg-shift = <2>;
 240                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 242                 resets = <&tegra_car 7>;
 243                 reset-names = "serial";
 244                 dmas = <&apbdma 9>, <&apbdma 9>;
 245                 dma-names = "rx", "tx";
 246                 status = "disabled";
 247         };
 248
 249         serial@0,70006200 {
 250                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 251                 reg = <0x0 0x70006200 0x0 0x40>;
 252                 reg-shift = <2>;
 253                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 255                 resets = <&tegra_car 55>;
 256                 reset-names = "serial";
 257                 dmas = <&apbdma 10>, <&apbdma 10>;
 258                 dma-names = "rx", "tx";
 259                 status = "disabled";
 260         };
 261
 262         serial@0,70006300 {
 263                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 264                 reg = <0x0 0x70006300 0x0 0x40>;
 265                 reg-shift = <2>;
 266                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 268                 resets = <&tegra_car 65>;
 269                 reset-names = "serial";
 270                 dmas = <&apbdma 19>, <&apbdma 19>;
 271                 dma-names = "rx", "tx";
 272                 status = "disabled";
 273         };
 274
 275         pwm@0,7000a000 {
 276                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 277                 reg = <0x0 0x7000a000 0x0 0x100>;
 278                 #pwm-cells = <2>;
 279                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 280                 resets = <&tegra_car 17>;
 281                 reset-names = "pwm";
 282                 status = "disabled";
 283         };
 284
 285         i2c@0,7000c000 {
 286                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 287                 reg = <0x0 0x7000c000 0x0 0x100>;
 288                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 292                 clock-names = "div-clk";
 293                 resets = <&tegra_car 12>;
 294                 reset-names = "i2c";
 295                 dmas = <&apbdma 21>, <&apbdma 21>;
 296                 dma-names = "rx", "tx";
 297                 status = "disabled";
 298         };
 299
 300         i2c@0,7000c400 {
 301                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 302                 reg = <0x0 0x7000c400 0x0 0x100>;
 303                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 307                 clock-names = "div-clk";
 308                 resets = <&tegra_car 54>;
 309                 reset-names = "i2c";
 310                 dmas = <&apbdma 22>, <&apbdma 22>;
 311                 dma-names = "rx", "tx";
 312                 status = "disabled";
 313         };
 314
 315         i2c@0,7000c500 {
 316                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 317                 reg = <0x0 0x7000c500 0x0 0x100>;
 318                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 322                 clock-names = "div-clk";
 323                 resets = <&tegra_car 67>;
 324                 reset-names = "i2c";
 325                 dmas = <&apbdma 23>, <&apbdma 23>;
 326                 dma-names = "rx", "tx";
 327                 status = "disabled";
 328         };
 329
 330         i2c@0,7000c700 {
 331                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 332                 reg = <0x0 0x7000c700 0x0 0x100>;
 333                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 337                 clock-names = "div-clk";
 338                 resets = <&tegra_car 103>;
 339                 reset-names = "i2c";
 340                 dmas = <&apbdma 26>, <&apbdma 26>;
 341                 dma-names = "rx", "tx";
 342                 status = "disabled";
 343         };
 344
 345         i2c@0,7000d000 {
 346                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 347                 reg = <0x0 0x7000d000 0x0 0x100>;
 348                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 352                 clock-names = "div-clk";
 353                 resets = <&tegra_car 47>;
 354                 reset-names = "i2c";
 355                 dmas = <&apbdma 24>, <&apbdma 24>;
 356                 dma-names = "rx", "tx";
 357                 status = "disabled";
 358         };
 359
 360         i2c@0,7000d100 {
 361                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 362                 reg = <0x0 0x7000d100 0x0 0x100>;
 363                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 367                 clock-names = "div-clk";
 368                 resets = <&tegra_car 166>;
 369                 reset-names = "i2c";
 370                 dmas = <&apbdma 30>, <&apbdma 30>;
 371                 dma-names = "rx", "tx";
 372                 status = "disabled";
 373         };
 374
 375         spi@0,7000d400 {
 376                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 377                 reg = <0x0 0x7000d400 0x0 0x200>;
 378                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 382                 clock-names = "spi";
 383                 resets = <&tegra_car 41>;
 384                 reset-names = "spi";
 385                 dmas = <&apbdma 15>, <&apbdma 15>;
 386                 dma-names = "rx", "tx";
 387                 status = "disabled";
 388         };
 389
 390         spi@0,7000d600 {
 391                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 392                 reg = <0x0 0x7000d600 0x0 0x200>;
 393                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 397                 clock-names = "spi";
 398                 resets = <&tegra_car 44>;
 399                 reset-names = "spi";
 400                 dmas = <&apbdma 16>, <&apbdma 16>;
 401                 dma-names = "rx", "tx";
 402                 status = "disabled";
 403         };
 404
 405         spi@0,7000d800 {
 406                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 407                 reg = <0x0 0x7000d800 0x0 0x200>;
 408                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 412                 clock-names = "spi";
 413                 resets = <&tegra_car 46>;
 414                 reset-names = "spi";
 415                 dmas = <&apbdma 17>, <&apbdma 17>;
 416                 dma-names = "rx", "tx";
 417                 status = "disabled";
 418         };
 419
 420         spi@0,7000da00 {
 421                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 422                 reg = <0x0 0x7000da00 0x0 0x200>;
 423                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 427                 clock-names = "spi";
 428                 resets = <&tegra_car 68>;
 429                 reset-names = "spi";
 430                 dmas = <&apbdma 18>, <&apbdma 18>;
 431                 dma-names = "rx", "tx";
 432                 status = "disabled";
 433         };
 434
 435         spi@0,7000dc00 {
 436                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 437                 reg = <0x0 0x7000dc00 0x0 0x200>;
 438                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 442                 clock-names = "spi";
 443                 resets = <&tegra_car 104>;
 444                 reset-names = "spi";
 445                 dmas = <&apbdma 27>, <&apbdma 27>;
 446                 dma-names = "rx", "tx";
 447                 status = "disabled";
 448         };
 449
 450         spi@0,7000de00 {
 451                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 452                 reg = <0x0 0x7000de00 0x0 0x200>;
 453                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 457                 clock-names = "spi";
 458                 resets = <&tegra_car 105>;
 459                 reset-names = "spi";
 460                 dmas = <&apbdma 28>, <&apbdma 28>;
 461                 dma-names = "rx", "tx";
 462                 status = "disabled";
 463         };
 464
 465         rtc@0,7000e000 {
 466                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 467                 reg = <0x0 0x7000e000 0x0 0x100>;
 468                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 470         };
 471
 472         pmc@0,7000e400 {
 473                 compatible = "nvidia,tegra124-pmc";
 474                 reg = <0x0 0x7000e400 0x0 0x400>;
 475                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 476                 clock-names = "pclk", "clk32k_in";
 477         };
 478
 479         fuse@0,7000f800 {
 480                 compatible = "nvidia,tegra124-efuse";
 481                 reg = <0x0 0x7000f800 0x0 0x400>;
 482                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 483                 clock-names = "fuse";
 484                 resets = <&tegra_car 39>;
 485                 reset-names = "fuse";
 486         };
 487
 488         sata@0,70020000 {
 489                 compatible = "nvidia,tegra124-ahci";
 490
 491                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 492                         <0x0 0x70020000 0x0 0x7000>; /* SATA */
 493
 494                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 495
 496                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 497                         <&tegra_car TEGRA124_CLK_SATA_OOB>,
 498                         <&tegra_car TEGRA124_CLK_CML1>,
 499                         <&tegra_car TEGRA124_CLK_PLL_E>;
 500                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 501
 502                 resets = <&tegra_car 124>,
 503                         <&tegra_car 123>,
 504                         <&tegra_car 129>;
 505                 reset-names = "sata", "sata-oob", "sata-cold";
 506
 507                 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
 508                 phy-names = "sata-phy";
 509
 510                 status = "disabled";
 511         };
 512
 513         hda@0,70030000 {
 514                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 515                 reg = <0x0 0x70030000 0x0 0x10000>;
 516                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 518                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 519                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 520                 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
 521                 resets = <&tegra_car 125>, /* hda */
 522                          <&tegra_car 128>, /* hda2hdmi */
 523                          <&tegra_car 111>; /* hda2codec_2x */
 524                 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
 525                 status = "disabled";
 526         };
 527
 528         padctl: padctl@0,7009f000 {
 529                 compatible = "nvidia,tegra124-xusb-padctl";
 530                 reg = <0x0 0x7009f000 0x0 0x1000>;
 531                 resets = <&tegra_car 142>;
 532                 reset-names = "padctl";
 533
 534                 #phy-cells = <1>;
 535         };
 536
 537         sdhci@0,700b0000 {
 538                 compatible = "nvidia,tegra124-sdhci";
 539                 reg = <0x0 0x700b0000 0x0 0x200>;
 540                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 542                 resets = <&tegra_car 14>;
 543                 reset-names = "sdhci";
 544                 status = "disabled";
 545         };
 546
 547         sdhci@0,700b0200 {
 548                 compatible = "nvidia,tegra124-sdhci";
 549                 reg = <0x0 0x700b0200 0x0 0x200>;
 550                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 552                 resets = <&tegra_car 9>;
 553                 reset-names = "sdhci";
 554                 status = "disabled";
 555         };
 556
 557         sdhci@0,700b0400 {
 558                 compatible = "nvidia,tegra124-sdhci";
 559                 reg = <0x0 0x700b0400 0x0 0x200>;
 560                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 562                 resets = <&tegra_car 69>;
 563                 reset-names = "sdhci";
 564                 status = "disabled";
 565         };
 566
 567         sdhci@0,700b0600 {
 568                 compatible = "nvidia,tegra124-sdhci";
 569                 reg = <0x0 0x700b0600 0x0 0x200>;
 570                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 572                 resets = <&tegra_car 15>;
 573                 reset-names = "sdhci";
 574                 status = "disabled";
 575         };
 576
 577         ahub@0,70300000 {
 578                 compatible = "nvidia,tegra124-ahub";
 579                 reg = <0x0 0x70300000 0x0 0x200>,
 580                       <0x0 0x70300800 0x0 0x800>,
 581                       <0x0 0x70300200 0x0 0x600>;
 582                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 584                          <&tegra_car TEGRA124_CLK_APBIF>;
 585                 clock-names = "d_audio", "apbif";
 586                 resets = <&tegra_car 106>, /* d_audio */
 587                          <&tegra_car 107>, /* apbif */
 588                          <&tegra_car 30>,  /* i2s0 */
 589                          <&tegra_car 11>,  /* i2s1 */
 590                          <&tegra_car 18>,  /* i2s2 */
 591                          <&tegra_car 101>, /* i2s3 */
 592                          <&tegra_car 102>, /* i2s4 */
 593                          <&tegra_car 108>, /* dam0 */
 594                          <&tegra_car 109>, /* dam1 */
 595                          <&tegra_car 110>, /* dam2 */
 596                          <&tegra_car 10>,  /* spdif */
 597                          <&tegra_car 153>, /* amx */
 598                          <&tegra_car 185>, /* amx1 */
 599                          <&tegra_car 154>, /* adx */
 600                          <&tegra_car 180>, /* adx1 */
 601                          <&tegra_car 186>, /* afc0 */
 602                          <&tegra_car 187>, /* afc1 */
 603                          <&tegra_car 188>, /* afc2 */
 604                          <&tegra_car 189>, /* afc3 */
 605                          <&tegra_car 190>, /* afc4 */
 606                          <&tegra_car 191>; /* afc5 */
 607                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 608                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 609                               "spdif", "amx", "amx1", "adx", "adx1",
 610                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 611                 dmas = <&apbdma 1>, <&apbdma 1>,
 612                        <&apbdma 2>, <&apbdma 2>,
 613                        <&apbdma 3>, <&apbdma 3>,
 614                        <&apbdma 4>, <&apbdma 4>,
 615                        <&apbdma 6>, <&apbdma 6>,
 616                        <&apbdma 7>, <&apbdma 7>,
 617                        <&apbdma 12>, <&apbdma 12>,
 618                        <&apbdma 13>, <&apbdma 13>,
 619                        <&apbdma 14>, <&apbdma 14>,
 620                        <&apbdma 29>, <&apbdma 29>;
 621                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 622                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 623                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 624                             "rx9", "tx9";
 625                 ranges;
 626                 #address-cells = <2>;
 627                 #size-cells = <2>;
 628
 629                 tegra_i2s0: i2s@0,70301000 {
 630                         compatible = "nvidia,tegra124-i2s";
 631                         reg = <0x0 0x70301000 0x0 0x100>;
 632                         nvidia,ahub-cif-ids = <4 4>;
 633                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 634                         resets = <&tegra_car 30>;
 635                         reset-names = "i2s";
 636                         status = "disabled";
 637                 };
 638
 639                 tegra_i2s1: i2s@0,70301100 {
 640                         compatible = "nvidia,tegra124-i2s";
 641                         reg = <0x0 0x70301100 0x0 0x100>;
 642                         nvidia,ahub-cif-ids = <5 5>;
 643                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 644                         resets = <&tegra_car 11>;
 645                         reset-names = "i2s";
 646                         status = "disabled";
 647                 };
 648
 649                 tegra_i2s2: i2s@0,70301200 {
 650                         compatible = "nvidia,tegra124-i2s";
 651                         reg = <0x0 0x70301200 0x0 0x100>;
 652                         nvidia,ahub-cif-ids = <6 6>;
 653                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 654                         resets = <&tegra_car 18>;
 655                         reset-names = "i2s";
 656                         status = "disabled";
 657                 };
 658
 659                 tegra_i2s3: i2s@0,70301300 {
 660                         compatible = "nvidia,tegra124-i2s";
 661                         reg = <0x0 0x70301300 0x0 0x100>;
 662                         nvidia,ahub-cif-ids = <7 7>;
 663                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 664                         resets = <&tegra_car 101>;
 665                         reset-names = "i2s";
 666                         status = "disabled";
 667                 };
 668
 669                 tegra_i2s4: i2s@0,70301400 {
 670                         compatible = "nvidia,tegra124-i2s";
 671                         reg = <0x0 0x70301400 0x0 0x100>;
 672                         nvidia,ahub-cif-ids = <8 8>;
 673                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 674                         resets = <&tegra_car 102>;
 675                         reset-names = "i2s";
 676                         status = "disabled";
 677                 };
 678         };
 679
 680         usb@0,7d000000 {
 681                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 682                 reg = <0x0 0x7d000000 0x0 0x4000>;
 683                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 684                 phy_type = "utmi";
 685                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 686                 resets = <&tegra_car 22>;
 687                 reset-names = "usb";
 688                 nvidia,phy = <&phy1>;
 689                 status = "disabled";
 690         };
 691
 692         phy1: usb-phy@0,7d000000 {
 693                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 694                 reg = <0x0 0x7d000000 0x0 0x4000>,
 695                       <0x0 0x7d000000 0x0 0x4000>;
 696                 phy_type = "utmi";
 697                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 698                          <&tegra_car TEGRA124_CLK_PLL_U>,
 699                          <&tegra_car TEGRA124_CLK_USBD>;
 700                 clock-names = "reg", "pll_u", "utmi-pads";
 701                 resets = <&tegra_car 59>, <&tegra_car 22>;
 702                 reset-names = "usb", "utmi-pads";
 703                 nvidia,hssync-start-delay = <0>;
 704                 nvidia,idle-wait-delay = <17>;
 705                 nvidia,elastic-limit = <16>;
 706                 nvidia,term-range-adj = <6>;
 707                 nvidia,xcvr-setup = <9>;
 708                 nvidia,xcvr-lsfslew = <0>;
 709                 nvidia,xcvr-lsrslew = <3>;
 710                 nvidia,hssquelch-level = <2>;
 711                 nvidia,hsdiscon-level = <5>;
 712                 nvidia,xcvr-hsslew = <12>;
 713                 status = "disabled";
 714         };
 715
 716         usb@0,7d004000 {
 717                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 718                 reg = <0x0 0x7d004000 0x0 0x4000>;
 719                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 720                 phy_type = "utmi";
 721                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 722                 resets = <&tegra_car 58>;
 723                 reset-names = "usb";
 724                 nvidia,phy = <&phy2>;
 725                 status = "disabled";
 726         };
 727
 728         phy2: usb-phy@0,7d004000 {
 729                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 730                 reg = <0x0 0x7d004000 0x0 0x4000>,
 731                       <0x0 0x7d000000 0x0 0x4000>;
 732                 phy_type = "utmi";
 733                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 734                          <&tegra_car TEGRA124_CLK_PLL_U>,
 735                          <&tegra_car TEGRA124_CLK_USBD>;
 736                 clock-names = "reg", "pll_u", "utmi-pads";
 737                 resets = <&tegra_car 22>, <&tegra_car 22>;
 738                 reset-names = "usb", "utmi-pads";
 739                 nvidia,hssync-start-delay = <0>;
 740                 nvidia,idle-wait-delay = <17>;
 741                 nvidia,elastic-limit = <16>;
 742                 nvidia,term-range-adj = <6>;
 743                 nvidia,xcvr-setup = <9>;
 744                 nvidia,xcvr-lsfslew = <0>;
 745                 nvidia,xcvr-lsrslew = <3>;
 746                 nvidia,hssquelch-level = <2>;
 747                 nvidia,hsdiscon-level = <5>;
 748                 nvidia,xcvr-hsslew = <12>;
 749                 nvidia,has-utmi-pad-registers;
 750                 status = "disabled";
 751         };
 752
 753         usb@0,7d008000 {
 754                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 755                 reg = <0x0 0x7d008000 0x0 0x4000>;
 756                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 757                 phy_type = "utmi";
 758                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 759                 resets = <&tegra_car 59>;
 760                 reset-names = "usb";
 761                 nvidia,phy = <&phy3>;
 762                 status = "disabled";
 763         };
 764
 765         phy3: usb-phy@0,7d008000 {
 766                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 767                 reg = <0x0 0x7d008000 0x0 0x4000>,
 768                       <0x0 0x7d000000 0x0 0x4000>;
 769                 phy_type = "utmi";
 770                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 771                          <&tegra_car TEGRA124_CLK_PLL_U>,
 772                          <&tegra_car TEGRA124_CLK_USBD>;
 773                 clock-names = "reg", "pll_u", "utmi-pads";
 774                 resets = <&tegra_car 58>, <&tegra_car 22>;
 775                 reset-names = "usb", "utmi-pads";
 776                 nvidia,hssync-start-delay = <0>;
 777                 nvidia,idle-wait-delay = <17>;
 778                 nvidia,elastic-limit = <16>;
 779                 nvidia,term-range-adj = <6>;
 780                 nvidia,xcvr-setup = <9>;
 781                 nvidia,xcvr-lsfslew = <0>;
 782                 nvidia,xcvr-lsrslew = <3>;
 783                 nvidia,hssquelch-level = <2>;
 784                 nvidia,hsdiscon-level = <5>;
 785                 nvidia,xcvr-hsslew = <12>;
 786                 status = "disabled";
 787         };
 788
 789         cpus {
 790                 #address-cells = <1>;
 791                 #size-cells = <0>;
 792
 793                 cpu@0 {
 794                         device_type = "cpu";
 795                         compatible = "arm,cortex-a15";
 796                         reg = <0>;
 797                 };
 798
 799                 cpu@1 {
 800                         device_type = "cpu";
 801                         compatible = "arm,cortex-a15";
 802                         reg = <1>;
 803                 };
 804
 805                 cpu@2 {
 806                         device_type = "cpu";
 807                         compatible = "arm,cortex-a15";
 808                         reg = <2>;
 809                 };
 810
 811                 cpu@3 {
 812                         device_type = "cpu";
 813                         compatible = "arm,cortex-a15";
 814                         reg = <3>;
 815                 };
 816         };
 817
 818         timer {
 819                 compatible = "arm,armv7-timer";
 820                 interrupts = <GIC_PPI 13
 821                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 822                              <GIC_PPI 14
 823                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 824                              <GIC_PPI 11
 825                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 826                              <GIC_PPI 10
 827                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 828         };
 829 };