1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra124";
10 interrupt-parent = <&gic>;
15 compatible = "nvidia,tegra124-host1x", "simple-bus";
16 reg = <0x0 0x50000000 0x0 0x00034000>;
17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
19 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
26 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
29 compatible = "nvidia,tegra124-dc";
30 reg = <0x0 0x54200000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
33 <&tegra_car TEGRA124_CLK_PLL_P>;
34 clock-names = "dc", "parent";
35 resets = <&tegra_car 27>;
42 compatible = "nvidia,tegra124-dc";
43 reg = <0x0 0x54240000 0x0 0x00040000>;
44 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
46 <&tegra_car TEGRA124_CLK_PLL_P>;
47 clock-names = "dc", "parent";
48 resets = <&tegra_car 26>;
55 compatible = "nvidia,tegra124-sor";
56 reg = <0x0 0x54540000 0x0 0x00040000>;
57 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
59 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
60 <&tegra_car TEGRA124_CLK_PLL_DP>,
61 <&tegra_car TEGRA124_CLK_CLK_M>;
62 clock-names = "sor", "parent", "dp", "safe";
63 resets = <&tegra_car 182>;
69 compatible = "nvidia,tegra124-dpaux";
70 reg = <0x0 0x545c0000 0x0 0x00040000>;
71 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
73 <&tegra_car TEGRA124_CLK_PLL_DP>;
74 clock-names = "dpaux", "parent";
75 resets = <&tegra_car 181>;
76 reset-names = "dpaux";
81 gic: interrupt-controller@0,50041000 {
82 compatible = "arm,cortex-a15-gic";
83 #interrupt-cells = <3>;
85 reg = <0x0 0x50041000 0x0 0x1000>,
86 <0x0 0x50042000 0x0 0x1000>,
87 <0x0 0x50044000 0x0 0x2000>,
88 <0x0 0x50046000 0x0 0x2000>;
89 interrupts = <GIC_PPI 9
90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
94 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
95 reg = <0x0 0x60005000 0x0 0x400>;
96 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
105 tegra_car: clock@0,60006000 {
106 compatible = "nvidia,tegra124-car";
107 reg = <0x0 0x60006000 0x0 0x1000>;
112 gpio: gpio@0,6000d000 {
113 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
114 reg = <0x0 0x6000d000 0x0 0x1000>;
115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
125 #interrupt-cells = <2>;
126 interrupt-controller;
129 apbdma: dma@0,60020000 {
130 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
131 reg = <0x0 0x60020000 0x0 0x1400>;
132 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
165 resets = <&tegra_car 34>;
170 pinmux: pinmux@0,70000868 {
171 compatible = "nvidia,tegra124-pinmux";
172 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
173 <0x0 0x70003000 0x0 0x434>; /* Mux registers */
177 * There are two serial driver i.e. 8250 based simple serial
178 * driver and APB DMA based serial driver for higher baudrate
179 * and performace. To enable the 8250 based driver, the compatible
180 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
181 * the APB DMA based serial driver, the comptible is
182 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
185 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
186 reg = <0x0 0x70006000 0x0 0x40>;
188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
190 resets = <&tegra_car 6>;
191 reset-names = "serial";
192 dmas = <&apbdma 8>, <&apbdma 8>;
193 dma-names = "rx", "tx";
198 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
199 reg = <0x0 0x70006040 0x0 0x40>;
201 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
203 resets = <&tegra_car 7>;
204 reset-names = "serial";
205 dmas = <&apbdma 9>, <&apbdma 9>;
206 dma-names = "rx", "tx";
211 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
212 reg = <0x0 0x70006200 0x0 0x40>;
214 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
216 resets = <&tegra_car 55>;
217 reset-names = "serial";
218 dmas = <&apbdma 10>, <&apbdma 10>;
219 dma-names = "rx", "tx";
224 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
225 reg = <0x0 0x70006300 0x0 0x40>;
227 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
229 resets = <&tegra_car 65>;
230 reset-names = "serial";
231 dmas = <&apbdma 19>, <&apbdma 19>;
232 dma-names = "rx", "tx";
237 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
238 reg = <0x0 0x7000a000 0x0 0x100>;
240 clocks = <&tegra_car TEGRA124_CLK_PWM>;
241 resets = <&tegra_car 17>;
247 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
248 reg = <0x0 0x7000c000 0x0 0x100>;
249 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
250 #address-cells = <1>;
252 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
253 clock-names = "div-clk";
254 resets = <&tegra_car 12>;
256 dmas = <&apbdma 21>, <&apbdma 21>;
257 dma-names = "rx", "tx";
262 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
263 reg = <0x0 0x7000c400 0x0 0x100>;
264 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
267 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
268 clock-names = "div-clk";
269 resets = <&tegra_car 54>;
271 dmas = <&apbdma 22>, <&apbdma 22>;
272 dma-names = "rx", "tx";
277 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
278 reg = <0x0 0x7000c500 0x0 0x100>;
279 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
280 #address-cells = <1>;
282 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
283 clock-names = "div-clk";
284 resets = <&tegra_car 67>;
286 dmas = <&apbdma 23>, <&apbdma 23>;
287 dma-names = "rx", "tx";
292 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
293 reg = <0x0 0x7000c700 0x0 0x100>;
294 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
297 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
298 clock-names = "div-clk";
299 resets = <&tegra_car 103>;
301 dmas = <&apbdma 26>, <&apbdma 26>;
302 dma-names = "rx", "tx";
307 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
308 reg = <0x0 0x7000d000 0x0 0x100>;
309 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
310 #address-cells = <1>;
312 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
313 clock-names = "div-clk";
314 resets = <&tegra_car 47>;
316 dmas = <&apbdma 24>, <&apbdma 24>;
317 dma-names = "rx", "tx";
322 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
323 reg = <0x0 0x7000d100 0x0 0x100>;
324 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
327 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
328 clock-names = "div-clk";
329 resets = <&tegra_car 166>;
331 dmas = <&apbdma 30>, <&apbdma 30>;
332 dma-names = "rx", "tx";
337 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
338 reg = <0x0 0x7000d400 0x0 0x200>;
339 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
344 resets = <&tegra_car 41>;
346 dmas = <&apbdma 15>, <&apbdma 15>;
347 dma-names = "rx", "tx";
352 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
353 reg = <0x0 0x7000d600 0x0 0x200>;
354 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
357 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
359 resets = <&tegra_car 44>;
361 dmas = <&apbdma 16>, <&apbdma 16>;
362 dma-names = "rx", "tx";
367 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
368 reg = <0x0 0x7000d800 0x0 0x200>;
369 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
372 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
374 resets = <&tegra_car 46>;
376 dmas = <&apbdma 17>, <&apbdma 17>;
377 dma-names = "rx", "tx";
382 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
383 reg = <0x0 0x7000da00 0x0 0x200>;
384 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
385 #address-cells = <1>;
387 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
389 resets = <&tegra_car 68>;
391 dmas = <&apbdma 18>, <&apbdma 18>;
392 dma-names = "rx", "tx";
397 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
398 reg = <0x0 0x7000dc00 0x0 0x200>;
399 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
400 #address-cells = <1>;
402 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
404 resets = <&tegra_car 104>;
406 dmas = <&apbdma 27>, <&apbdma 27>;
407 dma-names = "rx", "tx";
412 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
413 reg = <0x0 0x7000de00 0x0 0x200>;
414 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
417 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
419 resets = <&tegra_car 105>;
421 dmas = <&apbdma 28>, <&apbdma 28>;
422 dma-names = "rx", "tx";
427 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
428 reg = <0x0 0x7000e000 0x0 0x100>;
429 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_RTC>;
434 compatible = "nvidia,tegra124-pmc";
435 reg = <0x0 0x7000e400 0x0 0x400>;
436 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
437 clock-names = "pclk", "clk32k_in";
441 compatible = "nvidia,tegra124-sdhci";
442 reg = <0x0 0x700b0000 0x0 0x200>;
443 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
445 resets = <&tegra_car 14>;
446 reset-names = "sdhci";
451 compatible = "nvidia,tegra124-sdhci";
452 reg = <0x0 0x700b0200 0x0 0x200>;
453 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
455 resets = <&tegra_car 9>;
456 reset-names = "sdhci";
461 compatible = "nvidia,tegra124-sdhci";
462 reg = <0x0 0x700b0400 0x0 0x200>;
463 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
465 resets = <&tegra_car 69>;
466 reset-names = "sdhci";
471 compatible = "nvidia,tegra124-sdhci";
472 reg = <0x0 0x700b0600 0x0 0x200>;
473 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
475 resets = <&tegra_car 15>;
476 reset-names = "sdhci";
481 compatible = "nvidia,tegra124-ahub";
482 reg = <0x0 0x70300000 0x0 0x200>,
483 <0x0 0x70300800 0x0 0x800>,
484 <0x0 0x70300200 0x0 0x600>;
485 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
487 <&tegra_car TEGRA124_CLK_APBIF>;
488 clock-names = "d_audio", "apbif";
489 resets = <&tegra_car 106>, /* d_audio */
490 <&tegra_car 107>, /* apbif */
491 <&tegra_car 30>, /* i2s0 */
492 <&tegra_car 11>, /* i2s1 */
493 <&tegra_car 18>, /* i2s2 */
494 <&tegra_car 101>, /* i2s3 */
495 <&tegra_car 102>, /* i2s4 */
496 <&tegra_car 108>, /* dam0 */
497 <&tegra_car 109>, /* dam1 */
498 <&tegra_car 110>, /* dam2 */
499 <&tegra_car 10>, /* spdif */
500 <&tegra_car 153>, /* amx */
501 <&tegra_car 185>, /* amx1 */
502 <&tegra_car 154>, /* adx */
503 <&tegra_car 180>, /* adx1 */
504 <&tegra_car 186>, /* afc0 */
505 <&tegra_car 187>, /* afc1 */
506 <&tegra_car 188>, /* afc2 */
507 <&tegra_car 189>, /* afc3 */
508 <&tegra_car 190>, /* afc4 */
509 <&tegra_car 191>; /* afc5 */
510 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
511 "i2s3", "i2s4", "dam0", "dam1", "dam2",
512 "spdif", "amx", "amx1", "adx", "adx1",
513 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
514 dmas = <&apbdma 1>, <&apbdma 1>,
515 <&apbdma 2>, <&apbdma 2>,
516 <&apbdma 3>, <&apbdma 3>,
517 <&apbdma 4>, <&apbdma 4>,
518 <&apbdma 6>, <&apbdma 6>,
519 <&apbdma 7>, <&apbdma 7>,
520 <&apbdma 12>, <&apbdma 12>,
521 <&apbdma 13>, <&apbdma 13>,
522 <&apbdma 14>, <&apbdma 14>,
523 <&apbdma 29>, <&apbdma 29>;
524 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
525 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
526 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
529 #address-cells = <2>;
532 tegra_i2s0: i2s@0,70301000 {
533 compatible = "nvidia,tegra124-i2s";
534 reg = <0x0 0x70301000 0x0 0x100>;
535 nvidia,ahub-cif-ids = <4 4>;
536 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
537 resets = <&tegra_car 30>;
542 tegra_i2s1: i2s@0,70301100 {
543 compatible = "nvidia,tegra124-i2s";
544 reg = <0x0 0x70301100 0x0 0x100>;
545 nvidia,ahub-cif-ids = <5 5>;
546 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
547 resets = <&tegra_car 11>;
552 tegra_i2s2: i2s@0,70301200 {
553 compatible = "nvidia,tegra124-i2s";
554 reg = <0x0 0x70301200 0x0 0x100>;
555 nvidia,ahub-cif-ids = <6 6>;
556 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
557 resets = <&tegra_car 18>;
562 tegra_i2s3: i2s@0,70301300 {
563 compatible = "nvidia,tegra124-i2s";
564 reg = <0x0 0x70301300 0x0 0x100>;
565 nvidia,ahub-cif-ids = <7 7>;
566 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
567 resets = <&tegra_car 101>;
572 tegra_i2s4: i2s@0,70301400 {
573 compatible = "nvidia,tegra124-i2s";
574 reg = <0x0 0x70301400 0x0 0x100>;
575 nvidia,ahub-cif-ids = <8 8>;
576 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
577 resets = <&tegra_car 102>;
584 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
585 reg = <0x0 0x7d000000 0x0 0x4000>;
586 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&tegra_car TEGRA124_CLK_USBD>;
589 resets = <&tegra_car 22>;
591 nvidia,phy = <&phy1>;
595 phy1: usb-phy@0,7d000000 {
596 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
597 reg = <0x0 0x7d000000 0x0 0x4000>,
598 <0x0 0x7d000000 0x0 0x4000>;
600 clocks = <&tegra_car TEGRA124_CLK_USBD>,
601 <&tegra_car TEGRA124_CLK_PLL_U>,
602 <&tegra_car TEGRA124_CLK_USBD>;
603 clock-names = "reg", "pll_u", "utmi-pads";
604 nvidia,hssync-start-delay = <0>;
605 nvidia,idle-wait-delay = <17>;
606 nvidia,elastic-limit = <16>;
607 nvidia,term-range-adj = <6>;
608 nvidia,xcvr-setup = <9>;
609 nvidia,xcvr-lsfslew = <0>;
610 nvidia,xcvr-lsrslew = <3>;
611 nvidia,hssquelch-level = <2>;
612 nvidia,hsdiscon-level = <5>;
613 nvidia,xcvr-hsslew = <12>;
618 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
619 reg = <0x0 0x7d004000 0x0 0x4000>;
620 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&tegra_car TEGRA124_CLK_USB2>;
623 resets = <&tegra_car 58>;
625 nvidia,phy = <&phy2>;
629 phy2: usb-phy@0,7d004000 {
630 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
631 reg = <0x0 0x7d004000 0x0 0x4000>,
632 <0x0 0x7d000000 0x0 0x4000>;
634 clocks = <&tegra_car TEGRA124_CLK_USB2>,
635 <&tegra_car TEGRA124_CLK_PLL_U>,
636 <&tegra_car TEGRA124_CLK_USBD>;
637 clock-names = "reg", "pll_u", "utmi-pads";
638 nvidia,hssync-start-delay = <0>;
639 nvidia,idle-wait-delay = <17>;
640 nvidia,elastic-limit = <16>;
641 nvidia,term-range-adj = <6>;
642 nvidia,xcvr-setup = <9>;
643 nvidia,xcvr-lsfslew = <0>;
644 nvidia,xcvr-lsrslew = <3>;
645 nvidia,hssquelch-level = <2>;
646 nvidia,hsdiscon-level = <5>;
647 nvidia,xcvr-hsslew = <12>;
652 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
653 reg = <0x0 0x7d008000 0x0 0x4000>;
654 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA124_CLK_USB3>;
657 resets = <&tegra_car 59>;
659 nvidia,phy = <&phy3>;
663 phy3: usb-phy@0,7d008000 {
664 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
665 reg = <0x0 0x7d008000 0x0 0x4000>,
666 <0x0 0x7d000000 0x0 0x4000>;
668 clocks = <&tegra_car TEGRA124_CLK_USB3>,
669 <&tegra_car TEGRA124_CLK_PLL_U>,
670 <&tegra_car TEGRA124_CLK_USBD>;
671 clock-names = "reg", "pll_u", "utmi-pads";
672 nvidia,hssync-start-delay = <0>;
673 nvidia,idle-wait-delay = <17>;
674 nvidia,elastic-limit = <16>;
675 nvidia,term-range-adj = <6>;
676 nvidia,xcvr-setup = <9>;
677 nvidia,xcvr-lsfslew = <0>;
678 nvidia,xcvr-lsrslew = <3>;
679 nvidia,hssquelch-level = <2>;
680 nvidia,hsdiscon-level = <5>;
681 nvidia,xcvr-hsslew = <12>;
686 #address-cells = <1>;
691 compatible = "arm,cortex-a15";
697 compatible = "arm,cortex-a15";
703 compatible = "arm,cortex-a15";
709 compatible = "arm,cortex-a15";
715 compatible = "arm,armv7-timer";
716 interrupts = <GIC_PPI 13
717 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
719 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
721 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
723 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;