2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
72 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
85 reg = <0x40000000 0x80000000>;
89 compatible = "arm,armv7-timer";
90 interrupts = <1 13 0xf08>,
97 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
98 interrupts = <0 120 4>,
103 #address-cells = <1>;
107 osc24M: clk@01c20050 {
109 compatible = "allwinner,sun4i-a10-osc-clk";
110 reg = <0x01c20050 0x4>;
111 clock-frequency = <24000000>;
112 clock-output-names = "osc24M";
117 compatible = "fixed-clock";
118 clock-frequency = <32768>;
119 clock-output-names = "osc32k";
124 compatible = "allwinner,sun4i-a10-pll1-clk";
125 reg = <0x01c20000 0x4>;
127 clock-output-names = "pll1";
132 compatible = "allwinner,sun7i-a20-pll4-clk";
133 reg = <0x01c20018 0x4>;
135 clock-output-names = "pll4";
140 compatible = "allwinner,sun4i-a10-pll5-clk";
141 reg = <0x01c20020 0x4>;
143 clock-output-names = "pll5_ddr", "pll5_other";
148 compatible = "allwinner,sun4i-a10-pll6-clk";
149 reg = <0x01c20028 0x4>;
151 clock-output-names = "pll6_sata", "pll6_other", "pll6";
156 compatible = "allwinner,sun7i-a20-pll4-clk";
157 reg = <0x01c20040 0x4>;
159 clock-output-names = "pll8";
164 compatible = "allwinner,sun4i-a10-cpu-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
167 clock-output-names = "cpu";
172 compatible = "allwinner,sun4i-a10-axi-clk";
173 reg = <0x01c20054 0x4>;
175 clock-output-names = "axi";
180 compatible = "allwinner,sun4i-a10-ahb-clk";
181 reg = <0x01c20054 0x4>;
183 clock-output-names = "ahb";
186 ahb_gates: clk@01c20060 {
188 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
189 reg = <0x01c20060 0x8>;
191 clock-output-names = "ahb_usb0", "ahb_ehci0",
192 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
193 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
194 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
195 "ahb_nand", "ahb_sdram", "ahb_ace",
196 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
197 "ahb_spi2", "ahb_spi3", "ahb_sata",
198 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
199 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
200 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
201 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
202 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
206 apb0: apb0@01c20054 {
208 compatible = "allwinner,sun4i-a10-apb0-clk";
209 reg = <0x01c20054 0x4>;
211 clock-output-names = "apb0";
214 apb0_gates: clk@01c20068 {
216 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
217 reg = <0x01c20068 0x4>;
219 clock-output-names = "apb0_codec", "apb0_spdif",
220 "apb0_ac97", "apb0_iis0", "apb0_iis1",
221 "apb0_pio", "apb0_ir0", "apb0_ir1",
222 "apb0_iis2", "apb0_keypad";
227 compatible = "allwinner,sun4i-a10-apb1-clk";
228 reg = <0x01c20058 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
230 clock-output-names = "apb1";
233 apb1_gates: clk@01c2006c {
235 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
236 reg = <0x01c2006c 0x4>;
238 clock-output-names = "apb1_i2c0", "apb1_i2c1",
239 "apb1_i2c2", "apb1_i2c3", "apb1_can",
240 "apb1_scr", "apb1_ps20", "apb1_ps21",
241 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
242 "apb1_uart2", "apb1_uart3", "apb1_uart4",
243 "apb1_uart5", "apb1_uart6", "apb1_uart7";
246 nand_clk: clk@01c20080 {
248 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c20080 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "nand";
254 ms_clk: clk@01c20084 {
256 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c20084 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ms";
262 mmc0_clk: clk@01c20088 {
264 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c20088 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mmc0";
270 mmc1_clk: clk@01c2008c {
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c2008c 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "mmc1";
278 mmc2_clk: clk@01c20090 {
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c20090 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "mmc2";
286 mmc3_clk: clk@01c20094 {
288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c20094 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mmc3";
294 ts_clk: clk@01c20098 {
296 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c20098 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ts";
302 ss_clk: clk@01c2009c {
304 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c2009c 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ss";
310 spi0_clk: clk@01c200a0 {
312 compatible = "allwinner,sun4i-a10-mod0-clk";
313 reg = <0x01c200a0 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "spi0";
318 spi1_clk: clk@01c200a4 {
320 compatible = "allwinner,sun4i-a10-mod0-clk";
321 reg = <0x01c200a4 0x4>;
322 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
323 clock-output-names = "spi1";
326 spi2_clk: clk@01c200a8 {
328 compatible = "allwinner,sun4i-a10-mod0-clk";
329 reg = <0x01c200a8 0x4>;
330 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
331 clock-output-names = "spi2";
334 pata_clk: clk@01c200ac {
336 compatible = "allwinner,sun4i-a10-mod0-clk";
337 reg = <0x01c200ac 0x4>;
338 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
339 clock-output-names = "pata";
342 ir0_clk: clk@01c200b0 {
344 compatible = "allwinner,sun4i-a10-mod0-clk";
345 reg = <0x01c200b0 0x4>;
346 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
347 clock-output-names = "ir0";
350 ir1_clk: clk@01c200b4 {
352 compatible = "allwinner,sun4i-a10-mod0-clk";
353 reg = <0x01c200b4 0x4>;
354 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
355 clock-output-names = "ir1";
358 usb_clk: clk@01c200cc {
361 compatible = "allwinner,sun4i-a10-usb-clk";
362 reg = <0x01c200cc 0x4>;
364 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
367 spi3_clk: clk@01c200d4 {
369 compatible = "allwinner,sun4i-a10-mod0-clk";
370 reg = <0x01c200d4 0x4>;
371 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
372 clock-output-names = "spi3";
375 mbus_clk: clk@01c2015c {
377 compatible = "allwinner,sun5i-a13-mbus-clk";
378 reg = <0x01c2015c 0x4>;
379 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
380 clock-output-names = "mbus";
384 * The following two are dummy clocks, placeholders used in the gmac_tx
385 * clock. The gmac driver will choose one parent depending on the PHY
386 * interface mode, using clk_set_rate auto-reparenting.
387 * The actual TX clock rate is not controlled by the gmac_tx clock.
389 mii_phy_tx_clk: clk@2 {
391 compatible = "fixed-clock";
392 clock-frequency = <25000000>;
393 clock-output-names = "mii_phy_tx";
396 gmac_int_tx_clk: clk@3 {
398 compatible = "fixed-clock";
399 clock-frequency = <125000000>;
400 clock-output-names = "gmac_int_tx";
403 gmac_tx_clk: clk@01c20164 {
405 compatible = "allwinner,sun7i-a20-gmac-clk";
406 reg = <0x01c20164 0x4>;
407 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
408 clock-output-names = "gmac_tx";
412 * Dummy clock used by output clocks
416 compatible = "fixed-factor-clock";
420 clock-output-names = "osc24M_32k";
423 clk_out_a: clk@01c201f0 {
425 compatible = "allwinner,sun7i-a20-out-clk";
426 reg = <0x01c201f0 0x4>;
427 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
428 clock-output-names = "clk_out_a";
431 clk_out_b: clk@01c201f4 {
433 compatible = "allwinner,sun7i-a20-out-clk";
434 reg = <0x01c201f4 0x4>;
435 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
436 clock-output-names = "clk_out_b";
441 compatible = "simple-bus";
442 #address-cells = <1>;
446 nmi_intc: interrupt-controller@01c00030 {
447 compatible = "allwinner,sun7i-a20-sc-nmi";
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 reg = <0x01c00030 0x0c>;
451 interrupts = <0 0 4>;
454 dma: dma-controller@01c02000 {
455 compatible = "allwinner,sun4i-a10-dma";
456 reg = <0x01c02000 0x1000>;
457 interrupts = <0 27 4>;
458 clocks = <&ahb_gates 6>;
463 compatible = "allwinner,sun4i-a10-spi";
464 reg = <0x01c05000 0x1000>;
465 interrupts = <0 10 4>;
466 clocks = <&ahb_gates 20>, <&spi0_clk>;
467 clock-names = "ahb", "mod";
468 dmas = <&dma 1 27>, <&dma 1 26>;
469 dma-names = "rx", "tx";
471 #address-cells = <1>;
476 compatible = "allwinner,sun4i-a10-spi";
477 reg = <0x01c06000 0x1000>;
478 interrupts = <0 11 4>;
479 clocks = <&ahb_gates 21>, <&spi1_clk>;
480 clock-names = "ahb", "mod";
481 dmas = <&dma 1 9>, <&dma 1 8>;
482 dma-names = "rx", "tx";
484 #address-cells = <1>;
488 emac: ethernet@01c0b000 {
489 compatible = "allwinner,sun4i-a10-emac";
490 reg = <0x01c0b000 0x1000>;
491 interrupts = <0 55 4>;
492 clocks = <&ahb_gates 17>;
497 compatible = "allwinner,sun4i-a10-mdio";
498 reg = <0x01c0b080 0x14>;
500 #address-cells = <1>;
505 compatible = "allwinner,sun5i-a13-mmc";
506 reg = <0x01c0f000 0x1000>;
507 clocks = <&ahb_gates 8>, <&mmc0_clk>;
508 clock-names = "ahb", "mmc";
509 interrupts = <0 32 4>;
514 compatible = "allwinner,sun5i-a13-mmc";
515 reg = <0x01c10000 0x1000>;
516 clocks = <&ahb_gates 9>, <&mmc1_clk>;
517 clock-names = "ahb", "mmc";
518 interrupts = <0 33 4>;
523 compatible = "allwinner,sun5i-a13-mmc";
524 reg = <0x01c11000 0x1000>;
525 clocks = <&ahb_gates 10>, <&mmc2_clk>;
526 clock-names = "ahb", "mmc";
527 interrupts = <0 34 4>;
532 compatible = "allwinner,sun5i-a13-mmc";
533 reg = <0x01c12000 0x1000>;
534 clocks = <&ahb_gates 11>, <&mmc3_clk>;
535 clock-names = "ahb", "mmc";
536 interrupts = <0 35 4>;
540 usbphy: phy@01c13400 {
542 compatible = "allwinner,sun7i-a20-usb-phy";
543 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
544 reg-names = "phy_ctrl", "pmu1", "pmu2";
545 clocks = <&usb_clk 8>;
546 clock-names = "usb_phy";
547 resets = <&usb_clk 1>, <&usb_clk 2>;
548 reset-names = "usb1_reset", "usb2_reset";
552 ehci0: usb@01c14000 {
553 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
554 reg = <0x01c14000 0x100>;
555 interrupts = <0 39 4>;
556 clocks = <&ahb_gates 1>;
562 ohci0: usb@01c14400 {
563 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
564 reg = <0x01c14400 0x100>;
565 interrupts = <0 64 4>;
566 clocks = <&usb_clk 6>, <&ahb_gates 2>;
573 compatible = "allwinner,sun4i-a10-spi";
574 reg = <0x01c17000 0x1000>;
575 interrupts = <0 12 4>;
576 clocks = <&ahb_gates 22>, <&spi2_clk>;
577 clock-names = "ahb", "mod";
578 dmas = <&dma 1 29>, <&dma 1 28>;
579 dma-names = "rx", "tx";
581 #address-cells = <1>;
585 ahci: sata@01c18000 {
586 compatible = "allwinner,sun4i-a10-ahci";
587 reg = <0x01c18000 0x1000>;
588 interrupts = <0 56 4>;
589 clocks = <&pll6 0>, <&ahb_gates 25>;
593 ehci1: usb@01c1c000 {
594 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
595 reg = <0x01c1c000 0x100>;
596 interrupts = <0 40 4>;
597 clocks = <&ahb_gates 3>;
603 ohci1: usb@01c1c400 {
604 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
605 reg = <0x01c1c400 0x100>;
606 interrupts = <0 65 4>;
607 clocks = <&usb_clk 7>, <&ahb_gates 4>;
614 compatible = "allwinner,sun4i-a10-spi";
615 reg = <0x01c1f000 0x1000>;
616 interrupts = <0 50 4>;
617 clocks = <&ahb_gates 23>, <&spi3_clk>;
618 clock-names = "ahb", "mod";
619 dmas = <&dma 1 31>, <&dma 1 30>;
620 dma-names = "rx", "tx";
622 #address-cells = <1>;
626 pio: pinctrl@01c20800 {
627 compatible = "allwinner,sun7i-a20-pinctrl";
628 reg = <0x01c20800 0x400>;
629 interrupts = <0 28 4>;
630 clocks = <&apb0_gates 5>;
632 interrupt-controller;
633 #interrupt-cells = <2>;
637 pwm0_pins_a: pwm0@0 {
638 allwinner,pins = "PB2";
639 allwinner,function = "pwm";
640 allwinner,drive = <0>;
641 allwinner,pull = <0>;
644 pwm1_pins_a: pwm1@0 {
645 allwinner,pins = "PI3";
646 allwinner,function = "pwm";
647 allwinner,drive = <0>;
648 allwinner,pull = <0>;
651 uart0_pins_a: uart0@0 {
652 allwinner,pins = "PB22", "PB23";
653 allwinner,function = "uart0";
654 allwinner,drive = <0>;
655 allwinner,pull = <0>;
658 uart2_pins_a: uart2@0 {
659 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
660 allwinner,function = "uart2";
661 allwinner,drive = <0>;
662 allwinner,pull = <0>;
665 uart3_pins_a: uart3@0 {
666 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
667 allwinner,function = "uart3";
668 allwinner,drive = <0>;
669 allwinner,pull = <0>;
672 uart4_pins_a: uart4@0 {
673 allwinner,pins = "PG10", "PG11";
674 allwinner,function = "uart4";
675 allwinner,drive = <0>;
676 allwinner,pull = <0>;
679 uart5_pins_a: uart5@0 {
680 allwinner,pins = "PI10", "PI11";
681 allwinner,function = "uart5";
682 allwinner,drive = <0>;
683 allwinner,pull = <0>;
686 uart6_pins_a: uart6@0 {
687 allwinner,pins = "PI12", "PI13";
688 allwinner,function = "uart6";
689 allwinner,drive = <0>;
690 allwinner,pull = <0>;
693 uart7_pins_a: uart7@0 {
694 allwinner,pins = "PI20", "PI21";
695 allwinner,function = "uart7";
696 allwinner,drive = <0>;
697 allwinner,pull = <0>;
700 i2c0_pins_a: i2c0@0 {
701 allwinner,pins = "PB0", "PB1";
702 allwinner,function = "i2c0";
703 allwinner,drive = <0>;
704 allwinner,pull = <0>;
707 i2c1_pins_a: i2c1@0 {
708 allwinner,pins = "PB18", "PB19";
709 allwinner,function = "i2c1";
710 allwinner,drive = <0>;
711 allwinner,pull = <0>;
714 i2c2_pins_a: i2c2@0 {
715 allwinner,pins = "PB20", "PB21";
716 allwinner,function = "i2c2";
717 allwinner,drive = <0>;
718 allwinner,pull = <0>;
721 i2c3_pins_a: i2c3@0 {
722 allwinner,pins = "PI0", "PI1";
723 allwinner,function = "i2c3";
724 allwinner,drive = <0>;
725 allwinner,pull = <0>;
728 emac_pins_a: emac0@0 {
729 allwinner,pins = "PA0", "PA1", "PA2",
730 "PA3", "PA4", "PA5", "PA6",
731 "PA7", "PA8", "PA9", "PA10",
732 "PA11", "PA12", "PA13", "PA14",
734 allwinner,function = "emac";
735 allwinner,drive = <0>;
736 allwinner,pull = <0>;
739 clk_out_a_pins_a: clk_out_a@0 {
740 allwinner,pins = "PI12";
741 allwinner,function = "clk_out_a";
742 allwinner,drive = <0>;
743 allwinner,pull = <0>;
746 clk_out_b_pins_a: clk_out_b@0 {
747 allwinner,pins = "PI13";
748 allwinner,function = "clk_out_b";
749 allwinner,drive = <0>;
750 allwinner,pull = <0>;
753 gmac_pins_mii_a: gmac_mii@0 {
754 allwinner,pins = "PA0", "PA1", "PA2",
755 "PA3", "PA4", "PA5", "PA6",
756 "PA7", "PA8", "PA9", "PA10",
757 "PA11", "PA12", "PA13", "PA14",
759 allwinner,function = "gmac";
760 allwinner,drive = <0>;
761 allwinner,pull = <0>;
764 gmac_pins_rgmii_a: gmac_rgmii@0 {
765 allwinner,pins = "PA0", "PA1", "PA2",
766 "PA3", "PA4", "PA5", "PA6",
767 "PA7", "PA8", "PA10",
768 "PA11", "PA12", "PA13",
770 allwinner,function = "gmac";
772 * data lines in RGMII mode use DDR mode
773 * and need a higher signal drive strength
775 allwinner,drive = <3>;
776 allwinner,pull = <0>;
779 spi1_pins_a: spi1@0 {
780 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
781 allwinner,function = "spi1";
782 allwinner,drive = <0>;
783 allwinner,pull = <0>;
786 spi2_pins_a: spi2@0 {
787 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
788 allwinner,function = "spi2";
789 allwinner,drive = <0>;
790 allwinner,pull = <0>;
793 spi2_pins_b: spi2@1 {
794 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
795 allwinner,function = "spi2";
796 allwinner,drive = <0>;
797 allwinner,pull = <0>;
800 mmc0_pins_a: mmc0@0 {
801 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
802 allwinner,function = "mmc0";
803 allwinner,drive = <2>;
804 allwinner,pull = <0>;
807 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
808 allwinner,pins = "PH1";
809 allwinner,function = "gpio_in";
810 allwinner,drive = <0>;
811 allwinner,pull = <1>;
814 mmc3_pins_a: mmc3@0 {
815 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
816 allwinner,function = "mmc3";
817 allwinner,drive = <2>;
818 allwinner,pull = <0>;
822 allwinner,pins = "PB3","PB4";
823 allwinner,function = "ir0";
824 allwinner,drive = <0>;
825 allwinner,pull = <0>;
829 allwinner,pins = "PB22","PB23";
830 allwinner,function = "ir1";
831 allwinner,drive = <0>;
832 allwinner,pull = <0>;
837 compatible = "allwinner,sun4i-a10-timer";
838 reg = <0x01c20c00 0x90>;
839 interrupts = <0 22 4>,
848 wdt: watchdog@01c20c90 {
849 compatible = "allwinner,sun4i-a10-wdt";
850 reg = <0x01c20c90 0x10>;
854 compatible = "allwinner,sun7i-a20-rtc";
855 reg = <0x01c20d00 0x20>;
856 interrupts = <0 24 4>;
860 compatible = "allwinner,sun7i-a20-pwm";
861 reg = <0x01c20e00 0xc>;
868 compatible = "allwinner,sun4i-a10-ir";
869 clocks = <&apb0_gates 6>, <&ir0_clk>;
870 clock-names = "apb", "ir";
871 interrupts = <0 5 4>;
872 reg = <0x01c21800 0x40>;
877 compatible = "allwinner,sun4i-a10-ir";
878 clocks = <&apb0_gates 7>, <&ir1_clk>;
879 clock-names = "apb", "ir";
880 interrupts = <0 6 4>;
881 reg = <0x01c21c00 0x40>;
885 sid: eeprom@01c23800 {
886 compatible = "allwinner,sun7i-a20-sid";
887 reg = <0x01c23800 0x200>;
891 compatible = "allwinner,sun4i-a10-ts";
892 reg = <0x01c25000 0x100>;
893 interrupts = <0 29 4>;
896 uart0: serial@01c28000 {
897 compatible = "snps,dw-apb-uart";
898 reg = <0x01c28000 0x400>;
899 interrupts = <0 1 4>;
902 clocks = <&apb1_gates 16>;
906 uart1: serial@01c28400 {
907 compatible = "snps,dw-apb-uart";
908 reg = <0x01c28400 0x400>;
909 interrupts = <0 2 4>;
912 clocks = <&apb1_gates 17>;
916 uart2: serial@01c28800 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c28800 0x400>;
919 interrupts = <0 3 4>;
922 clocks = <&apb1_gates 18>;
926 uart3: serial@01c28c00 {
927 compatible = "snps,dw-apb-uart";
928 reg = <0x01c28c00 0x400>;
929 interrupts = <0 4 4>;
932 clocks = <&apb1_gates 19>;
936 uart4: serial@01c29000 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c29000 0x400>;
939 interrupts = <0 17 4>;
942 clocks = <&apb1_gates 20>;
946 uart5: serial@01c29400 {
947 compatible = "snps,dw-apb-uart";
948 reg = <0x01c29400 0x400>;
949 interrupts = <0 18 4>;
952 clocks = <&apb1_gates 21>;
956 uart6: serial@01c29800 {
957 compatible = "snps,dw-apb-uart";
958 reg = <0x01c29800 0x400>;
959 interrupts = <0 19 4>;
962 clocks = <&apb1_gates 22>;
966 uart7: serial@01c29c00 {
967 compatible = "snps,dw-apb-uart";
968 reg = <0x01c29c00 0x400>;
969 interrupts = <0 20 4>;
972 clocks = <&apb1_gates 23>;
977 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
978 reg = <0x01c2ac00 0x400>;
979 interrupts = <0 7 4>;
980 clocks = <&apb1_gates 0>;
982 #address-cells = <1>;
987 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
988 reg = <0x01c2b000 0x400>;
989 interrupts = <0 8 4>;
990 clocks = <&apb1_gates 1>;
992 #address-cells = <1>;
997 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
998 reg = <0x01c2b400 0x400>;
999 interrupts = <0 9 4>;
1000 clocks = <&apb1_gates 2>;
1001 status = "disabled";
1002 #address-cells = <1>;
1006 i2c3: i2c@01c2b800 {
1007 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1008 reg = <0x01c2b800 0x400>;
1009 interrupts = <0 88 4>;
1010 clocks = <&apb1_gates 3>;
1011 status = "disabled";
1012 #address-cells = <1>;
1016 i2c4: i2c@01c2c000 {
1017 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1018 reg = <0x01c2c000 0x400>;
1019 interrupts = <0 89 4>;
1020 clocks = <&apb1_gates 15>;
1021 status = "disabled";
1022 #address-cells = <1>;
1026 gmac: ethernet@01c50000 {
1027 compatible = "allwinner,sun7i-a20-gmac";
1028 reg = <0x01c50000 0x10000>;
1029 interrupts = <0 85 4>;
1030 interrupt-names = "macirq";
1031 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1032 clock-names = "stmmaceth", "allwinner_gmac_tx";
1035 snps,force_sf_dma_mode;
1036 status = "disabled";
1037 #address-cells = <1>;
1042 compatible = "allwinner,sun7i-a20-hstimer";
1043 reg = <0x01c60000 0x1000>;
1044 interrupts = <0 81 4>,
1048 clocks = <&ahb_gates 28>;
1051 gic: interrupt-controller@01c81000 {
1052 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1053 reg = <0x01c81000 0x1000>,
1054 <0x01c82000 0x1000>,
1055 <0x01c84000 0x2000>,
1056 <0x01c86000 0x2000>;
1057 interrupt-controller;
1058 #interrupt-cells = <3>;
1059 interrupts = <1 9 0xf04>;