2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
49 reg = <0x40000000 0x80000000>;
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
65 osc24M: clk@01c20050 {
67 compatible = "allwinner,sun4i-a10-osc-clk";
68 reg = <0x01c20050 0x4>;
69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
75 compatible = "fixed-clock";
76 clock-frequency = <32768>;
77 clock-output-names = "osc32k";
82 compatible = "allwinner,sun4i-a10-pll1-clk";
83 reg = <0x01c20000 0x4>;
85 clock-output-names = "pll1";
90 compatible = "allwinner,sun4i-a10-pll1-clk";
91 reg = <0x01c20018 0x4>;
93 clock-output-names = "pll4";
98 compatible = "allwinner,sun4i-a10-pll5-clk";
99 reg = <0x01c20020 0x4>;
101 clock-output-names = "pll5_ddr", "pll5_other";
106 compatible = "allwinner,sun4i-a10-pll6-clk";
107 reg = <0x01c20028 0x4>;
109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
114 compatible = "allwinner,sun4i-a10-cpu-clk";
115 reg = <0x01c20054 0x4>;
116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
117 clock-output-names = "cpu";
122 compatible = "allwinner,sun4i-a10-axi-clk";
123 reg = <0x01c20054 0x4>;
125 clock-output-names = "axi";
130 compatible = "allwinner,sun4i-a10-ahb-clk";
131 reg = <0x01c20054 0x4>;
133 clock-output-names = "ahb";
136 ahb_gates: clk@01c20060 {
138 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
139 reg = <0x01c20060 0x8>;
141 clock-output-names = "ahb_usb0", "ahb_ehci0",
142 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
143 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
144 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
145 "ahb_nand", "ahb_sdram", "ahb_ace",
146 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
147 "ahb_spi2", "ahb_spi3", "ahb_sata",
148 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
149 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
150 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
151 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
152 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
156 apb0: apb0@01c20054 {
158 compatible = "allwinner,sun4i-a10-apb0-clk";
159 reg = <0x01c20054 0x4>;
161 clock-output-names = "apb0";
164 apb0_gates: clk@01c20068 {
166 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
167 reg = <0x01c20068 0x4>;
169 clock-output-names = "apb0_codec", "apb0_spdif",
170 "apb0_ac97", "apb0_iis0", "apb0_iis1",
171 "apb0_pio", "apb0_ir0", "apb0_ir1",
172 "apb0_iis2", "apb0_keypad";
175 apb1_mux: apb1_mux@01c20058 {
177 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
178 reg = <0x01c20058 0x4>;
179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1_mux";
183 apb1: apb1@01c20058 {
185 compatible = "allwinner,sun4i-a10-apb1-clk";
186 reg = <0x01c20058 0x4>;
187 clocks = <&apb1_mux>;
188 clock-output-names = "apb1";
191 apb1_gates: clk@01c2006c {
193 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
194 reg = <0x01c2006c 0x4>;
196 clock-output-names = "apb1_i2c0", "apb1_i2c1",
197 "apb1_i2c2", "apb1_i2c3", "apb1_can",
198 "apb1_scr", "apb1_ps20", "apb1_ps21",
199 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
200 "apb1_uart2", "apb1_uart3", "apb1_uart4",
201 "apb1_uart5", "apb1_uart6", "apb1_uart7";
204 nand_clk: clk@01c20080 {
206 compatible = "allwinner,sun4i-a10-mod0-clk";
207 reg = <0x01c20080 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "nand";
212 ms_clk: clk@01c20084 {
214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20084 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "ms";
220 mmc0_clk: clk@01c20088 {
222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc0";
228 mmc1_clk: clk@01c2008c {
230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c2008c 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc1";
236 mmc2_clk: clk@01c20090 {
238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c20090 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc2";
244 mmc3_clk: clk@01c20094 {
246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c20094 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc3";
252 ts_clk: clk@01c20098 {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20098 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "ts";
260 ss_clk: clk@01c2009c {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c2009c 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "ss";
268 spi0_clk: clk@01c200a0 {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c200a0 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "spi0";
276 spi1_clk: clk@01c200a4 {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c200a4 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi1";
284 spi2_clk: clk@01c200a8 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200a8 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi2";
292 pata_clk: clk@01c200ac {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c200ac 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "pata";
300 ir0_clk: clk@01c200b0 {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200b0 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "ir0";
308 ir1_clk: clk@01c200b4 {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200b4 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "ir1";
316 usb_clk: clk@01c200cc {
319 compatible = "allwinner,sun4i-a10-usb-clk";
320 reg = <0x01c200cc 0x4>;
322 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 spi3_clk: clk@01c200d4 {
327 compatible = "allwinner,sun4i-a10-mod0-clk";
328 reg = <0x01c200d4 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "spi3";
333 mbus_clk: clk@01c2015c {
335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c2015c 0x4>;
337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
338 clock-output-names = "mbus";
342 * The following two are dummy clocks, placeholders used in the gmac_tx
343 * clock. The gmac driver will choose one parent depending on the PHY
344 * interface mode, using clk_set_rate auto-reparenting.
345 * The actual TX clock rate is not controlled by the gmac_tx clock.
347 mii_phy_tx_clk: clk@2 {
349 compatible = "fixed-clock";
350 clock-frequency = <25000000>;
351 clock-output-names = "mii_phy_tx";
354 gmac_int_tx_clk: clk@3 {
356 compatible = "fixed-clock";
357 clock-frequency = <125000000>;
358 clock-output-names = "gmac_int_tx";
361 gmac_tx_clk: clk@01c20164 {
363 compatible = "allwinner,sun7i-a20-gmac-clk";
364 reg = <0x01c20164 0x4>;
365 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
366 clock-output-names = "gmac_tx";
370 * Dummy clock used by output clocks
374 compatible = "fixed-factor-clock";
378 clock-output-names = "osc24M_32k";
381 clk_out_a: clk@01c201f0 {
383 compatible = "allwinner,sun7i-a20-out-clk";
384 reg = <0x01c201f0 0x4>;
385 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
386 clock-output-names = "clk_out_a";
389 clk_out_b: clk@01c201f4 {
391 compatible = "allwinner,sun7i-a20-out-clk";
392 reg = <0x01c201f4 0x4>;
393 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
394 clock-output-names = "clk_out_b";
399 compatible = "simple-bus";
400 #address-cells = <1>;
404 nmi_intc: interrupt-controller@01c00030 {
405 compatible = "allwinner,sun7i-a20-sc-nmi";
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 reg = <0x01c00030 0x0c>;
409 interrupts = <0 0 4>;
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c05000 0x1000>;
415 interrupts = <0 10 4>;
416 clocks = <&ahb_gates 20>, <&spi0_clk>;
417 clock-names = "ahb", "mod";
419 #address-cells = <1>;
424 compatible = "allwinner,sun4i-a10-spi";
425 reg = <0x01c06000 0x1000>;
426 interrupts = <0 11 4>;
427 clocks = <&ahb_gates 21>, <&spi1_clk>;
428 clock-names = "ahb", "mod";
430 #address-cells = <1>;
434 emac: ethernet@01c0b000 {
435 compatible = "allwinner,sun4i-a10-emac";
436 reg = <0x01c0b000 0x1000>;
437 interrupts = <0 55 4>;
438 clocks = <&ahb_gates 17>;
443 compatible = "allwinner,sun4i-a10-mdio";
444 reg = <0x01c0b080 0x14>;
446 #address-cells = <1>;
450 usbphy: phy@01c13400 {
452 compatible = "allwinner,sun7i-a20-usb-phy";
453 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
454 reg-names = "phy_ctrl", "pmu1", "pmu2";
455 clocks = <&usb_clk 8>;
456 clock-names = "usb_phy";
457 resets = <&usb_clk 1>, <&usb_clk 2>;
458 reset-names = "usb1_reset", "usb2_reset";
462 ehci0: usb@01c14000 {
463 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
464 reg = <0x01c14000 0x100>;
465 interrupts = <0 39 4>;
466 clocks = <&ahb_gates 1>;
472 ohci0: usb@01c14400 {
473 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
474 reg = <0x01c14400 0x100>;
475 interrupts = <0 64 4>;
476 clocks = <&usb_clk 6>, <&ahb_gates 2>;
483 compatible = "allwinner,sun4i-a10-spi";
484 reg = <0x01c17000 0x1000>;
485 interrupts = <0 12 4>;
486 clocks = <&ahb_gates 22>, <&spi2_clk>;
487 clock-names = "ahb", "mod";
489 #address-cells = <1>;
493 ahci: sata@01c18000 {
494 compatible = "allwinner,sun4i-a10-ahci";
495 reg = <0x01c18000 0x1000>;
496 interrupts = <0 56 4>;
497 clocks = <&pll6 0>, <&ahb_gates 25>;
501 ehci1: usb@01c1c000 {
502 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
503 reg = <0x01c1c000 0x100>;
504 interrupts = <0 40 4>;
505 clocks = <&ahb_gates 3>;
511 ohci1: usb@01c1c400 {
512 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
513 reg = <0x01c1c400 0x100>;
514 interrupts = <0 65 4>;
515 clocks = <&usb_clk 7>, <&ahb_gates 4>;
522 compatible = "allwinner,sun4i-a10-spi";
523 reg = <0x01c1f000 0x1000>;
524 interrupts = <0 50 4>;
525 clocks = <&ahb_gates 23>, <&spi3_clk>;
526 clock-names = "ahb", "mod";
528 #address-cells = <1>;
532 pio: pinctrl@01c20800 {
533 compatible = "allwinner,sun7i-a20-pinctrl";
534 reg = <0x01c20800 0x400>;
535 interrupts = <0 28 4>;
536 clocks = <&apb0_gates 5>;
538 interrupt-controller;
539 #address-cells = <1>;
543 uart0_pins_a: uart0@0 {
544 allwinner,pins = "PB22", "PB23";
545 allwinner,function = "uart0";
546 allwinner,drive = <0>;
547 allwinner,pull = <0>;
550 uart2_pins_a: uart2@0 {
551 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
552 allwinner,function = "uart2";
553 allwinner,drive = <0>;
554 allwinner,pull = <0>;
557 uart6_pins_a: uart6@0 {
558 allwinner,pins = "PI12", "PI13";
559 allwinner,function = "uart6";
560 allwinner,drive = <0>;
561 allwinner,pull = <0>;
564 uart7_pins_a: uart7@0 {
565 allwinner,pins = "PI20", "PI21";
566 allwinner,function = "uart7";
567 allwinner,drive = <0>;
568 allwinner,pull = <0>;
571 i2c0_pins_a: i2c0@0 {
572 allwinner,pins = "PB0", "PB1";
573 allwinner,function = "i2c0";
574 allwinner,drive = <0>;
575 allwinner,pull = <0>;
578 i2c1_pins_a: i2c1@0 {
579 allwinner,pins = "PB18", "PB19";
580 allwinner,function = "i2c1";
581 allwinner,drive = <0>;
582 allwinner,pull = <0>;
585 i2c2_pins_a: i2c2@0 {
586 allwinner,pins = "PB20", "PB21";
587 allwinner,function = "i2c2";
588 allwinner,drive = <0>;
589 allwinner,pull = <0>;
592 emac_pins_a: emac0@0 {
593 allwinner,pins = "PA0", "PA1", "PA2",
594 "PA3", "PA4", "PA5", "PA6",
595 "PA7", "PA8", "PA9", "PA10",
596 "PA11", "PA12", "PA13", "PA14",
598 allwinner,function = "emac";
599 allwinner,drive = <0>;
600 allwinner,pull = <0>;
603 clk_out_a_pins_a: clk_out_a@0 {
604 allwinner,pins = "PI12";
605 allwinner,function = "clk_out_a";
606 allwinner,drive = <0>;
607 allwinner,pull = <0>;
610 clk_out_b_pins_a: clk_out_b@0 {
611 allwinner,pins = "PI13";
612 allwinner,function = "clk_out_b";
613 allwinner,drive = <0>;
614 allwinner,pull = <0>;
617 gmac_pins_mii_a: gmac_mii@0 {
618 allwinner,pins = "PA0", "PA1", "PA2",
619 "PA3", "PA4", "PA5", "PA6",
620 "PA7", "PA8", "PA9", "PA10",
621 "PA11", "PA12", "PA13", "PA14",
623 allwinner,function = "gmac";
624 allwinner,drive = <0>;
625 allwinner,pull = <0>;
628 gmac_pins_rgmii_a: gmac_rgmii@0 {
629 allwinner,pins = "PA0", "PA1", "PA2",
630 "PA3", "PA4", "PA5", "PA6",
631 "PA7", "PA8", "PA10",
632 "PA11", "PA12", "PA13",
634 allwinner,function = "gmac";
636 * data lines in RGMII mode use DDR mode
637 * and need a higher signal drive strength
639 allwinner,drive = <3>;
640 allwinner,pull = <0>;
643 spi1_pins_a: spi1@0 {
644 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
645 allwinner,function = "spi1";
646 allwinner,drive = <0>;
647 allwinner,pull = <0>;
650 spi2_pins_a: spi2@0 {
651 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
652 allwinner,function = "spi2";
653 allwinner,drive = <0>;
654 allwinner,pull = <0>;
659 compatible = "allwinner,sun4i-a10-timer";
660 reg = <0x01c20c00 0x90>;
661 interrupts = <0 22 4>,
670 wdt: watchdog@01c20c90 {
671 compatible = "allwinner,sun4i-a10-wdt";
672 reg = <0x01c20c90 0x10>;
676 compatible = "allwinner,sun7i-a20-rtc";
677 reg = <0x01c20d00 0x20>;
678 interrupts = <0 24 4>;
681 sid: eeprom@01c23800 {
682 compatible = "allwinner,sun7i-a20-sid";
683 reg = <0x01c23800 0x200>;
687 compatible = "allwinner,sun4i-a10-ts";
688 reg = <0x01c25000 0x100>;
689 interrupts = <0 29 4>;
692 uart0: serial@01c28000 {
693 compatible = "snps,dw-apb-uart";
694 reg = <0x01c28000 0x400>;
695 interrupts = <0 1 4>;
698 clocks = <&apb1_gates 16>;
702 uart1: serial@01c28400 {
703 compatible = "snps,dw-apb-uart";
704 reg = <0x01c28400 0x400>;
705 interrupts = <0 2 4>;
708 clocks = <&apb1_gates 17>;
712 uart2: serial@01c28800 {
713 compatible = "snps,dw-apb-uart";
714 reg = <0x01c28800 0x400>;
715 interrupts = <0 3 4>;
718 clocks = <&apb1_gates 18>;
722 uart3: serial@01c28c00 {
723 compatible = "snps,dw-apb-uart";
724 reg = <0x01c28c00 0x400>;
725 interrupts = <0 4 4>;
728 clocks = <&apb1_gates 19>;
732 uart4: serial@01c29000 {
733 compatible = "snps,dw-apb-uart";
734 reg = <0x01c29000 0x400>;
735 interrupts = <0 17 4>;
738 clocks = <&apb1_gates 20>;
742 uart5: serial@01c29400 {
743 compatible = "snps,dw-apb-uart";
744 reg = <0x01c29400 0x400>;
745 interrupts = <0 18 4>;
748 clocks = <&apb1_gates 21>;
752 uart6: serial@01c29800 {
753 compatible = "snps,dw-apb-uart";
754 reg = <0x01c29800 0x400>;
755 interrupts = <0 19 4>;
758 clocks = <&apb1_gates 22>;
762 uart7: serial@01c29c00 {
763 compatible = "snps,dw-apb-uart";
764 reg = <0x01c29c00 0x400>;
765 interrupts = <0 20 4>;
768 clocks = <&apb1_gates 23>;
773 compatible = "allwinner,sun4i-i2c";
774 reg = <0x01c2ac00 0x400>;
775 interrupts = <0 7 4>;
776 clocks = <&apb1_gates 0>;
777 clock-frequency = <100000>;
782 compatible = "allwinner,sun4i-i2c";
783 reg = <0x01c2b000 0x400>;
784 interrupts = <0 8 4>;
785 clocks = <&apb1_gates 1>;
786 clock-frequency = <100000>;
791 compatible = "allwinner,sun4i-i2c";
792 reg = <0x01c2b400 0x400>;
793 interrupts = <0 9 4>;
794 clocks = <&apb1_gates 2>;
795 clock-frequency = <100000>;
800 compatible = "allwinner,sun4i-i2c";
801 reg = <0x01c2b800 0x400>;
802 interrupts = <0 88 4>;
803 clocks = <&apb1_gates 3>;
804 clock-frequency = <100000>;
809 compatible = "allwinner,sun4i-i2c";
810 reg = <0x01c2bc00 0x400>;
811 interrupts = <0 89 4>;
812 clocks = <&apb1_gates 15>;
813 clock-frequency = <100000>;
817 gmac: ethernet@01c50000 {
818 compatible = "allwinner,sun7i-a20-gmac";
819 reg = <0x01c50000 0x10000>;
820 interrupts = <0 85 4>;
821 interrupt-names = "macirq";
822 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
823 clock-names = "stmmaceth", "allwinner_gmac_tx";
826 snps,force_sf_dma_mode;
828 #address-cells = <1>;
833 compatible = "allwinner,sun7i-a20-hstimer";
834 reg = <0x01c60000 0x1000>;
835 interrupts = <0 81 4>,
839 clocks = <&ahb_gates 28>;
842 gic: interrupt-controller@01c81000 {
843 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
844 reg = <0x01c81000 0x1000>,
848 interrupt-controller;
849 #interrupt-cells = <3>;
850 interrupts = <1 9 0xf04>;