2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton.dtsi"
53 interrupt-parent = <&gic>;
65 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
91 reg = <0x40000000 0x80000000>;
95 compatible = "arm,armv7-timer";
96 interrupts = <1 13 0xf08>,
103 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
104 interrupts = <0 120 4>,
109 #address-cells = <1>;
113 osc24M: clk@01c20050 {
115 compatible = "allwinner,sun4i-a10-osc-clk";
116 reg = <0x01c20050 0x4>;
117 clock-frequency = <24000000>;
118 clock-output-names = "osc24M";
123 compatible = "fixed-clock";
124 clock-frequency = <32768>;
125 clock-output-names = "osc32k";
130 compatible = "allwinner,sun4i-a10-pll1-clk";
131 reg = <0x01c20000 0x4>;
133 clock-output-names = "pll1";
138 compatible = "allwinner,sun7i-a20-pll4-clk";
139 reg = <0x01c20018 0x4>;
141 clock-output-names = "pll4";
146 compatible = "allwinner,sun4i-a10-pll5-clk";
147 reg = <0x01c20020 0x4>;
149 clock-output-names = "pll5_ddr", "pll5_other";
154 compatible = "allwinner,sun4i-a10-pll6-clk";
155 reg = <0x01c20028 0x4>;
157 clock-output-names = "pll6_sata", "pll6_other", "pll6";
162 compatible = "allwinner,sun7i-a20-pll4-clk";
163 reg = <0x01c20040 0x4>;
165 clock-output-names = "pll8";
170 compatible = "allwinner,sun4i-a10-cpu-clk";
171 reg = <0x01c20054 0x4>;
172 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
173 clock-output-names = "cpu";
178 compatible = "allwinner,sun4i-a10-axi-clk";
179 reg = <0x01c20054 0x4>;
181 clock-output-names = "axi";
186 compatible = "allwinner,sun4i-a10-ahb-clk";
187 reg = <0x01c20054 0x4>;
189 clock-output-names = "ahb";
192 ahb_gates: clk@01c20060 {
194 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
195 reg = <0x01c20060 0x8>;
197 clock-output-names = "ahb_usb0", "ahb_ehci0",
198 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
199 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
200 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
201 "ahb_nand", "ahb_sdram", "ahb_ace",
202 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
203 "ahb_spi2", "ahb_spi3", "ahb_sata",
204 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
205 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
206 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
207 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
208 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
212 apb0: apb0@01c20054 {
214 compatible = "allwinner,sun4i-a10-apb0-clk";
215 reg = <0x01c20054 0x4>;
217 clock-output-names = "apb0";
220 apb0_gates: clk@01c20068 {
222 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
223 reg = <0x01c20068 0x4>;
225 clock-output-names = "apb0_codec", "apb0_spdif",
226 "apb0_ac97", "apb0_iis0", "apb0_iis1",
227 "apb0_pio", "apb0_ir0", "apb0_ir1",
228 "apb0_iis2", "apb0_keypad";
233 compatible = "allwinner,sun4i-a10-apb1-clk";
234 reg = <0x01c20058 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
236 clock-output-names = "apb1";
239 apb1_gates: clk@01c2006c {
241 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
242 reg = <0x01c2006c 0x4>;
244 clock-output-names = "apb1_i2c0", "apb1_i2c1",
245 "apb1_i2c2", "apb1_i2c3", "apb1_can",
246 "apb1_scr", "apb1_ps20", "apb1_ps21",
247 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
248 "apb1_uart2", "apb1_uart3", "apb1_uart4",
249 "apb1_uart5", "apb1_uart6", "apb1_uart7";
252 nand_clk: clk@01c20080 {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20080 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "nand";
260 ms_clk: clk@01c20084 {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c20084 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "ms";
268 mmc0_clk: clk@01c20088 {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c20088 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "mmc0";
276 mmc1_clk: clk@01c2008c {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c2008c 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "mmc1";
284 mmc2_clk: clk@01c20090 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c20090 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "mmc2";
292 mmc3_clk: clk@01c20094 {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c20094 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "mmc3";
300 ts_clk: clk@01c20098 {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c20098 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "ts";
308 ss_clk: clk@01c2009c {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c2009c 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "ss";
316 spi0_clk: clk@01c200a0 {
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c200a0 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "spi0";
324 spi1_clk: clk@01c200a4 {
326 compatible = "allwinner,sun4i-a10-mod0-clk";
327 reg = <0x01c200a4 0x4>;
328 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329 clock-output-names = "spi1";
332 spi2_clk: clk@01c200a8 {
334 compatible = "allwinner,sun4i-a10-mod0-clk";
335 reg = <0x01c200a8 0x4>;
336 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
337 clock-output-names = "spi2";
340 pata_clk: clk@01c200ac {
342 compatible = "allwinner,sun4i-a10-mod0-clk";
343 reg = <0x01c200ac 0x4>;
344 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
345 clock-output-names = "pata";
348 ir0_clk: clk@01c200b0 {
350 compatible = "allwinner,sun4i-a10-mod0-clk";
351 reg = <0x01c200b0 0x4>;
352 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
353 clock-output-names = "ir0";
356 ir1_clk: clk@01c200b4 {
358 compatible = "allwinner,sun4i-a10-mod0-clk";
359 reg = <0x01c200b4 0x4>;
360 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
361 clock-output-names = "ir1";
364 usb_clk: clk@01c200cc {
367 compatible = "allwinner,sun4i-a10-usb-clk";
368 reg = <0x01c200cc 0x4>;
370 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
373 spi3_clk: clk@01c200d4 {
375 compatible = "allwinner,sun4i-a10-mod0-clk";
376 reg = <0x01c200d4 0x4>;
377 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
378 clock-output-names = "spi3";
381 mbus_clk: clk@01c2015c {
383 compatible = "allwinner,sun5i-a13-mbus-clk";
384 reg = <0x01c2015c 0x4>;
385 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
386 clock-output-names = "mbus";
390 * The following two are dummy clocks, placeholders used in the gmac_tx
391 * clock. The gmac driver will choose one parent depending on the PHY
392 * interface mode, using clk_set_rate auto-reparenting.
393 * The actual TX clock rate is not controlled by the gmac_tx clock.
395 mii_phy_tx_clk: clk@2 {
397 compatible = "fixed-clock";
398 clock-frequency = <25000000>;
399 clock-output-names = "mii_phy_tx";
402 gmac_int_tx_clk: clk@3 {
404 compatible = "fixed-clock";
405 clock-frequency = <125000000>;
406 clock-output-names = "gmac_int_tx";
409 gmac_tx_clk: clk@01c20164 {
411 compatible = "allwinner,sun7i-a20-gmac-clk";
412 reg = <0x01c20164 0x4>;
413 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
414 clock-output-names = "gmac_tx";
418 * Dummy clock used by output clocks
422 compatible = "fixed-factor-clock";
426 clock-output-names = "osc24M_32k";
429 clk_out_a: clk@01c201f0 {
431 compatible = "allwinner,sun7i-a20-out-clk";
432 reg = <0x01c201f0 0x4>;
433 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
434 clock-output-names = "clk_out_a";
437 clk_out_b: clk@01c201f4 {
439 compatible = "allwinner,sun7i-a20-out-clk";
440 reg = <0x01c201f4 0x4>;
441 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
442 clock-output-names = "clk_out_b";
447 compatible = "simple-bus";
448 #address-cells = <1>;
452 nmi_intc: interrupt-controller@01c00030 {
453 compatible = "allwinner,sun7i-a20-sc-nmi";
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 reg = <0x01c00030 0x0c>;
457 interrupts = <0 0 4>;
460 dma: dma-controller@01c02000 {
461 compatible = "allwinner,sun4i-a10-dma";
462 reg = <0x01c02000 0x1000>;
463 interrupts = <0 27 4>;
464 clocks = <&ahb_gates 6>;
469 compatible = "allwinner,sun4i-a10-spi";
470 reg = <0x01c05000 0x1000>;
471 interrupts = <0 10 4>;
472 clocks = <&ahb_gates 20>, <&spi0_clk>;
473 clock-names = "ahb", "mod";
474 dmas = <&dma 1 27>, <&dma 1 26>;
475 dma-names = "rx", "tx";
477 #address-cells = <1>;
482 compatible = "allwinner,sun4i-a10-spi";
483 reg = <0x01c06000 0x1000>;
484 interrupts = <0 11 4>;
485 clocks = <&ahb_gates 21>, <&spi1_clk>;
486 clock-names = "ahb", "mod";
487 dmas = <&dma 1 9>, <&dma 1 8>;
488 dma-names = "rx", "tx";
490 #address-cells = <1>;
494 emac: ethernet@01c0b000 {
495 compatible = "allwinner,sun4i-a10-emac";
496 reg = <0x01c0b000 0x1000>;
497 interrupts = <0 55 4>;
498 clocks = <&ahb_gates 17>;
503 compatible = "allwinner,sun4i-a10-mdio";
504 reg = <0x01c0b080 0x14>;
506 #address-cells = <1>;
511 compatible = "allwinner,sun5i-a13-mmc";
512 reg = <0x01c0f000 0x1000>;
513 clocks = <&ahb_gates 8>, <&mmc0_clk>;
514 clock-names = "ahb", "mmc";
515 interrupts = <0 32 4>;
520 compatible = "allwinner,sun5i-a13-mmc";
521 reg = <0x01c10000 0x1000>;
522 clocks = <&ahb_gates 9>, <&mmc1_clk>;
523 clock-names = "ahb", "mmc";
524 interrupts = <0 33 4>;
529 compatible = "allwinner,sun5i-a13-mmc";
530 reg = <0x01c11000 0x1000>;
531 clocks = <&ahb_gates 10>, <&mmc2_clk>;
532 clock-names = "ahb", "mmc";
533 interrupts = <0 34 4>;
538 compatible = "allwinner,sun5i-a13-mmc";
539 reg = <0x01c12000 0x1000>;
540 clocks = <&ahb_gates 11>, <&mmc3_clk>;
541 clock-names = "ahb", "mmc";
542 interrupts = <0 35 4>;
546 usbphy: phy@01c13400 {
548 compatible = "allwinner,sun7i-a20-usb-phy";
549 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
550 reg-names = "phy_ctrl", "pmu1", "pmu2";
551 clocks = <&usb_clk 8>;
552 clock-names = "usb_phy";
553 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
554 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
558 ehci0: usb@01c14000 {
559 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
560 reg = <0x01c14000 0x100>;
561 interrupts = <0 39 4>;
562 clocks = <&ahb_gates 1>;
568 ohci0: usb@01c14400 {
569 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
570 reg = <0x01c14400 0x100>;
571 interrupts = <0 64 4>;
572 clocks = <&usb_clk 6>, <&ahb_gates 2>;
579 compatible = "allwinner,sun4i-a10-spi";
580 reg = <0x01c17000 0x1000>;
581 interrupts = <0 12 4>;
582 clocks = <&ahb_gates 22>, <&spi2_clk>;
583 clock-names = "ahb", "mod";
584 dmas = <&dma 1 29>, <&dma 1 28>;
585 dma-names = "rx", "tx";
587 #address-cells = <1>;
591 ahci: sata@01c18000 {
592 compatible = "allwinner,sun4i-a10-ahci";
593 reg = <0x01c18000 0x1000>;
594 interrupts = <0 56 4>;
595 clocks = <&pll6 0>, <&ahb_gates 25>;
599 ehci1: usb@01c1c000 {
600 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
601 reg = <0x01c1c000 0x100>;
602 interrupts = <0 40 4>;
603 clocks = <&ahb_gates 3>;
609 ohci1: usb@01c1c400 {
610 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
611 reg = <0x01c1c400 0x100>;
612 interrupts = <0 65 4>;
613 clocks = <&usb_clk 7>, <&ahb_gates 4>;
620 compatible = "allwinner,sun4i-a10-spi";
621 reg = <0x01c1f000 0x1000>;
622 interrupts = <0 50 4>;
623 clocks = <&ahb_gates 23>, <&spi3_clk>;
624 clock-names = "ahb", "mod";
625 dmas = <&dma 1 31>, <&dma 1 30>;
626 dma-names = "rx", "tx";
628 #address-cells = <1>;
632 pio: pinctrl@01c20800 {
633 compatible = "allwinner,sun7i-a20-pinctrl";
634 reg = <0x01c20800 0x400>;
635 interrupts = <0 28 4>;
636 clocks = <&apb0_gates 5>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
643 pwm0_pins_a: pwm0@0 {
644 allwinner,pins = "PB2";
645 allwinner,function = "pwm";
646 allwinner,drive = <0>;
647 allwinner,pull = <0>;
650 pwm1_pins_a: pwm1@0 {
651 allwinner,pins = "PI3";
652 allwinner,function = "pwm";
653 allwinner,drive = <0>;
654 allwinner,pull = <0>;
657 uart0_pins_a: uart0@0 {
658 allwinner,pins = "PB22", "PB23";
659 allwinner,function = "uart0";
660 allwinner,drive = <0>;
661 allwinner,pull = <0>;
664 uart2_pins_a: uart2@0 {
665 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
666 allwinner,function = "uart2";
667 allwinner,drive = <0>;
668 allwinner,pull = <0>;
671 uart3_pins_a: uart3@0 {
672 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
673 allwinner,function = "uart3";
674 allwinner,drive = <0>;
675 allwinner,pull = <0>;
678 uart3_pins_b: uart3@1 {
679 allwinner,pins = "PH0", "PH1";
680 allwinner,function = "uart3";
681 allwinner,drive = <0>;
682 allwinner,pull = <0>;
685 uart4_pins_a: uart4@0 {
686 allwinner,pins = "PG10", "PG11";
687 allwinner,function = "uart4";
688 allwinner,drive = <0>;
689 allwinner,pull = <0>;
692 uart5_pins_a: uart5@0 {
693 allwinner,pins = "PI10", "PI11";
694 allwinner,function = "uart5";
695 allwinner,drive = <0>;
696 allwinner,pull = <0>;
699 uart6_pins_a: uart6@0 {
700 allwinner,pins = "PI12", "PI13";
701 allwinner,function = "uart6";
702 allwinner,drive = <0>;
703 allwinner,pull = <0>;
706 uart7_pins_a: uart7@0 {
707 allwinner,pins = "PI20", "PI21";
708 allwinner,function = "uart7";
709 allwinner,drive = <0>;
710 allwinner,pull = <0>;
713 i2c0_pins_a: i2c0@0 {
714 allwinner,pins = "PB0", "PB1";
715 allwinner,function = "i2c0";
716 allwinner,drive = <0>;
717 allwinner,pull = <0>;
720 i2c1_pins_a: i2c1@0 {
721 allwinner,pins = "PB18", "PB19";
722 allwinner,function = "i2c1";
723 allwinner,drive = <0>;
724 allwinner,pull = <0>;
727 i2c2_pins_a: i2c2@0 {
728 allwinner,pins = "PB20", "PB21";
729 allwinner,function = "i2c2";
730 allwinner,drive = <0>;
731 allwinner,pull = <0>;
734 i2c3_pins_a: i2c3@0 {
735 allwinner,pins = "PI0", "PI1";
736 allwinner,function = "i2c3";
737 allwinner,drive = <0>;
738 allwinner,pull = <0>;
741 emac_pins_a: emac0@0 {
742 allwinner,pins = "PA0", "PA1", "PA2",
743 "PA3", "PA4", "PA5", "PA6",
744 "PA7", "PA8", "PA9", "PA10",
745 "PA11", "PA12", "PA13", "PA14",
747 allwinner,function = "emac";
748 allwinner,drive = <0>;
749 allwinner,pull = <0>;
752 clk_out_a_pins_a: clk_out_a@0 {
753 allwinner,pins = "PI12";
754 allwinner,function = "clk_out_a";
755 allwinner,drive = <0>;
756 allwinner,pull = <0>;
759 clk_out_b_pins_a: clk_out_b@0 {
760 allwinner,pins = "PI13";
761 allwinner,function = "clk_out_b";
762 allwinner,drive = <0>;
763 allwinner,pull = <0>;
766 gmac_pins_mii_a: gmac_mii@0 {
767 allwinner,pins = "PA0", "PA1", "PA2",
768 "PA3", "PA4", "PA5", "PA6",
769 "PA7", "PA8", "PA9", "PA10",
770 "PA11", "PA12", "PA13", "PA14",
772 allwinner,function = "gmac";
773 allwinner,drive = <0>;
774 allwinner,pull = <0>;
777 gmac_pins_rgmii_a: gmac_rgmii@0 {
778 allwinner,pins = "PA0", "PA1", "PA2",
779 "PA3", "PA4", "PA5", "PA6",
780 "PA7", "PA8", "PA10",
781 "PA11", "PA12", "PA13",
783 allwinner,function = "gmac";
785 * data lines in RGMII mode use DDR mode
786 * and need a higher signal drive strength
788 allwinner,drive = <3>;
789 allwinner,pull = <0>;
792 spi0_pins_a: spi0@0 {
793 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
794 allwinner,function = "spi0";
795 allwinner,drive = <0>;
796 allwinner,pull = <0>;
799 spi1_pins_a: spi1@0 {
800 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
801 allwinner,function = "spi1";
802 allwinner,drive = <0>;
803 allwinner,pull = <0>;
806 spi2_pins_a: spi2@0 {
807 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
808 allwinner,function = "spi2";
809 allwinner,drive = <0>;
810 allwinner,pull = <0>;
813 spi2_pins_b: spi2@1 {
814 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
815 allwinner,function = "spi2";
816 allwinner,drive = <0>;
817 allwinner,pull = <0>;
820 mmc0_pins_a: mmc0@0 {
821 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
822 allwinner,function = "mmc0";
823 allwinner,drive = <2>;
824 allwinner,pull = <0>;
827 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
828 allwinner,pins = "PH1";
829 allwinner,function = "gpio_in";
830 allwinner,drive = <0>;
831 allwinner,pull = <1>;
834 mmc2_pins_a: mmc2@0 {
835 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
836 allwinner,function = "mmc2";
837 allwinner,drive = <2>;
838 allwinner,pull = <1>;
841 mmc3_pins_a: mmc3@0 {
842 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
843 allwinner,function = "mmc3";
844 allwinner,drive = <2>;
845 allwinner,pull = <0>;
849 allwinner,pins = "PB3","PB4";
850 allwinner,function = "ir0";
851 allwinner,drive = <0>;
852 allwinner,pull = <0>;
856 allwinner,pins = "PB22","PB23";
857 allwinner,function = "ir1";
858 allwinner,drive = <0>;
859 allwinner,pull = <0>;
864 compatible = "allwinner,sun4i-a10-timer";
865 reg = <0x01c20c00 0x90>;
866 interrupts = <0 22 4>,
875 wdt: watchdog@01c20c90 {
876 compatible = "allwinner,sun4i-a10-wdt";
877 reg = <0x01c20c90 0x10>;
881 compatible = "allwinner,sun7i-a20-rtc";
882 reg = <0x01c20d00 0x20>;
883 interrupts = <0 24 4>;
887 compatible = "allwinner,sun7i-a20-pwm";
888 reg = <0x01c20e00 0xc>;
895 compatible = "allwinner,sun4i-a10-ir";
896 clocks = <&apb0_gates 6>, <&ir0_clk>;
897 clock-names = "apb", "ir";
898 interrupts = <0 5 4>;
899 reg = <0x01c21800 0x40>;
904 compatible = "allwinner,sun4i-a10-ir";
905 clocks = <&apb0_gates 7>, <&ir1_clk>;
906 clock-names = "apb", "ir";
907 interrupts = <0 6 4>;
908 reg = <0x01c21c00 0x40>;
912 sid: eeprom@01c23800 {
913 compatible = "allwinner,sun7i-a20-sid";
914 reg = <0x01c23800 0x200>;
918 compatible = "allwinner,sun4i-a10-ts";
919 reg = <0x01c25000 0x100>;
920 interrupts = <0 29 4>;
923 uart0: serial@01c28000 {
924 compatible = "snps,dw-apb-uart";
925 reg = <0x01c28000 0x400>;
926 interrupts = <0 1 4>;
929 clocks = <&apb1_gates 16>;
933 uart1: serial@01c28400 {
934 compatible = "snps,dw-apb-uart";
935 reg = <0x01c28400 0x400>;
936 interrupts = <0 2 4>;
939 clocks = <&apb1_gates 17>;
943 uart2: serial@01c28800 {
944 compatible = "snps,dw-apb-uart";
945 reg = <0x01c28800 0x400>;
946 interrupts = <0 3 4>;
949 clocks = <&apb1_gates 18>;
953 uart3: serial@01c28c00 {
954 compatible = "snps,dw-apb-uart";
955 reg = <0x01c28c00 0x400>;
956 interrupts = <0 4 4>;
959 clocks = <&apb1_gates 19>;
963 uart4: serial@01c29000 {
964 compatible = "snps,dw-apb-uart";
965 reg = <0x01c29000 0x400>;
966 interrupts = <0 17 4>;
969 clocks = <&apb1_gates 20>;
973 uart5: serial@01c29400 {
974 compatible = "snps,dw-apb-uart";
975 reg = <0x01c29400 0x400>;
976 interrupts = <0 18 4>;
979 clocks = <&apb1_gates 21>;
983 uart6: serial@01c29800 {
984 compatible = "snps,dw-apb-uart";
985 reg = <0x01c29800 0x400>;
986 interrupts = <0 19 4>;
989 clocks = <&apb1_gates 22>;
993 uart7: serial@01c29c00 {
994 compatible = "snps,dw-apb-uart";
995 reg = <0x01c29c00 0x400>;
996 interrupts = <0 20 4>;
999 clocks = <&apb1_gates 23>;
1000 status = "disabled";
1003 i2c0: i2c@01c2ac00 {
1004 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1005 reg = <0x01c2ac00 0x400>;
1006 interrupts = <0 7 4>;
1007 clocks = <&apb1_gates 0>;
1008 status = "disabled";
1009 #address-cells = <1>;
1013 i2c1: i2c@01c2b000 {
1014 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1015 reg = <0x01c2b000 0x400>;
1016 interrupts = <0 8 4>;
1017 clocks = <&apb1_gates 1>;
1018 status = "disabled";
1019 #address-cells = <1>;
1023 i2c2: i2c@01c2b400 {
1024 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1025 reg = <0x01c2b400 0x400>;
1026 interrupts = <0 9 4>;
1027 clocks = <&apb1_gates 2>;
1028 status = "disabled";
1029 #address-cells = <1>;
1033 i2c3: i2c@01c2b800 {
1034 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1035 reg = <0x01c2b800 0x400>;
1036 interrupts = <0 88 4>;
1037 clocks = <&apb1_gates 3>;
1038 status = "disabled";
1039 #address-cells = <1>;
1043 i2c4: i2c@01c2c000 {
1044 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1045 reg = <0x01c2c000 0x400>;
1046 interrupts = <0 89 4>;
1047 clocks = <&apb1_gates 15>;
1048 status = "disabled";
1049 #address-cells = <1>;
1053 gmac: ethernet@01c50000 {
1054 compatible = "allwinner,sun7i-a20-gmac";
1055 reg = <0x01c50000 0x10000>;
1056 interrupts = <0 85 4>;
1057 interrupt-names = "macirq";
1058 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1059 clock-names = "stmmaceth", "allwinner_gmac_tx";
1062 snps,force_sf_dma_mode;
1063 status = "disabled";
1064 #address-cells = <1>;
1069 compatible = "allwinner,sun7i-a20-hstimer";
1070 reg = <0x01c60000 0x1000>;
1071 interrupts = <0 81 4>,
1075 clocks = <&ahb_gates 28>;
1078 gic: interrupt-controller@01c81000 {
1079 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1080 reg = <0x01c81000 0x1000>,
1081 <0x01c82000 0x1000>,
1082 <0x01c84000 0x2000>,
1083 <0x01c86000 0x2000>;
1084 interrupt-controller;
1085 #interrupt-cells = <3>;
1086 interrupts = <1 9 0xf04>;