2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
31 enable-method = "allwinner,sun6i-a31";
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
48 compatible = "arm,cortex-a7";
54 compatible = "arm,cortex-a7";
61 reg = <0x40000000 0x80000000>;
65 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
66 interrupts = <0 120 4>,
79 compatible = "fixed-clock";
80 clock-frequency = <24000000>;
85 compatible = "fixed-clock";
86 clock-frequency = <32768>;
87 clock-output-names = "osc32k";
92 compatible = "allwinner,sun6i-a31-pll1-clk";
93 reg = <0x01c20000 0x4>;
95 clock-output-names = "pll1";
100 compatible = "allwinner,sun6i-a31-pll6-clk";
101 reg = <0x01c20028 0x4>;
103 clock-output-names = "pll6";
108 compatible = "allwinner,sun4i-a10-cpu-clk";
109 reg = <0x01c20050 0x4>;
112 * PLL1 is listed twice here.
113 * While it looks suspicious, it's actually documented
114 * that way both in the datasheet and in the code from
117 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
118 clock-output-names = "cpu";
123 compatible = "allwinner,sun4i-a10-axi-clk";
124 reg = <0x01c20050 0x4>;
126 clock-output-names = "axi";
129 ahb1_mux: ahb1_mux@01c20054 {
131 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
132 reg = <0x01c20054 0x4>;
133 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
134 clock-output-names = "ahb1_mux";
137 ahb1: ahb1@01c20054 {
139 compatible = "allwinner,sun4i-a10-ahb-clk";
140 reg = <0x01c20054 0x4>;
141 clocks = <&ahb1_mux>;
142 clock-output-names = "ahb1";
145 ahb1_gates: clk@01c20060 {
147 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
148 reg = <0x01c20060 0x8>;
150 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
151 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
152 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
153 "ahb1_nand0", "ahb1_sdram",
154 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
155 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
156 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
157 "ahb1_ehci1", "ahb1_ohci0",
158 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
159 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
160 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
161 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
162 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
163 "ahb1_drc0", "ahb1_drc1";
166 apb1: apb1@01c20054 {
168 compatible = "allwinner,sun4i-a10-apb0-clk";
169 reg = <0x01c20054 0x4>;
171 clock-output-names = "apb1";
174 apb1_gates: clk@01c20068 {
176 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
177 reg = <0x01c20068 0x4>;
179 clock-output-names = "apb1_codec", "apb1_digital_mic",
180 "apb1_pio", "apb1_daudio0",
184 apb2_mux: apb2_mux@01c20058 {
186 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
187 reg = <0x01c20058 0x4>;
188 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
189 clock-output-names = "apb2_mux";
192 apb2: apb2@01c20058 {
194 compatible = "allwinner,sun6i-a31-apb2-div-clk";
195 reg = <0x01c20058 0x4>;
196 clocks = <&apb2_mux>;
197 clock-output-names = "apb2";
200 apb2_gates: clk@01c2006c {
202 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
203 reg = <0x01c2006c 0x4>;
205 clock-output-names = "apb2_i2c0", "apb2_i2c1",
206 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
207 "apb2_uart1", "apb2_uart2", "apb2_uart3",
208 "apb2_uart4", "apb2_uart5";
211 mmc0_clk: clk@01c20088 {
213 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c20088 0x4>;
215 clocks = <&osc24M>, <&pll6>;
216 clock-output-names = "mmc0";
219 mmc1_clk: clk@01c2008c {
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c2008c 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc1";
227 mmc2_clk: clk@01c20090 {
229 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c20090 0x4>;
231 clocks = <&osc24M>, <&pll6>;
232 clock-output-names = "mmc2";
235 mmc3_clk: clk@01c20094 {
237 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c20094 0x4>;
239 clocks = <&osc24M>, <&pll6>;
240 clock-output-names = "mmc3";
243 spi0_clk: clk@01c200a0 {
245 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6>;
248 clock-output-names = "spi0";
251 spi1_clk: clk@01c200a4 {
253 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6>;
256 clock-output-names = "spi1";
259 spi2_clk: clk@01c200a8 {
261 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6>;
264 clock-output-names = "spi2";
267 spi3_clk: clk@01c200ac {
269 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6>;
272 clock-output-names = "spi3";
275 usb_clk: clk@01c200cc {
278 compatible = "allwinner,sun6i-a31-usb-clk";
279 reg = <0x01c200cc 0x4>;
281 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
282 "usb_ohci0", "usb_ohci1",
287 * The following two are dummy clocks, placeholders used in the gmac_tx
288 * clock. The gmac driver will choose one parent depending on the PHY
289 * interface mode, using clk_set_rate auto-reparenting.
290 * The actual TX clock rate is not controlled by the gmac_tx clock.
292 mii_phy_tx_clk: clk@1 {
294 compatible = "fixed-clock";
295 clock-frequency = <25000000>;
296 clock-output-names = "mii_phy_tx";
299 gmac_int_tx_clk: clk@2 {
301 compatible = "fixed-clock";
302 clock-frequency = <125000000>;
303 clock-output-names = "gmac_int_tx";
306 gmac_tx_clk: clk@01c200d0 {
308 compatible = "allwinner,sun7i-a20-gmac-clk";
309 reg = <0x01c200d0 0x4>;
310 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
311 clock-output-names = "gmac_tx";
316 compatible = "simple-bus";
317 #address-cells = <1>;
321 dma: dma-controller@01c02000 {
322 compatible = "allwinner,sun6i-a31-dma";
323 reg = <0x01c02000 0x1000>;
324 interrupts = <0 50 4>;
325 clocks = <&ahb1_gates 6>;
326 resets = <&ahb1_rst 6>;
331 compatible = "allwinner,sun5i-a13-mmc";
332 reg = <0x01c0f000 0x1000>;
333 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
334 clock-names = "ahb", "mmc";
335 resets = <&ahb1_rst 8>;
337 interrupts = <0 60 4>;
342 compatible = "allwinner,sun5i-a13-mmc";
343 reg = <0x01c10000 0x1000>;
344 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
345 clock-names = "ahb", "mmc";
346 resets = <&ahb1_rst 9>;
348 interrupts = <0 61 4>;
353 compatible = "allwinner,sun5i-a13-mmc";
354 reg = <0x01c11000 0x1000>;
355 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
356 clock-names = "ahb", "mmc";
357 resets = <&ahb1_rst 10>;
359 interrupts = <0 62 4>;
364 compatible = "allwinner,sun5i-a13-mmc";
365 reg = <0x01c12000 0x1000>;
366 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
367 clock-names = "ahb", "mmc";
368 resets = <&ahb1_rst 11>;
370 interrupts = <0 63 4>;
374 usbphy: phy@01c19400 {
375 compatible = "allwinner,sun6i-a31-usb-phy";
376 reg = <0x01c19400 0x10>,
379 reg-names = "phy_ctrl",
382 clocks = <&usb_clk 8>,
385 clock-names = "usb0_phy",
388 resets = <&usb_clk 0>,
391 reset-names = "usb0_reset",
398 ehci0: usb@01c1a000 {
399 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
400 reg = <0x01c1a000 0x100>;
401 interrupts = <0 72 4>;
402 clocks = <&ahb1_gates 26>;
403 resets = <&ahb1_rst 26>;
409 ohci0: usb@01c1a400 {
410 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
411 reg = <0x01c1a400 0x100>;
412 interrupts = <0 73 4>;
413 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
414 resets = <&ahb1_rst 29>;
420 ehci1: usb@01c1b000 {
421 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
422 reg = <0x01c1b000 0x100>;
423 interrupts = <0 74 4>;
424 clocks = <&ahb1_gates 27>;
425 resets = <&ahb1_rst 27>;
431 ohci1: usb@01c1b400 {
432 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
433 reg = <0x01c1b400 0x100>;
434 interrupts = <0 75 4>;
435 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
436 resets = <&ahb1_rst 30>;
442 ohci2: usb@01c1c400 {
443 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
444 reg = <0x01c1c400 0x100>;
445 interrupts = <0 77 4>;
446 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
447 resets = <&ahb1_rst 31>;
451 pio: pinctrl@01c20800 {
452 compatible = "allwinner,sun6i-a31-pinctrl";
453 reg = <0x01c20800 0x400>;
454 interrupts = <0 11 4>,
458 clocks = <&apb1_gates 5>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
465 uart0_pins_a: uart0@0 {
466 allwinner,pins = "PH20", "PH21";
467 allwinner,function = "uart0";
468 allwinner,drive = <0>;
469 allwinner,pull = <0>;
472 i2c0_pins_a: i2c0@0 {
473 allwinner,pins = "PH14", "PH15";
474 allwinner,function = "i2c0";
475 allwinner,drive = <0>;
476 allwinner,pull = <0>;
479 i2c1_pins_a: i2c1@0 {
480 allwinner,pins = "PH16", "PH17";
481 allwinner,function = "i2c1";
482 allwinner,drive = <0>;
483 allwinner,pull = <0>;
486 i2c2_pins_a: i2c2@0 {
487 allwinner,pins = "PH18", "PH19";
488 allwinner,function = "i2c2";
489 allwinner,drive = <0>;
490 allwinner,pull = <0>;
493 mmc0_pins_a: mmc0@0 {
494 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
495 allwinner,function = "mmc0";
496 allwinner,drive = <2>;
497 allwinner,pull = <0>;
500 gmac_pins_mii_a: gmac_mii@0 {
501 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
502 "PA8", "PA9", "PA11",
503 "PA12", "PA13", "PA14", "PA19",
504 "PA20", "PA21", "PA22", "PA23",
505 "PA24", "PA26", "PA27";
506 allwinner,function = "gmac";
507 allwinner,drive = <0>;
508 allwinner,pull = <0>;
511 gmac_pins_gmii_a: gmac_gmii@0 {
512 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
513 "PA4", "PA5", "PA6", "PA7",
514 "PA8", "PA9", "PA10", "PA11",
515 "PA12", "PA13", "PA14", "PA15",
516 "PA16", "PA17", "PA18", "PA19",
517 "PA20", "PA21", "PA22", "PA23",
518 "PA24", "PA25", "PA26", "PA27";
519 allwinner,function = "gmac";
521 * data lines in GMII mode run at 125MHz and
522 * might need a higher signal drive strength
524 allwinner,drive = <2>;
525 allwinner,pull = <0>;
528 gmac_pins_rgmii_a: gmac_rgmii@0 {
529 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
530 "PA9", "PA10", "PA11",
531 "PA12", "PA13", "PA14", "PA19",
532 "PA20", "PA25", "PA26", "PA27";
533 allwinner,function = "gmac";
535 * data lines in RGMII mode use DDR mode
536 * and need a higher signal drive strength
538 allwinner,drive = <3>;
539 allwinner,pull = <0>;
543 ahb1_rst: reset@01c202c0 {
545 compatible = "allwinner,sun6i-a31-ahb1-reset";
546 reg = <0x01c202c0 0xc>;
549 apb1_rst: reset@01c202d0 {
551 compatible = "allwinner,sun6i-a31-clock-reset";
552 reg = <0x01c202d0 0x4>;
555 apb2_rst: reset@01c202d8 {
557 compatible = "allwinner,sun6i-a31-clock-reset";
558 reg = <0x01c202d8 0x4>;
562 compatible = "allwinner,sun4i-a10-timer";
563 reg = <0x01c20c00 0xa0>;
564 interrupts = <0 18 4>,
572 wdt1: watchdog@01c20ca0 {
573 compatible = "allwinner,sun6i-a31-wdt";
574 reg = <0x01c20ca0 0x20>;
577 uart0: serial@01c28000 {
578 compatible = "snps,dw-apb-uart";
579 reg = <0x01c28000 0x400>;
580 interrupts = <0 0 4>;
583 clocks = <&apb2_gates 16>;
584 resets = <&apb2_rst 16>;
585 dmas = <&dma 6>, <&dma 6>;
586 dma-names = "rx", "tx";
590 uart1: serial@01c28400 {
591 compatible = "snps,dw-apb-uart";
592 reg = <0x01c28400 0x400>;
593 interrupts = <0 1 4>;
596 clocks = <&apb2_gates 17>;
597 resets = <&apb2_rst 17>;
598 dmas = <&dma 7>, <&dma 7>;
599 dma-names = "rx", "tx";
603 uart2: serial@01c28800 {
604 compatible = "snps,dw-apb-uart";
605 reg = <0x01c28800 0x400>;
606 interrupts = <0 2 4>;
609 clocks = <&apb2_gates 18>;
610 resets = <&apb2_rst 18>;
611 dmas = <&dma 8>, <&dma 8>;
612 dma-names = "rx", "tx";
616 uart3: serial@01c28c00 {
617 compatible = "snps,dw-apb-uart";
618 reg = <0x01c28c00 0x400>;
619 interrupts = <0 3 4>;
622 clocks = <&apb2_gates 19>;
623 resets = <&apb2_rst 19>;
624 dmas = <&dma 9>, <&dma 9>;
625 dma-names = "rx", "tx";
629 uart4: serial@01c29000 {
630 compatible = "snps,dw-apb-uart";
631 reg = <0x01c29000 0x400>;
632 interrupts = <0 4 4>;
635 clocks = <&apb2_gates 20>;
636 resets = <&apb2_rst 20>;
637 dmas = <&dma 10>, <&dma 10>;
638 dma-names = "rx", "tx";
642 uart5: serial@01c29400 {
643 compatible = "snps,dw-apb-uart";
644 reg = <0x01c29400 0x400>;
645 interrupts = <0 5 4>;
648 clocks = <&apb2_gates 21>;
649 resets = <&apb2_rst 21>;
650 dmas = <&dma 22>, <&dma 22>;
651 dma-names = "rx", "tx";
656 compatible = "allwinner,sun6i-a31-i2c";
657 reg = <0x01c2ac00 0x400>;
658 interrupts = <0 6 4>;
659 clocks = <&apb2_gates 0>;
660 clock-frequency = <100000>;
661 resets = <&apb2_rst 0>;
663 #address-cells = <1>;
668 compatible = "allwinner,sun6i-a31-i2c";
669 reg = <0x01c2b000 0x400>;
670 interrupts = <0 7 4>;
671 clocks = <&apb2_gates 1>;
672 clock-frequency = <100000>;
673 resets = <&apb2_rst 1>;
675 #address-cells = <1>;
680 compatible = "allwinner,sun6i-a31-i2c";
681 reg = <0x01c2b400 0x400>;
682 interrupts = <0 8 4>;
683 clocks = <&apb2_gates 2>;
684 clock-frequency = <100000>;
685 resets = <&apb2_rst 2>;
687 #address-cells = <1>;
692 compatible = "allwinner,sun6i-a31-i2c";
693 reg = <0x01c2b800 0x400>;
694 interrupts = <0 9 4>;
695 clocks = <&apb2_gates 3>;
696 clock-frequency = <100000>;
697 resets = <&apb2_rst 3>;
699 #address-cells = <1>;
703 gmac: ethernet@01c30000 {
704 compatible = "allwinner,sun7i-a20-gmac";
705 reg = <0x01c30000 0x1054>;
706 interrupts = <0 82 4>;
707 interrupt-names = "macirq";
708 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
709 clock-names = "stmmaceth", "allwinner_gmac_tx";
710 resets = <&ahb1_rst 17>;
711 reset-names = "stmmaceth";
714 snps,force_sf_dma_mode;
716 #address-cells = <1>;
721 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
722 reg = <0x01c60000 0x1000>;
723 interrupts = <0 51 4>,
727 clocks = <&ahb1_gates 19>;
728 resets = <&ahb1_rst 19>;
732 compatible = "allwinner,sun6i-a31-spi";
733 reg = <0x01c68000 0x1000>;
734 interrupts = <0 65 4>;
735 clocks = <&ahb1_gates 20>, <&spi0_clk>;
736 clock-names = "ahb", "mod";
737 dmas = <&dma 23>, <&dma 23>;
738 dma-names = "rx", "tx";
739 resets = <&ahb1_rst 20>;
744 compatible = "allwinner,sun6i-a31-spi";
745 reg = <0x01c69000 0x1000>;
746 interrupts = <0 66 4>;
747 clocks = <&ahb1_gates 21>, <&spi1_clk>;
748 clock-names = "ahb", "mod";
749 dmas = <&dma 24>, <&dma 24>;
750 dma-names = "rx", "tx";
751 resets = <&ahb1_rst 21>;
756 compatible = "allwinner,sun6i-a31-spi";
757 reg = <0x01c6a000 0x1000>;
758 interrupts = <0 67 4>;
759 clocks = <&ahb1_gates 22>, <&spi2_clk>;
760 clock-names = "ahb", "mod";
761 dmas = <&dma 25>, <&dma 25>;
762 dma-names = "rx", "tx";
763 resets = <&ahb1_rst 22>;
768 compatible = "allwinner,sun6i-a31-spi";
769 reg = <0x01c6b000 0x1000>;
770 interrupts = <0 68 4>;
771 clocks = <&ahb1_gates 23>, <&spi3_clk>;
772 clock-names = "ahb", "mod";
773 dmas = <&dma 26>, <&dma 26>;
774 dma-names = "rx", "tx";
775 resets = <&ahb1_rst 23>;
779 gic: interrupt-controller@01c81000 {
780 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
781 reg = <0x01c81000 0x1000>,
785 interrupt-controller;
786 #interrupt-cells = <3>;
787 interrupts = <1 9 0xf04>;
790 nmi_intc: interrupt-controller@01f00c0c {
791 compatible = "allwinner,sun6i-a31-sc-nmi";
792 interrupt-controller;
793 #interrupt-cells = <2>;
794 reg = <0x01f00c0c 0x38>;
795 interrupts = <0 32 4>;
799 compatible = "allwinner,sun6i-a31-prcm";
800 reg = <0x01f01400 0x200>;
803 compatible = "allwinner,sun6i-a31-ar100-clk";
805 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
806 clock-output-names = "ar100";
810 compatible = "fixed-factor-clock";
815 clock-output-names = "ahb0";
819 compatible = "allwinner,sun6i-a31-apb0-clk";
822 clock-output-names = "apb0";
825 apb0_gates: apb0_gates_clk {
826 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
829 clock-output-names = "apb0_pio", "apb0_ir",
830 "apb0_timer", "apb0_p2wi",
831 "apb0_uart", "apb0_1wire",
836 compatible = "allwinner,sun6i-a31-clock-reset";
842 compatible = "allwinner,sun6i-a31-cpuconfig";
843 reg = <0x01f01c00 0x300>;
846 r_pio: pinctrl@01f02c00 {
847 compatible = "allwinner,sun6i-a31-r-pinctrl";
848 reg = <0x01f02c00 0x400>;
849 interrupts = <0 45 4>,
851 clocks = <&apb0_gates 0>;
852 resets = <&apb0_rst 0>;
854 interrupt-controller;
855 #interrupt-cells = <2>;