arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/pinctrl/sun4i-a10.h>
  49
  50 / {
  51         interrupt-parent = <&intc>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a8";
  60                         reg = <0x0>;
  61                         clocks = <&cpu>;
  62                 };
  63         };
  64
  65         clocks {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges;
  69
  70                 /*
  71                  * This is a dummy clock, to be used as placeholder on
  72                  * other mux clocks when a specific parent clock is not
  73                  * yet implemented. It should be dropped when the driver
  74                  * is complete.
  75                  */
  76                 dummy: dummy {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <0>;
  80                 };
  81
  82                 osc24M: clk@01c20050 {
  83                         #clock-cells = <0>;
  84                         compatible = "allwinner,sun4i-a10-osc-clk";
  85                         reg = <0x01c20050 0x4>;
  86                         clock-frequency = <24000000>;
  87                         clock-output-names = "osc24M";
  88                 };
  89
  90                 osc32k: clk@0 {
  91                         #clock-cells = <0>;
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <32768>;
  94                         clock-output-names = "osc32k";
  95                 };
  96
  97                 pll1: clk@01c20000 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun4i-a10-pll1-clk";
 100                         reg = <0x01c20000 0x4>;
 101                         clocks = <&osc24M>;
 102                         clock-output-names = "pll1";
 103                 };
 104
 105                 pll4: clk@01c20018 {
 106                         #clock-cells = <0>;
 107                         compatible = "allwinner,sun4i-a10-pll1-clk";
 108                         reg = <0x01c20018 0x4>;
 109                         clocks = <&osc24M>;
 110                         clock-output-names = "pll4";
 111                 };
 112
 113                 pll5: clk@01c20020 {
 114                         #clock-cells = <1>;
 115                         compatible = "allwinner,sun4i-a10-pll5-clk";
 116                         reg = <0x01c20020 0x4>;
 117                         clocks = <&osc24M>;
 118                         clock-output-names = "pll5_ddr", "pll5_other";
 119                 };
 120
 121                 pll6: clk@01c20028 {
 122                         #clock-cells = <1>;
 123                         compatible = "allwinner,sun4i-a10-pll6-clk";
 124                         reg = <0x01c20028 0x4>;
 125                         clocks = <&osc24M>;
 126                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 127                 };
 128
 129                 /* dummy is 200M */
 130                 cpu: cpu@01c20054 {
 131                         #clock-cells = <0>;
 132                         compatible = "allwinner,sun4i-a10-cpu-clk";
 133                         reg = <0x01c20054 0x4>;
 134                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 135                         clock-output-names = "cpu";
 136                 };
 137
 138                 axi: axi@01c20054 {
 139                         #clock-cells = <0>;
 140                         compatible = "allwinner,sun4i-a10-axi-clk";
 141                         reg = <0x01c20054 0x4>;
 142                         clocks = <&cpu>;
 143                         clock-output-names = "axi";
 144                 };
 145
 146                 ahb: ahb@01c20054 {
 147                         #clock-cells = <0>;
 148                         compatible = "allwinner,sun5i-a13-ahb-clk";
 149                         reg = <0x01c20054 0x4>;
 150                         clocks = <&axi>, <&cpu>, <&pll6 1>;
 151                         clock-output-names = "ahb";
 152                         /*
 153                          * Use PLL6 as parent, instead of CPU/AXI
 154                          * which has rate changes due to cpufreq
 155                          */
 156                         assigned-clocks = <&ahb>;
 157                         assigned-clock-parents = <&pll6 1>;
 158                 };
 159
 160                 apb0: apb0@01c20054 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-a10-apb0-clk";
 163                         reg = <0x01c20054 0x4>;
 164                         clocks = <&ahb>;
 165                         clock-output-names = "apb0";
 166                 };
 167
 168                 apb1: clk@01c20058 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun4i-a10-apb1-clk";
 171                         reg = <0x01c20058 0x4>;
 172                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 173                         clock-output-names = "apb1";
 174                 };
 175
 176                 axi_gates: clk@01c2005c {
 177                         #clock-cells = <1>;
 178                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 179                         reg = <0x01c2005c 0x4>;
 180                         clocks = <&axi>;
 181                         clock-output-names = "axi_dram";
 182                 };
 183
 184                 nand_clk: clk@01c20080 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-mod0-clk";
 187                         reg = <0x01c20080 0x4>;
 188                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 189                         clock-output-names = "nand";
 190                 };
 191
 192                 ms_clk: clk@01c20084 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-mod0-clk";
 195                         reg = <0x01c20084 0x4>;
 196                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 197                         clock-output-names = "ms";
 198                 };
 199
 200                 mmc0_clk: clk@01c20088 {
 201                         #clock-cells = <1>;
 202                         compatible = "allwinner,sun4i-a10-mmc-clk";
 203                         reg = <0x01c20088 0x4>;
 204                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 205                         clock-output-names = "mmc0",
 206                                              "mmc0_output",
 207                                              "mmc0_sample";
 208                 };
 209
 210                 mmc1_clk: clk@01c2008c {
 211                         #clock-cells = <1>;
 212                         compatible = "allwinner,sun4i-a10-mmc-clk";
 213                         reg = <0x01c2008c 0x4>;
 214                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 215                         clock-output-names = "mmc1",
 216                                              "mmc1_output",
 217                                              "mmc1_sample";
 218                 };
 219
 220                 mmc2_clk: clk@01c20090 {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun4i-a10-mmc-clk";
 223                         reg = <0x01c20090 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc2",
 226                                              "mmc2_output",
 227                                              "mmc2_sample";
 228                 };
 229
 230                 ts_clk: clk@01c20098 {
 231                         #clock-cells = <0>;
 232                         compatible = "allwinner,sun4i-a10-mod0-clk";
 233                         reg = <0x01c20098 0x4>;
 234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 235                         clock-output-names = "ts";
 236                 };
 237
 238                 ss_clk: clk@01c2009c {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun4i-a10-mod0-clk";
 241                         reg = <0x01c2009c 0x4>;
 242                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 243                         clock-output-names = "ss";
 244                 };
 245
 246                 spi0_clk: clk@01c200a0 {
 247                         #clock-cells = <0>;
 248                         compatible = "allwinner,sun4i-a10-mod0-clk";
 249                         reg = <0x01c200a0 0x4>;
 250                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 251                         clock-output-names = "spi0";
 252                 };
 253
 254                 spi1_clk: clk@01c200a4 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun4i-a10-mod0-clk";
 257                         reg = <0x01c200a4 0x4>;
 258                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 259                         clock-output-names = "spi1";
 260                 };
 261
 262                 spi2_clk: clk@01c200a8 {
 263                         #clock-cells = <0>;
 264                         compatible = "allwinner,sun4i-a10-mod0-clk";
 265                         reg = <0x01c200a8 0x4>;
 266                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 267                         clock-output-names = "spi2";
 268                 };
 269
 270                 ir0_clk: clk@01c200b0 {
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-a10-mod0-clk";
 273                         reg = <0x01c200b0 0x4>;
 274                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 275                         clock-output-names = "ir0";
 276                 };
 277
 278                 usb_clk: clk@01c200cc {
 279                         #clock-cells = <1>;
 280                         #reset-cells = <1>;
 281                         compatible = "allwinner,sun5i-a13-usb-clk";
 282                         reg = <0x01c200cc 0x4>;
 283                         clocks = <&pll6 1>;
 284                         clock-output-names = "usb_ohci0", "usb_phy";
 285                 };
 286
 287                 mbus_clk: clk@01c2015c {
 288                         #clock-cells = <0>;
 289                         compatible = "allwinner,sun5i-a13-mbus-clk";
 290                         reg = <0x01c2015c 0x4>;
 291                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 292                         clock-output-names = "mbus";
 293                 };
 294         };
 295
 296         /*
 297          * Note we use the address where the mmio registers start, not where
 298          * the SRAM blocks start, this cannot be changed because that would be
 299          * a devicetree ABI change.
 300          */
 301         soc@01c00000 {
 302                 compatible = "simple-bus";
 303                 #address-cells = <1>;
 304                 #size-cells = <1>;
 305                 ranges;
 306
 307                 sram@00000000 {
 308                         compatible = "allwinner,sun4i-a10-sram";
 309                         reg = <0x00000000 0x4000>;
 310                         allwinner,sram-name = "A1";
 311                 };
 312
 313                 sram@00004000 {
 314                         compatible = "allwinner,sun4i-a10-sram";
 315                         reg = <0x00004000 0x4000>;
 316                         allwinner,sram-name = "A2";
 317                 };
 318
 319                 sram@00008000 {
 320                         compatible = "allwinner,sun4i-a10-sram";
 321                         reg = <0x00008000 0x4000>;
 322                         allwinner,sram-name = "A3-A4";
 323                 };
 324
 325                 sram@00010000 {
 326                         compatible = "allwinner,sun4i-a10-sram";
 327                         reg = <0x00010000 0x1000>;
 328                         allwinner,sram-name = "D";
 329                 };
 330
 331                 sram-controller@01c00000 {
 332                         compatible = "allwinner,sun4i-a10-sram-controller";
 333                         reg = <0x01c00000 0x30>;
 334                 };
 335
 336                 dma: dma-controller@01c02000 {
 337                         compatible = "allwinner,sun4i-a10-dma";
 338                         reg = <0x01c02000 0x1000>;
 339                         interrupts = <27>;
 340                         clocks = <&ahb_gates 6>;
 341                         #dma-cells = <2>;
 342                 };
 343
 344                 spi0: spi@01c05000 {
 345                         compatible = "allwinner,sun4i-a10-spi";
 346                         reg = <0x01c05000 0x1000>;
 347                         interrupts = <10>;
 348                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 349                         clock-names = "ahb", "mod";
 350                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 351                                <&dma SUN4I_DMA_DEDICATED 26>;
 352                         dma-names = "rx", "tx";
 353                         status = "disabled";
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                 };
 357
 358                 spi1: spi@01c06000 {
 359                         compatible = "allwinner,sun4i-a10-spi";
 360                         reg = <0x01c06000 0x1000>;
 361                         interrupts = <11>;
 362                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 363                         clock-names = "ahb", "mod";
 364                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 365                                <&dma SUN4I_DMA_DEDICATED 8>;
 366                         dma-names = "rx", "tx";
 367                         status = "disabled";
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                 };
 371
 372                 mmc0: mmc@01c0f000 {
 373                         compatible = "allwinner,sun5i-a13-mmc";
 374                         reg = <0x01c0f000 0x1000>;
 375                         clocks = <&ahb_gates 8>,
 376                                  <&mmc0_clk 0>,
 377                                  <&mmc0_clk 1>,
 378                                  <&mmc0_clk 2>;
 379                         clock-names = "ahb",
 380                                       "mmc",
 381                                       "output",
 382                                       "sample";
 383                         interrupts = <32>;
 384                         status = "disabled";
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                 };
 388
 389                 mmc1: mmc@01c10000 {
 390                         compatible = "allwinner,sun5i-a13-mmc";
 391                         reg = <0x01c10000 0x1000>;
 392                         clocks = <&ahb_gates 9>,
 393                                  <&mmc1_clk 0>,
 394                                  <&mmc1_clk 1>,
 395                                  <&mmc1_clk 2>;
 396                         clock-names = "ahb",
 397                                       "mmc",
 398                                       "output",
 399                                       "sample";
 400                         interrupts = <33>;
 401                         status = "disabled";
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                 };
 405
 406                 mmc2: mmc@01c11000 {
 407                         compatible = "allwinner,sun5i-a13-mmc";
 408                         reg = <0x01c11000 0x1000>;
 409                         clocks = <&ahb_gates 10>,
 410                                  <&mmc2_clk 0>,
 411                                  <&mmc2_clk 1>,
 412                                  <&mmc2_clk 2>;
 413                         clock-names = "ahb",
 414                                       "mmc",
 415                                       "output",
 416                                       "sample";
 417                         interrupts = <34>;
 418                         status = "disabled";
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                 };
 422
 423                 usbphy: phy@01c13400 {
 424                         #phy-cells = <1>;
 425                         compatible = "allwinner,sun5i-a13-usb-phy";
 426                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 427                         reg-names = "phy_ctrl", "pmu1";
 428                         clocks = <&usb_clk 8>;
 429                         clock-names = "usb_phy";
 430                         resets = <&usb_clk 0>, <&usb_clk 1>;
 431                         reset-names = "usb0_reset", "usb1_reset";
 432                         status = "disabled";
 433                 };
 434
 435                 ehci0: usb@01c14000 {
 436                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 437                         reg = <0x01c14000 0x100>;
 438                         interrupts = <39>;
 439                         clocks = <&ahb_gates 1>;
 440                         phys = <&usbphy 1>;
 441                         phy-names = "usb";
 442                         status = "disabled";
 443                 };
 444
 445                 ohci0: usb@01c14400 {
 446                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 447                         reg = <0x01c14400 0x100>;
 448                         interrupts = <40>;
 449                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 450                         phys = <&usbphy 1>;
 451                         phy-names = "usb";
 452                         status = "disabled";
 453                 };
 454
 455                 spi2: spi@01c17000 {
 456                         compatible = "allwinner,sun4i-a10-spi";
 457                         reg = <0x01c17000 0x1000>;
 458                         interrupts = <12>;
 459                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 460                         clock-names = "ahb", "mod";
 461                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 462                                <&dma SUN4I_DMA_DEDICATED 28>;
 463                         dma-names = "rx", "tx";
 464                         status = "disabled";
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                 };
 468
 469                 intc: interrupt-controller@01c20400 {
 470                         compatible = "allwinner,sun4i-a10-ic";
 471                         reg = <0x01c20400 0x400>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <1>;
 474                 };
 475
 476                 pio: pinctrl@01c20800 {
 477                         reg = <0x01c20800 0x400>;
 478                         interrupts = <28>;
 479                         clocks = <&apb0_gates 5>;
 480                         gpio-controller;
 481                         interrupt-controller;
 482                         #interrupt-cells = <2>;
 483                         #size-cells = <0>;
 484                         #gpio-cells = <3>;
 485
 486                         i2c0_pins_a: i2c0@0 {
 487                                 allwinner,pins = "PB0", "PB1";
 488                                 allwinner,function = "i2c0";
 489                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 490                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 491                         };
 492
 493                         i2c1_pins_a: i2c1@0 {
 494                                 allwinner,pins = "PB15", "PB16";
 495                                 allwinner,function = "i2c1";
 496                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 497                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 498                         };
 499
 500                         i2c2_pins_a: i2c2@0 {
 501                                 allwinner,pins = "PB17", "PB18";
 502                                 allwinner,function = "i2c2";
 503                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 504                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 505                         };
 506
 507                         mmc0_pins_a: mmc0@0 {
 508                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 509                                                  "PF4", "PF5";
 510                                 allwinner,function = "mmc0";
 511                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 512                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 513                         };
 514
 515                         mmc2_pins_a: mmc2@0 {
 516                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 517                                         "PC10", "PC11", "PC12", "PC13",
 518                                         "PC14", "PC15";
 519                                 allwinner,function = "mmc2";
 520                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 521                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 522                         };
 523                 };
 524
 525                 timer@01c20c00 {
 526                         compatible = "allwinner,sun4i-a10-timer";
 527                         reg = <0x01c20c00 0x90>;
 528                         interrupts = <22>;
 529                         clocks = <&osc24M>;
 530                 };
 531
 532                 wdt: watchdog@01c20c90 {
 533                         compatible = "allwinner,sun4i-a10-wdt";
 534                         reg = <0x01c20c90 0x10>;
 535                 };
 536
 537                 lradc: lradc@01c22800 {
 538                         compatible = "allwinner,sun4i-a10-lradc-keys";
 539                         reg = <0x01c22800 0x100>;
 540                         interrupts = <31>;
 541                         status = "disabled";
 542                 };
 543
 544                 sid: eeprom@01c23800 {
 545                         compatible = "allwinner,sun4i-a10-sid";
 546                         reg = <0x01c23800 0x10>;
 547                 };
 548
 549                 rtp: rtp@01c25000 {
 550                         compatible = "allwinner,sun5i-a13-ts";
 551                         reg = <0x01c25000 0x100>;
 552                         interrupts = <29>;
 553                         #thermal-sensor-cells = <0>;
 554                 };
 555
 556                 uart1: serial@01c28400 {
 557                         compatible = "snps,dw-apb-uart";
 558                         reg = <0x01c28400 0x400>;
 559                         interrupts = <2>;
 560                         reg-shift = <2>;
 561                         reg-io-width = <4>;
 562                         clocks = <&apb1_gates 17>;
 563                         status = "disabled";
 564                 };
 565
 566                 uart3: serial@01c28c00 {
 567                         compatible = "snps,dw-apb-uart";
 568                         reg = <0x01c28c00 0x400>;
 569                         interrupts = <4>;
 570                         reg-shift = <2>;
 571                         reg-io-width = <4>;
 572                         clocks = <&apb1_gates 19>;
 573                         status = "disabled";
 574                 };
 575
 576                 i2c0: i2c@01c2ac00 {
 577                         compatible = "allwinner,sun4i-a10-i2c";
 578                         reg = <0x01c2ac00 0x400>;
 579                         interrupts = <7>;
 580                         clocks = <&apb1_gates 0>;
 581                         status = "disabled";
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                 };
 585
 586                 i2c1: i2c@01c2b000 {
 587                         compatible = "allwinner,sun4i-a10-i2c";
 588                         reg = <0x01c2b000 0x400>;
 589                         interrupts = <8>;
 590                         clocks = <&apb1_gates 1>;
 591                         status = "disabled";
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                 };
 595
 596                 i2c2: i2c@01c2b400 {
 597                         compatible = "allwinner,sun4i-a10-i2c";
 598                         reg = <0x01c2b400 0x400>;
 599                         interrupts = <9>;
 600                         clocks = <&apb1_gates 2>;
 601                         status = "disabled";
 602                         #address-cells = <1>;
 603                         #size-cells = <0>;
 604                 };
 605
 606                 timer@01c60000 {
 607                         compatible = "allwinner,sun5i-a13-hstimer";
 608                         reg = <0x01c60000 0x1000>;
 609                         interrupts = <82>, <83>;
 610                         clocks = <&ahb_gates 28>;
 611                 };
 612         };
 613 };