2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
16 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/dma/sun4i-a10.h>
19 #include <dt-bindings/pinctrl/sun4i-a10.h>
22 interrupt-parent = <&intc>;
30 compatible = "allwinner,simple-framebuffer",
32 allwinner,pipeline = "de_be0-lcd0";
33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
44 compatible = "arm,cortex-a8";
47 clock-latency = <244144>; /* 8 32k periods */
58 cooling-min-level = <0>;
59 cooling-max-level = <5>;
66 polling-delay-passive = <250>;
67 polling-delay = <1000>;
68 thermal-sensors = <&rtp>;
73 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
78 cpu_alert0: cpu_alert0 {
80 temperature = <850000>;
87 temperature = <100000>;
96 reg = <0x40000000 0x20000000>;
100 #address-cells = <1>;
105 * This is a dummy clock, to be used as placeholder on
106 * other mux clocks when a specific parent clock is not
107 * yet implemented. It should be dropped when the driver
112 compatible = "fixed-clock";
113 clock-frequency = <0>;
116 osc24M: clk@01c20050 {
118 compatible = "allwinner,sun4i-a10-osc-clk";
119 reg = <0x01c20050 0x4>;
120 clock-frequency = <24000000>;
121 clock-output-names = "osc24M";
126 compatible = "fixed-clock";
127 clock-frequency = <32768>;
128 clock-output-names = "osc32k";
133 compatible = "allwinner,sun4i-a10-pll1-clk";
134 reg = <0x01c20000 0x4>;
136 clock-output-names = "pll1";
141 compatible = "allwinner,sun4i-a10-pll1-clk";
142 reg = <0x01c20018 0x4>;
144 clock-output-names = "pll4";
149 compatible = "allwinner,sun4i-a10-pll5-clk";
150 reg = <0x01c20020 0x4>;
152 clock-output-names = "pll5_ddr", "pll5_other";
157 compatible = "allwinner,sun4i-a10-pll6-clk";
158 reg = <0x01c20028 0x4>;
160 clock-output-names = "pll6_sata", "pll6_other", "pll6";
166 compatible = "allwinner,sun4i-a10-cpu-clk";
167 reg = <0x01c20054 0x4>;
168 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
169 clock-output-names = "cpu";
174 compatible = "allwinner,sun4i-a10-axi-clk";
175 reg = <0x01c20054 0x4>;
177 clock-output-names = "axi";
180 axi_gates: clk@01c2005c {
182 compatible = "allwinner,sun4i-a10-axi-gates-clk";
183 reg = <0x01c2005c 0x4>;
185 clock-output-names = "axi_dram";
190 compatible = "allwinner,sun4i-a10-ahb-clk";
191 reg = <0x01c20054 0x4>;
193 clock-output-names = "ahb";
196 ahb_gates: clk@01c20060 {
198 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
199 reg = <0x01c20060 0x8>;
201 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
202 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
203 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
204 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
205 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
206 "ahb_de_fe", "ahb_iep", "ahb_mali400";
209 apb0: apb0@01c20054 {
211 compatible = "allwinner,sun4i-a10-apb0-clk";
212 reg = <0x01c20054 0x4>;
214 clock-output-names = "apb0";
217 apb0_gates: clk@01c20068 {
219 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
220 reg = <0x01c20068 0x4>;
222 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
227 compatible = "allwinner,sun4i-a10-apb1-clk";
228 reg = <0x01c20058 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
230 clock-output-names = "apb1";
233 apb1_gates: clk@01c2006c {
235 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
236 reg = <0x01c2006c 0x4>;
238 clock-output-names = "apb1_i2c0", "apb1_i2c1",
239 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
242 nand_clk: clk@01c20080 {
244 compatible = "allwinner,sun4i-a10-mod0-clk";
245 reg = <0x01c20080 0x4>;
246 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
247 clock-output-names = "nand";
250 ms_clk: clk@01c20084 {
252 compatible = "allwinner,sun4i-a10-mod0-clk";
253 reg = <0x01c20084 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "ms";
258 mmc0_clk: clk@01c20088 {
260 compatible = "allwinner,sun4i-a10-mmc-clk";
261 reg = <0x01c20088 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
263 clock-output-names = "mmc0",
268 mmc1_clk: clk@01c2008c {
270 compatible = "allwinner,sun4i-a10-mmc-clk";
271 reg = <0x01c2008c 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "mmc1",
278 mmc2_clk: clk@01c20090 {
280 compatible = "allwinner,sun4i-a10-mmc-clk";
281 reg = <0x01c20090 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "mmc2",
288 ts_clk: clk@01c20098 {
290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c20098 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "ts";
296 ss_clk: clk@01c2009c {
298 compatible = "allwinner,sun4i-a10-mod0-clk";
299 reg = <0x01c2009c 0x4>;
300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clock-output-names = "ss";
304 spi0_clk: clk@01c200a0 {
306 compatible = "allwinner,sun4i-a10-mod0-clk";
307 reg = <0x01c200a0 0x4>;
308 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
309 clock-output-names = "spi0";
312 spi1_clk: clk@01c200a4 {
314 compatible = "allwinner,sun4i-a10-mod0-clk";
315 reg = <0x01c200a4 0x4>;
316 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
317 clock-output-names = "spi1";
320 spi2_clk: clk@01c200a8 {
322 compatible = "allwinner,sun4i-a10-mod0-clk";
323 reg = <0x01c200a8 0x4>;
324 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
325 clock-output-names = "spi2";
328 ir0_clk: clk@01c200b0 {
330 compatible = "allwinner,sun4i-a10-mod0-clk";
331 reg = <0x01c200b0 0x4>;
332 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
333 clock-output-names = "ir0";
336 usb_clk: clk@01c200cc {
339 compatible = "allwinner,sun5i-a13-usb-clk";
340 reg = <0x01c200cc 0x4>;
342 clock-output-names = "usb_ohci0", "usb_phy";
345 mbus_clk: clk@01c2015c {
347 compatible = "allwinner,sun5i-a13-mbus-clk";
348 reg = <0x01c2015c 0x4>;
349 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
350 clock-output-names = "mbus";
355 compatible = "simple-bus";
356 #address-cells = <1>;
360 dma: dma-controller@01c02000 {
361 compatible = "allwinner,sun4i-a10-dma";
362 reg = <0x01c02000 0x1000>;
364 clocks = <&ahb_gates 6>;
369 compatible = "allwinner,sun4i-a10-spi";
370 reg = <0x01c05000 0x1000>;
372 clocks = <&ahb_gates 20>, <&spi0_clk>;
373 clock-names = "ahb", "mod";
374 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
375 <&dma SUN4I_DMA_DEDICATED 26>;
376 dma-names = "rx", "tx";
378 #address-cells = <1>;
383 compatible = "allwinner,sun4i-a10-spi";
384 reg = <0x01c06000 0x1000>;
386 clocks = <&ahb_gates 21>, <&spi1_clk>;
387 clock-names = "ahb", "mod";
388 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
389 <&dma SUN4I_DMA_DEDICATED 8>;
390 dma-names = "rx", "tx";
392 #address-cells = <1>;
397 compatible = "allwinner,sun5i-a13-mmc";
398 reg = <0x01c0f000 0x1000>;
399 clocks = <&ahb_gates 8>,
412 compatible = "allwinner,sun5i-a13-mmc";
413 reg = <0x01c11000 0x1000>;
414 clocks = <&ahb_gates 10>,
426 usbphy: phy@01c13400 {
428 compatible = "allwinner,sun5i-a13-usb-phy";
429 reg = <0x01c13400 0x10 0x01c14800 0x4>;
430 reg-names = "phy_ctrl", "pmu1";
431 clocks = <&usb_clk 8>;
432 clock-names = "usb_phy";
433 resets = <&usb_clk 0>, <&usb_clk 1>;
434 reset-names = "usb0_reset", "usb1_reset";
438 ehci0: usb@01c14000 {
439 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
440 reg = <0x01c14000 0x100>;
442 clocks = <&ahb_gates 1>;
448 ohci0: usb@01c14400 {
449 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
450 reg = <0x01c14400 0x100>;
452 clocks = <&usb_clk 6>, <&ahb_gates 2>;
459 compatible = "allwinner,sun4i-a10-spi";
460 reg = <0x01c17000 0x1000>;
462 clocks = <&ahb_gates 22>, <&spi2_clk>;
463 clock-names = "ahb", "mod";
464 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
465 <&dma SUN4I_DMA_DEDICATED 28>;
466 dma-names = "rx", "tx";
468 #address-cells = <1>;
472 intc: interrupt-controller@01c20400 {
473 compatible = "allwinner,sun4i-a10-ic";
474 reg = <0x01c20400 0x400>;
475 interrupt-controller;
476 #interrupt-cells = <1>;
479 pio: pinctrl@01c20800 {
480 compatible = "allwinner,sun5i-a13-pinctrl";
481 reg = <0x01c20800 0x400>;
483 clocks = <&apb0_gates 5>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
490 uart1_pins_a: uart1@0 {
491 allwinner,pins = "PE10", "PE11";
492 allwinner,function = "uart1";
493 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
494 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
497 uart1_pins_b: uart1@1 {
498 allwinner,pins = "PG3", "PG4";
499 allwinner,function = "uart1";
500 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
501 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
504 i2c0_pins_a: i2c0@0 {
505 allwinner,pins = "PB0", "PB1";
506 allwinner,function = "i2c0";
507 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
508 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
511 i2c1_pins_a: i2c1@0 {
512 allwinner,pins = "PB15", "PB16";
513 allwinner,function = "i2c1";
514 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
515 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
518 i2c2_pins_a: i2c2@0 {
519 allwinner,pins = "PB17", "PB18";
520 allwinner,function = "i2c2";
521 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
522 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
525 mmc0_pins_a: mmc0@0 {
526 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
527 allwinner,function = "mmc0";
528 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
529 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
534 compatible = "allwinner,sun4i-a10-timer";
535 reg = <0x01c20c00 0x90>;
540 wdt: watchdog@01c20c90 {
541 compatible = "allwinner,sun4i-a10-wdt";
542 reg = <0x01c20c90 0x10>;
545 lradc: lradc@01c22800 {
546 compatible = "allwinner,sun4i-a10-lradc-keys";
547 reg = <0x01c22800 0x100>;
552 sid: eeprom@01c23800 {
553 compatible = "allwinner,sun4i-a10-sid";
554 reg = <0x01c23800 0x10>;
558 compatible = "allwinner,sun4i-a10-ts";
559 reg = <0x01c25000 0x100>;
561 #thermal-sensor-cells = <0>;
564 uart1: serial@01c28400 {
565 compatible = "snps,dw-apb-uart";
566 reg = <0x01c28400 0x400>;
570 clocks = <&apb1_gates 17>;
574 uart3: serial@01c28c00 {
575 compatible = "snps,dw-apb-uart";
576 reg = <0x01c28c00 0x400>;
580 clocks = <&apb1_gates 19>;
585 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
586 reg = <0x01c2ac00 0x400>;
588 clocks = <&apb1_gates 0>;
590 #address-cells = <1>;
595 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
596 reg = <0x01c2b000 0x400>;
598 clocks = <&apb1_gates 1>;
600 #address-cells = <1>;
605 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
606 reg = <0x01c2b400 0x400>;
608 clocks = <&apb1_gates 2>;
610 #address-cells = <1>;
615 compatible = "allwinner,sun5i-a13-hstimer";
616 reg = <0x01c60000 0x1000>;
617 interrupts = <82>, <83>;
618 clocks = <&ahb_gates 28>;