arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a8";
  25                         reg = <0x0>;
  26                 };
  27         };
  28
  29         memory {
  30                 reg = <0x40000000 0x20000000>;
  31         };
  32
  33         clocks {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 /*
  39                  * This is a dummy clock, to be used as placeholder on
  40                  * other mux clocks when a specific parent clock is not
  41                  * yet implemented. It should be dropped when the driver
  42                  * is complete.
  43                  */
  44                 dummy: dummy {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <0>;
  48                 };
  49
  50                 osc24M: osc24M@01c20050 {
  51                         #clock-cells = <0>;
  52                         compatible = "allwinner,sun4i-osc-clk";
  53                         reg = <0x01c20050 0x4>;
  54                         clock-frequency = <24000000>;
  55                 };
  56
  57                 osc32k: osc32k {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 pll1: pll1@01c20000 {
  64                         #clock-cells = <0>;
  65                         compatible = "allwinner,sun4i-pll1-clk";
  66                         reg = <0x01c20000 0x4>;
  67                         clocks = <&osc24M>;
  68                 };
  69
  70                 /* dummy is 200M */
  71                 cpu: cpu@01c20054 {
  72                         #clock-cells = <0>;
  73                         compatible = "allwinner,sun4i-cpu-clk";
  74                         reg = <0x01c20054 0x4>;
  75                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  76                 };
  77
  78                 axi: axi@01c20054 {
  79                         #clock-cells = <0>;
  80                         compatible = "allwinner,sun4i-axi-clk";
  81                         reg = <0x01c20054 0x4>;
  82                         clocks = <&cpu>;
  83                 };
  84
  85                 axi_gates: axi_gates@01c2005c {
  86                         #clock-cells = <1>;
  87                         compatible = "allwinner,sun4i-axi-gates-clk";
  88                         reg = <0x01c2005c 0x4>;
  89                         clocks = <&axi>;
  90                         clock-output-names = "axi_dram";
  91                 };
  92
  93                 ahb: ahb@01c20054 {
  94                         #clock-cells = <0>;
  95                         compatible = "allwinner,sun4i-ahb-clk";
  96                         reg = <0x01c20054 0x4>;
  97                         clocks = <&axi>;
  98                 };
  99
 100                 ahb_gates: ahb_gates@01c20060 {
 101                         #clock-cells = <1>;
 102                         compatible = "allwinner,sun4i-ahb-gates-clk";
 103                         reg = <0x01c20060 0x8>;
 104                         clocks = <&ahb>;
 105                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 106                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 107                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 108                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 109                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 110                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 111                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 112                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 113                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 114                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 115                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 116                 };
 117
 118                 apb0: apb0@01c20054 {
 119                         #clock-cells = <0>;
 120                         compatible = "allwinner,sun4i-apb0-clk";
 121                         reg = <0x01c20054 0x4>;
 122                         clocks = <&ahb>;
 123                 };
 124
 125                 apb0_gates: apb0_gates@01c20068 {
 126                         #clock-cells = <1>;
 127                         compatible = "allwinner,sun4i-apb0-gates-clk";
 128                         reg = <0x01c20068 0x4>;
 129                         clocks = <&apb0>;
 130                         clock-output-names = "apb0_codec", "apb0_spdif",
 131                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 132                                 "apb0_ir1", "apb0_keypad";
 133                 };
 134
 135                 /* dummy is pll62 */
 136                 apb1_mux: apb1_mux@01c20058 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-apb1-mux-clk";
 139                         reg = <0x01c20058 0x4>;
 140                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 141                 };
 142
 143                 apb1: apb1@01c20058 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-apb1-clk";
 146                         reg = <0x01c20058 0x4>;
 147                         clocks = <&apb1_mux>;
 148                 };
 149
 150                 apb1_gates: apb1_gates@01c2006c {
 151                         #clock-cells = <1>;
 152                         compatible = "allwinner,sun4i-apb1-gates-clk";
 153                         reg = <0x01c2006c 0x4>;
 154                         clocks = <&apb1>;
 155                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 156                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 157                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 158                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 159                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 160                                 "apb1_uart7";
 161                 };
 162         };
 163
 164         soc@01c20000 {
 165                 compatible = "simple-bus";
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 reg = <0x01c20000 0x300000>;
 169                 ranges;
 170
 171                 intc: interrupt-controller@01c20400 {
 172                         compatible = "allwinner,sun4i-ic";
 173                         reg = <0x01c20400 0x400>;
 174                         interrupt-controller;
 175                         #interrupt-cells = <1>;
 176                 };
 177
 178                 pio: pinctrl@01c20800 {
 179                         compatible = "allwinner,sun5i-a13-pinctrl";
 180                         reg = <0x01c20800 0x400>;
 181                         clocks = <&apb0_gates 5>;
 182                         gpio-controller;
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         #gpio-cells = <3>;
 186
 187                         uart1_pins_a: uart1@0 {
 188                                 allwinner,pins = "PE10", "PE11";
 189                                 allwinner,function = "uart1";
 190                                 allwinner,drive = <0>;
 191                                 allwinner,pull = <0>;
 192                         };
 193
 194                         uart1_pins_b: uart1@1 {
 195                                 allwinner,pins = "PG3", "PG4";
 196                                 allwinner,function = "uart1";
 197                                 allwinner,drive = <0>;
 198                                 allwinner,pull = <0>;
 199                         };
 200                 };
 201
 202                 timer@01c20c00 {
 203                         compatible = "allwinner,sun4i-timer";
 204                         reg = <0x01c20c00 0x90>;
 205                         interrupts = <22>;
 206                         clocks = <&osc24M>;
 207                 };
 208
 209                 wdt: watchdog@01c20c90 {
 210                         compatible = "allwinner,sun4i-wdt";
 211                         reg = <0x01c20c90 0x10>;
 212                 };
 213
 214                 uart1: serial@01c28400 {
 215                         compatible = "snps,dw-apb-uart";
 216                         reg = <0x01c28400 0x400>;
 217                         interrupts = <2>;
 218                         reg-shift = <2>;
 219                         reg-io-width = <4>;
 220                         clocks = <&apb1_gates 17>;
 221                         status = "disabled";
 222                 };
 223
 224                 uart3: serial@01c28c00 {
 225                         compatible = "snps,dw-apb-uart";
 226                         reg = <0x01c28c00 0x400>;
 227                         interrupts = <4>;
 228                         reg-shift = <2>;
 229                         reg-io-width = <4>;
 230                         clocks = <&apb1_gates 19>;
 231                         status = "disabled";
 232                 };
 233         };
 234 };