2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
24 compatible = "arm,cortex-a8";
30 reg = <0x40000000 0x20000000>;
39 * This is a dummy clock, to be used as placeholder on
40 * other mux clocks when a specific parent clock is not
41 * yet implemented. It should be dropped when the driver
46 compatible = "fixed-clock";
47 clock-frequency = <0>;
50 osc24M: clk@01c20050 {
52 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>;
55 clock-output-names = "osc24M";
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
62 clock-output-names = "osc32k";
67 compatible = "allwinner,sun4i-a10-pll1-clk";
68 reg = <0x01c20000 0x4>;
70 clock-output-names = "pll1";
75 compatible = "allwinner,sun4i-a10-pll1-clk";
76 reg = <0x01c20018 0x4>;
78 clock-output-names = "pll4";
83 compatible = "allwinner,sun4i-a10-pll5-clk";
84 reg = <0x01c20020 0x4>;
86 clock-output-names = "pll5_ddr", "pll5_other";
91 compatible = "allwinner,sun4i-a10-pll6-clk";
92 reg = <0x01c20028 0x4>;
94 clock-output-names = "pll6_sata", "pll6_other", "pll6";
100 compatible = "allwinner,sun4i-a10-cpu-clk";
101 reg = <0x01c20054 0x4>;
102 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
103 clock-output-names = "cpu";
108 compatible = "allwinner,sun4i-a10-axi-clk";
109 reg = <0x01c20054 0x4>;
111 clock-output-names = "axi";
114 axi_gates: clk@01c2005c {
116 compatible = "allwinner,sun4i-a10-axi-gates-clk";
117 reg = <0x01c2005c 0x4>;
119 clock-output-names = "axi_dram";
124 compatible = "allwinner,sun4i-a10-ahb-clk";
125 reg = <0x01c20054 0x4>;
127 clock-output-names = "ahb";
130 ahb_gates: clk@01c20060 {
132 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
133 reg = <0x01c20060 0x8>;
135 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
136 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
137 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
138 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
139 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
140 "ahb_de_fe", "ahb_iep", "ahb_mali400";
143 apb0: apb0@01c20054 {
145 compatible = "allwinner,sun4i-a10-apb0-clk";
146 reg = <0x01c20054 0x4>;
148 clock-output-names = "apb0";
151 apb0_gates: clk@01c20068 {
153 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
154 reg = <0x01c20068 0x4>;
156 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
161 compatible = "allwinner,sun4i-a10-apb1-clk";
162 reg = <0x01c20058 0x4>;
163 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
164 clock-output-names = "apb1";
167 apb1_gates: clk@01c2006c {
169 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
170 reg = <0x01c2006c 0x4>;
172 clock-output-names = "apb1_i2c0", "apb1_i2c1",
173 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
176 nand_clk: clk@01c20080 {
178 compatible = "allwinner,sun4i-a10-mod0-clk";
179 reg = <0x01c20080 0x4>;
180 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
181 clock-output-names = "nand";
184 ms_clk: clk@01c20084 {
186 compatible = "allwinner,sun4i-a10-mod0-clk";
187 reg = <0x01c20084 0x4>;
188 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
189 clock-output-names = "ms";
192 mmc0_clk: clk@01c20088 {
194 compatible = "allwinner,sun4i-a10-mod0-clk";
195 reg = <0x01c20088 0x4>;
196 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
197 clock-output-names = "mmc0";
200 mmc1_clk: clk@01c2008c {
202 compatible = "allwinner,sun4i-a10-mod0-clk";
203 reg = <0x01c2008c 0x4>;
204 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
205 clock-output-names = "mmc1";
208 mmc2_clk: clk@01c20090 {
210 compatible = "allwinner,sun4i-a10-mod0-clk";
211 reg = <0x01c20090 0x4>;
212 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
213 clock-output-names = "mmc2";
216 ts_clk: clk@01c20098 {
218 compatible = "allwinner,sun4i-a10-mod0-clk";
219 reg = <0x01c20098 0x4>;
220 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
221 clock-output-names = "ts";
224 ss_clk: clk@01c2009c {
226 compatible = "allwinner,sun4i-a10-mod0-clk";
227 reg = <0x01c2009c 0x4>;
228 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
229 clock-output-names = "ss";
232 spi0_clk: clk@01c200a0 {
234 compatible = "allwinner,sun4i-a10-mod0-clk";
235 reg = <0x01c200a0 0x4>;
236 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
237 clock-output-names = "spi0";
240 spi1_clk: clk@01c200a4 {
242 compatible = "allwinner,sun4i-a10-mod0-clk";
243 reg = <0x01c200a4 0x4>;
244 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
245 clock-output-names = "spi1";
248 spi2_clk: clk@01c200a8 {
250 compatible = "allwinner,sun4i-a10-mod0-clk";
251 reg = <0x01c200a8 0x4>;
252 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
253 clock-output-names = "spi2";
256 ir0_clk: clk@01c200b0 {
258 compatible = "allwinner,sun4i-a10-mod0-clk";
259 reg = <0x01c200b0 0x4>;
260 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
261 clock-output-names = "ir0";
264 usb_clk: clk@01c200cc {
267 compatible = "allwinner,sun5i-a13-usb-clk";
268 reg = <0x01c200cc 0x4>;
270 clock-output-names = "usb_ohci0", "usb_phy";
273 mbus_clk: clk@01c2015c {
275 compatible = "allwinner,sun5i-a13-mbus-clk";
276 reg = <0x01c2015c 0x4>;
277 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
278 clock-output-names = "mbus";
283 compatible = "simple-bus";
284 #address-cells = <1>;
288 dma: dma-controller@01c02000 {
289 compatible = "allwinner,sun4i-a10-dma";
290 reg = <0x01c02000 0x1000>;
292 clocks = <&ahb_gates 6>;
297 compatible = "allwinner,sun4i-a10-spi";
298 reg = <0x01c05000 0x1000>;
300 clocks = <&ahb_gates 20>, <&spi0_clk>;
301 clock-names = "ahb", "mod";
302 dmas = <&dma 1 27>, <&dma 1 26>;
303 dma-names = "rx", "tx";
305 #address-cells = <1>;
310 compatible = "allwinner,sun4i-a10-spi";
311 reg = <0x01c06000 0x1000>;
313 clocks = <&ahb_gates 21>, <&spi1_clk>;
314 clock-names = "ahb", "mod";
315 dmas = <&dma 1 9>, <&dma 1 8>;
316 dma-names = "rx", "tx";
318 #address-cells = <1>;
323 compatible = "allwinner,sun5i-a13-mmc";
324 reg = <0x01c0f000 0x1000>;
325 clocks = <&ahb_gates 8>, <&mmc0_clk>;
326 clock-names = "ahb", "mmc";
332 compatible = "allwinner,sun5i-a13-mmc";
333 reg = <0x01c11000 0x1000>;
334 clocks = <&ahb_gates 10>, <&mmc2_clk>;
335 clock-names = "ahb", "mmc";
340 usbphy: phy@01c13400 {
342 compatible = "allwinner,sun5i-a13-usb-phy";
343 reg = <0x01c13400 0x10 0x01c14800 0x4>;
344 reg-names = "phy_ctrl", "pmu1";
345 clocks = <&usb_clk 8>;
346 clock-names = "usb_phy";
347 resets = <&usb_clk 0>, <&usb_clk 1>;
348 reset-names = "usb0_reset", "usb1_reset";
352 ehci0: usb@01c14000 {
353 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
354 reg = <0x01c14000 0x100>;
356 clocks = <&ahb_gates 1>;
362 ohci0: usb@01c14400 {
363 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
364 reg = <0x01c14400 0x100>;
366 clocks = <&usb_clk 6>, <&ahb_gates 2>;
373 compatible = "allwinner,sun4i-a10-spi";
374 reg = <0x01c17000 0x1000>;
376 clocks = <&ahb_gates 22>, <&spi2_clk>;
377 clock-names = "ahb", "mod";
378 dmas = <&dma 1 29>, <&dma 1 28>;
379 dma-names = "rx", "tx";
381 #address-cells = <1>;
385 intc: interrupt-controller@01c20400 {
386 compatible = "allwinner,sun4i-a10-ic";
387 reg = <0x01c20400 0x400>;
388 interrupt-controller;
389 #interrupt-cells = <1>;
392 pio: pinctrl@01c20800 {
393 compatible = "allwinner,sun5i-a13-pinctrl";
394 reg = <0x01c20800 0x400>;
396 clocks = <&apb0_gates 5>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
403 uart1_pins_a: uart1@0 {
404 allwinner,pins = "PE10", "PE11";
405 allwinner,function = "uart1";
406 allwinner,drive = <0>;
407 allwinner,pull = <0>;
410 uart1_pins_b: uart1@1 {
411 allwinner,pins = "PG3", "PG4";
412 allwinner,function = "uart1";
413 allwinner,drive = <0>;
414 allwinner,pull = <0>;
417 i2c0_pins_a: i2c0@0 {
418 allwinner,pins = "PB0", "PB1";
419 allwinner,function = "i2c0";
420 allwinner,drive = <0>;
421 allwinner,pull = <0>;
424 i2c1_pins_a: i2c1@0 {
425 allwinner,pins = "PB15", "PB16";
426 allwinner,function = "i2c1";
427 allwinner,drive = <0>;
428 allwinner,pull = <0>;
431 i2c2_pins_a: i2c2@0 {
432 allwinner,pins = "PB17", "PB18";
433 allwinner,function = "i2c2";
434 allwinner,drive = <0>;
435 allwinner,pull = <0>;
438 mmc0_pins_a: mmc0@0 {
439 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
440 allwinner,function = "mmc0";
441 allwinner,drive = <2>;
442 allwinner,pull = <0>;
447 compatible = "allwinner,sun4i-a10-timer";
448 reg = <0x01c20c00 0x90>;
453 wdt: watchdog@01c20c90 {
454 compatible = "allwinner,sun4i-a10-wdt";
455 reg = <0x01c20c90 0x10>;
458 sid: eeprom@01c23800 {
459 compatible = "allwinner,sun4i-a10-sid";
460 reg = <0x01c23800 0x10>;
464 compatible = "allwinner,sun4i-a10-ts";
465 reg = <0x01c25000 0x100>;
469 uart1: serial@01c28400 {
470 compatible = "snps,dw-apb-uart";
471 reg = <0x01c28400 0x400>;
475 clocks = <&apb1_gates 17>;
479 uart3: serial@01c28c00 {
480 compatible = "snps,dw-apb-uart";
481 reg = <0x01c28c00 0x400>;
485 clocks = <&apb1_gates 19>;
490 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
491 reg = <0x01c2ac00 0x400>;
493 clocks = <&apb1_gates 0>;
495 #address-cells = <1>;
500 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
501 reg = <0x01c2b000 0x400>;
503 clocks = <&apb1_gates 1>;
505 #address-cells = <1>;
510 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
511 reg = <0x01c2b400 0x400>;
513 clocks = <&apb1_gates 2>;
515 #address-cells = <1>;
520 compatible = "allwinner,sun5i-a13-hstimer";
521 reg = <0x01c60000 0x1000>;
522 interrupts = <82>, <83>;
523 clocks = <&ahb_gates 28>;