2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
17 interrupt-parent = <&intc>;
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
43 compatible = "arm,cortex-a8";
48 reg = <0x40000000 0x20000000>;
57 * This is a dummy clock, to be used as placeholder on
58 * other mux clocks when a specific parent clock is not
59 * yet implemented. It should be dropped when the driver
64 compatible = "fixed-clock";
65 clock-frequency = <0>;
68 osc24M: clk@01c20050 {
70 compatible = "allwinner,sun4i-a10-osc-clk";
71 reg = <0x01c20050 0x4>;
72 clock-frequency = <24000000>;
73 clock-output-names = "osc24M";
78 compatible = "fixed-clock";
79 clock-frequency = <32768>;
80 clock-output-names = "osc32k";
85 compatible = "allwinner,sun4i-a10-pll1-clk";
86 reg = <0x01c20000 0x4>;
88 clock-output-names = "pll1";
93 compatible = "allwinner,sun4i-a10-pll1-clk";
94 reg = <0x01c20018 0x4>;
96 clock-output-names = "pll4";
101 compatible = "allwinner,sun4i-a10-pll5-clk";
102 reg = <0x01c20020 0x4>;
104 clock-output-names = "pll5_ddr", "pll5_other";
109 compatible = "allwinner,sun4i-a10-pll6-clk";
110 reg = <0x01c20028 0x4>;
112 clock-output-names = "pll6_sata", "pll6_other", "pll6";
118 compatible = "allwinner,sun4i-a10-cpu-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
121 clock-output-names = "cpu";
126 compatible = "allwinner,sun4i-a10-axi-clk";
127 reg = <0x01c20054 0x4>;
129 clock-output-names = "axi";
132 axi_gates: clk@01c2005c {
134 compatible = "allwinner,sun4i-a10-axi-gates-clk";
135 reg = <0x01c2005c 0x4>;
137 clock-output-names = "axi_dram";
142 compatible = "allwinner,sun4i-a10-ahb-clk";
143 reg = <0x01c20054 0x4>;
145 clock-output-names = "ahb";
148 ahb_gates: clk@01c20060 {
150 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
151 reg = <0x01c20060 0x8>;
153 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
154 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
155 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
156 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
157 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
158 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
159 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
162 apb0: apb0@01c20054 {
164 compatible = "allwinner,sun4i-a10-apb0-clk";
165 reg = <0x01c20054 0x4>;
167 clock-output-names = "apb0";
170 apb0_gates: clk@01c20068 {
172 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
173 reg = <0x01c20068 0x4>;
175 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
176 "apb0_ir", "apb0_keypad";
181 compatible = "allwinner,sun4i-a10-apb1-clk";
182 reg = <0x01c20058 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
184 clock-output-names = "apb1";
187 apb1_gates: clk@01c2006c {
189 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
190 reg = <0x01c2006c 0x4>;
192 clock-output-names = "apb1_i2c0", "apb1_i2c1",
193 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
194 "apb1_uart2", "apb1_uart3";
197 nand_clk: clk@01c20080 {
199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20080 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "nand";
205 ms_clk: clk@01c20084 {
207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20084 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "ms";
213 mmc0_clk: clk@01c20088 {
215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c20088 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc0";
221 mmc1_clk: clk@01c2008c {
223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c2008c 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc1";
229 mmc2_clk: clk@01c20090 {
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20090 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "mmc2";
237 ts_clk: clk@01c20098 {
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c20098 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ts";
245 ss_clk: clk@01c2009c {
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c2009c 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "ss";
253 spi0_clk: clk@01c200a0 {
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a0 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi0";
261 spi1_clk: clk@01c200a4 {
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a4 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi1";
269 spi2_clk: clk@01c200a8 {
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200a8 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "spi2";
277 ir0_clk: clk@01c200b0 {
279 compatible = "allwinner,sun4i-a10-mod0-clk";
280 reg = <0x01c200b0 0x4>;
281 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
282 clock-output-names = "ir0";
285 usb_clk: clk@01c200cc {
288 compatible = "allwinner,sun5i-a13-usb-clk";
289 reg = <0x01c200cc 0x4>;
291 clock-output-names = "usb_ohci0", "usb_phy";
294 mbus_clk: clk@01c2015c {
296 compatible = "allwinner,sun5i-a13-mbus-clk";
297 reg = <0x01c2015c 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "mbus";
304 compatible = "simple-bus";
305 #address-cells = <1>;
309 dma: dma-controller@01c02000 {
310 compatible = "allwinner,sun4i-a10-dma";
311 reg = <0x01c02000 0x1000>;
313 clocks = <&ahb_gates 6>;
318 compatible = "allwinner,sun4i-a10-spi";
319 reg = <0x01c05000 0x1000>;
321 clocks = <&ahb_gates 20>, <&spi0_clk>;
322 clock-names = "ahb", "mod";
323 dmas = <&dma 1 27>, <&dma 1 26>;
324 dma-names = "rx", "tx";
326 #address-cells = <1>;
331 compatible = "allwinner,sun4i-a10-spi";
332 reg = <0x01c06000 0x1000>;
334 clocks = <&ahb_gates 21>, <&spi1_clk>;
335 clock-names = "ahb", "mod";
336 dmas = <&dma 1 9>, <&dma 1 8>;
337 dma-names = "rx", "tx";
339 #address-cells = <1>;
343 emac: ethernet@01c0b000 {
344 compatible = "allwinner,sun4i-a10-emac";
345 reg = <0x01c0b000 0x1000>;
347 clocks = <&ahb_gates 17>;
352 compatible = "allwinner,sun4i-a10-mdio";
353 reg = <0x01c0b080 0x14>;
355 #address-cells = <1>;
360 compatible = "allwinner,sun5i-a13-mmc";
361 reg = <0x01c0f000 0x1000>;
362 clocks = <&ahb_gates 8>, <&mmc0_clk>;
363 clock-names = "ahb", "mmc";
369 compatible = "allwinner,sun5i-a13-mmc";
370 reg = <0x01c10000 0x1000>;
371 clocks = <&ahb_gates 9>, <&mmc1_clk>;
372 clock-names = "ahb", "mmc";
378 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c11000 0x1000>;
380 clocks = <&ahb_gates 10>, <&mmc2_clk>;
381 clock-names = "ahb", "mmc";
386 usbphy: phy@01c13400 {
388 compatible = "allwinner,sun5i-a13-usb-phy";
389 reg = <0x01c13400 0x10 0x01c14800 0x4>;
390 reg-names = "phy_ctrl", "pmu1";
391 clocks = <&usb_clk 8>;
392 clock-names = "usb_phy";
393 resets = <&usb_clk 0>, <&usb_clk 1>;
394 reset-names = "usb0_reset", "usb1_reset";
398 ehci0: usb@01c14000 {
399 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
400 reg = <0x01c14000 0x100>;
402 clocks = <&ahb_gates 1>;
408 ohci0: usb@01c14400 {
409 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
410 reg = <0x01c14400 0x100>;
412 clocks = <&usb_clk 6>, <&ahb_gates 2>;
419 compatible = "allwinner,sun4i-a10-spi";
420 reg = <0x01c17000 0x1000>;
422 clocks = <&ahb_gates 22>, <&spi2_clk>;
423 clock-names = "ahb", "mod";
424 dmas = <&dma 1 29>, <&dma 1 28>;
425 dma-names = "rx", "tx";
427 #address-cells = <1>;
431 intc: interrupt-controller@01c20400 {
432 compatible = "allwinner,sun4i-a10-ic";
433 reg = <0x01c20400 0x400>;
434 interrupt-controller;
435 #interrupt-cells = <1>;
438 pio: pinctrl@01c20800 {
439 compatible = "allwinner,sun5i-a10s-pinctrl";
440 reg = <0x01c20800 0x400>;
442 clocks = <&apb0_gates 5>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
449 uart0_pins_a: uart0@0 {
450 allwinner,pins = "PB19", "PB20";
451 allwinner,function = "uart0";
452 allwinner,drive = <0>;
453 allwinner,pull = <0>;
456 uart2_pins_a: uart2@0 {
457 allwinner,pins = "PC18", "PC19";
458 allwinner,function = "uart2";
459 allwinner,drive = <0>;
460 allwinner,pull = <0>;
463 uart3_pins_a: uart3@0 {
464 allwinner,pins = "PG9", "PG10";
465 allwinner,function = "uart3";
466 allwinner,drive = <0>;
467 allwinner,pull = <0>;
470 emac_pins_a: emac0@0 {
471 allwinner,pins = "PA0", "PA1", "PA2",
472 "PA3", "PA4", "PA5", "PA6",
473 "PA7", "PA8", "PA9", "PA10",
474 "PA11", "PA12", "PA13", "PA14",
476 allwinner,function = "emac";
477 allwinner,drive = <0>;
478 allwinner,pull = <0>;
481 i2c0_pins_a: i2c0@0 {
482 allwinner,pins = "PB0", "PB1";
483 allwinner,function = "i2c0";
484 allwinner,drive = <0>;
485 allwinner,pull = <0>;
488 i2c1_pins_a: i2c1@0 {
489 allwinner,pins = "PB15", "PB16";
490 allwinner,function = "i2c1";
491 allwinner,drive = <0>;
492 allwinner,pull = <0>;
495 i2c2_pins_a: i2c2@0 {
496 allwinner,pins = "PB17", "PB18";
497 allwinner,function = "i2c2";
498 allwinner,drive = <0>;
499 allwinner,pull = <0>;
502 mmc0_pins_a: mmc0@0 {
503 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
504 allwinner,function = "mmc0";
505 allwinner,drive = <2>;
506 allwinner,pull = <0>;
509 mmc1_pins_a: mmc1@0 {
510 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
511 allwinner,function = "mmc1";
512 allwinner,drive = <2>;
513 allwinner,pull = <0>;
518 compatible = "allwinner,sun4i-a10-timer";
519 reg = <0x01c20c00 0x90>;
524 wdt: watchdog@01c20c90 {
525 compatible = "allwinner,sun4i-a10-wdt";
526 reg = <0x01c20c90 0x10>;
529 lradc: lradc@01c22800 {
530 compatible = "allwinner,sun4i-a10-lradc-keys";
531 reg = <0x01c22800 0x100>;
536 sid: eeprom@01c23800 {
537 compatible = "allwinner,sun4i-a10-sid";
538 reg = <0x01c23800 0x10>;
542 compatible = "allwinner,sun4i-a10-ts";
543 reg = <0x01c25000 0x100>;
547 uart0: serial@01c28000 {
548 compatible = "snps,dw-apb-uart";
549 reg = <0x01c28000 0x400>;
553 clocks = <&apb1_gates 16>;
557 uart1: serial@01c28400 {
558 compatible = "snps,dw-apb-uart";
559 reg = <0x01c28400 0x400>;
563 clocks = <&apb1_gates 17>;
567 uart2: serial@01c28800 {
568 compatible = "snps,dw-apb-uart";
569 reg = <0x01c28800 0x400>;
573 clocks = <&apb1_gates 18>;
577 uart3: serial@01c28c00 {
578 compatible = "snps,dw-apb-uart";
579 reg = <0x01c28c00 0x400>;
583 clocks = <&apb1_gates 19>;
588 #address-cells = <1>;
590 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
591 reg = <0x01c2ac00 0x400>;
593 clocks = <&apb1_gates 0>;
598 #address-cells = <1>;
600 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
601 reg = <0x01c2b000 0x400>;
603 clocks = <&apb1_gates 1>;
608 #address-cells = <1>;
610 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
611 reg = <0x01c2b400 0x400>;
613 clocks = <&apb1_gates 2>;
618 compatible = "allwinner,sun5i-a13-hstimer";
619 reg = <0x01c60000 0x1000>;
620 interrupts = <82>, <83>;
621 clocks = <&ahb_gates 28>;