arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "skeleton.dtsi"
  45
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&intc>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56         };
  57
  58         chosen {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 framebuffer@0 {
  64                         compatible = "allwinner,simple-framebuffer",
  65                                      "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  68                                  <&ahb_gates 44>;
  69                         status = "disabled";
  70                 };
  71
  72                 framebuffer@1 {
  73                         compatible = "allwinner,simple-framebuffer",
  74                                      "simple-framebuffer";
  75                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  76                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  77                                  <&ahb_gates 44>, <&ahb_gates 46>;
  78                         status = "disabled";
  79                 };
  80
  81                 framebuffer@2 {
  82                         compatible = "allwinner,simple-framebuffer",
  83                                      "simple-framebuffer";
  84                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  85                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  86                                  <&ahb_gates 46>;
  87                         status = "disabled";
  88                 };
  89
  90                 framebuffer@3 {
  91                         compatible = "allwinner,simple-framebuffer",
  92                                      "simple-framebuffer";
  93                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  94                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  95                                  <&ahb_gates 44>, <&ahb_gates 46>;
  96                         status = "disabled";
  97                 };
  98         };
  99
 100         cpus {
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 cpu0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a8";
 106                         reg = <0x0>;
 107                         clocks = <&cpu>;
 108                         clock-latency = <244144>; /* 8 32k periods */
 109                         operating-points = <
 110                                 /* kHz    uV */
 111                                 1008000 1400000
 112                                 912000  1350000
 113                                 864000  1300000
 114                                 624000  1250000
 115                                 >;
 116                         #cooling-cells = <2>;
 117                         cooling-min-level = <0>;
 118                         cooling-max-level = <3>;
 119                 };
 120         };
 121
 122         thermal-zones {
 123                 cpu_thermal {
 124                         /* milliseconds */
 125                         polling-delay-passive = <250>;
 126                         polling-delay = <1000>;
 127                         thermal-sensors = <&rtp>;
 128
 129                         cooling-maps {
 130                                 map0 {
 131                                         trip = <&cpu_alert0>;
 132                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 133                                 };
 134                         };
 135
 136                         trips {
 137                                 cpu_alert0: cpu_alert0 {
 138                                         /* milliCelsius */
 139                                         temperature = <850000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 cpu_crit: cpu_crit {
 145                                         /* milliCelsius */
 146                                         temperature = <100000>;
 147                                         hysteresis = <2000>;
 148                                         type = "critical";
 149                                 };
 150                         };
 151                 };
 152         };
 153
 154         memory {
 155                 reg = <0x40000000 0x80000000>;
 156         };
 157
 158         clocks {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 ranges;
 162
 163                 /*
 164                  * This is a dummy clock, to be used as placeholder on
 165                  * other mux clocks when a specific parent clock is not
 166                  * yet implemented. It should be dropped when the driver
 167                  * is complete.
 168                  */
 169                 dummy: dummy {
 170                         #clock-cells = <0>;
 171                         compatible = "fixed-clock";
 172                         clock-frequency = <0>;
 173                 };
 174
 175                 osc24M: clk@01c20050 {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun4i-a10-osc-clk";
 178                         reg = <0x01c20050 0x4>;
 179                         clock-frequency = <24000000>;
 180                         clock-output-names = "osc24M";
 181                 };
 182
 183                 osc32k: clk@0 {
 184                         #clock-cells = <0>;
 185                         compatible = "fixed-clock";
 186                         clock-frequency = <32768>;
 187                         clock-output-names = "osc32k";
 188                 };
 189
 190                 pll1: clk@01c20000 {
 191                         #clock-cells = <0>;
 192                         compatible = "allwinner,sun4i-a10-pll1-clk";
 193                         reg = <0x01c20000 0x4>;
 194                         clocks = <&osc24M>;
 195                         clock-output-names = "pll1";
 196                 };
 197
 198                 pll4: clk@01c20018 {
 199                         #clock-cells = <0>;
 200                         compatible = "allwinner,sun4i-a10-pll1-clk";
 201                         reg = <0x01c20018 0x4>;
 202                         clocks = <&osc24M>;
 203                         clock-output-names = "pll4";
 204                 };
 205
 206                 pll5: clk@01c20020 {
 207                         #clock-cells = <1>;
 208                         compatible = "allwinner,sun4i-a10-pll5-clk";
 209                         reg = <0x01c20020 0x4>;
 210                         clocks = <&osc24M>;
 211                         clock-output-names = "pll5_ddr", "pll5_other";
 212                 };
 213
 214                 pll6: clk@01c20028 {
 215                         #clock-cells = <1>;
 216                         compatible = "allwinner,sun4i-a10-pll6-clk";
 217                         reg = <0x01c20028 0x4>;
 218                         clocks = <&osc24M>;
 219                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 220                 };
 221
 222                 /* dummy is 200M */
 223                 cpu: cpu@01c20054 {
 224                         #clock-cells = <0>;
 225                         compatible = "allwinner,sun4i-a10-cpu-clk";
 226                         reg = <0x01c20054 0x4>;
 227                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 228                         clock-output-names = "cpu";
 229                 };
 230
 231                 axi: axi@01c20054 {
 232                         #clock-cells = <0>;
 233                         compatible = "allwinner,sun4i-a10-axi-clk";
 234                         reg = <0x01c20054 0x4>;
 235                         clocks = <&cpu>;
 236                         clock-output-names = "axi";
 237                 };
 238
 239                 axi_gates: clk@01c2005c {
 240                         #clock-cells = <1>;
 241                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 242                         reg = <0x01c2005c 0x4>;
 243                         clocks = <&axi>;
 244                         clock-indices = <0>;
 245                         clock-output-names = "axi_dram";
 246                 };
 247
 248                 ahb: ahb@01c20054 {
 249                         #clock-cells = <0>;
 250                         compatible = "allwinner,sun4i-a10-ahb-clk";
 251                         reg = <0x01c20054 0x4>;
 252                         clocks = <&axi>;
 253                         clock-output-names = "ahb";
 254                 };
 255
 256                 ahb_gates: clk@01c20060 {
 257                         #clock-cells = <1>;
 258                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 259                         reg = <0x01c20060 0x8>;
 260                         clocks = <&ahb>;
 261                         clock-indices = <0>, <1>,
 262                                         <2>, <3>,
 263                                         <4>, <5>, <6>,
 264                                         <7>, <8>, <9>,
 265                                         <10>, <11>, <12>,
 266                                         <13>, <14>, <16>,
 267                                         <17>, <18>, <20>,
 268                                         <21>, <22>, <23>,
 269                                         <24>, <25>, <26>,
 270                                         <32>, <33>, <34>,
 271                                         <35>, <36>, <37>,
 272                                         <40>, <41>, <43>,
 273                                         <44>, <45>,
 274                                         <46>, <47>,
 275                                         <50>, <52>;
 276                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 277                                              "ahb_ohci0", "ahb_ehci1",
 278                                              "ahb_ohci1", "ahb_ss", "ahb_dma",
 279                                              "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 280                                              "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 281                                              "ahb_nand", "ahb_sdram", "ahb_ace",
 282                                              "ahb_emac", "ahb_ts", "ahb_spi0",
 283                                              "ahb_spi1", "ahb_spi2", "ahb_spi3",
 284                                              "ahb_pata", "ahb_sata", "ahb_gps",
 285                                              "ahb_ve", "ahb_tvd", "ahb_tve0",
 286                                              "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
 287                                              "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 288                                              "ahb_de_be0", "ahb_de_be1",
 289                                              "ahb_de_fe0", "ahb_de_fe1",
 290                                              "ahb_mp", "ahb_mali400";
 291                 };
 292
 293                 apb0: apb0@01c20054 {
 294                         #clock-cells = <0>;
 295                         compatible = "allwinner,sun4i-a10-apb0-clk";
 296                         reg = <0x01c20054 0x4>;
 297                         clocks = <&ahb>;
 298                         clock-output-names = "apb0";
 299                 };
 300
 301                 apb0_gates: clk@01c20068 {
 302                         #clock-cells = <1>;
 303                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 304                         reg = <0x01c20068 0x4>;
 305                         clocks = <&apb0>;
 306                         clock-indices = <0>, <1>,
 307                                         <2>, <3>,
 308                                         <5>, <6>,
 309                                         <7>, <10>;
 310                         clock-output-names = "apb0_codec", "apb0_spdif",
 311                                              "apb0_ac97", "apb0_iis",
 312                                              "apb0_pio", "apb0_ir0",
 313                                              "apb0_ir1", "apb0_keypad";
 314                 };
 315
 316                 apb1: clk@01c20058 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-apb1-clk";
 319                         reg = <0x01c20058 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 321                         clock-output-names = "apb1";
 322                 };
 323
 324                 apb1_gates: clk@01c2006c {
 325                         #clock-cells = <1>;
 326                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 327                         reg = <0x01c2006c 0x4>;
 328                         clocks = <&apb1>;
 329                         clock-indices = <0>, <1>,
 330                                         <2>, <4>,
 331                                         <5>, <6>,
 332                                         <7>, <16>,
 333                                         <17>, <18>,
 334                                         <19>, <20>,
 335                                         <21>, <22>,
 336                                         <23>;
 337                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 338                                              "apb1_i2c2", "apb1_can",
 339                                              "apb1_scr", "apb1_ps20",
 340                                              "apb1_ps21", "apb1_uart0",
 341                                              "apb1_uart1", "apb1_uart2",
 342                                              "apb1_uart3", "apb1_uart4",
 343                                              "apb1_uart5", "apb1_uart6",
 344                                              "apb1_uart7";
 345                 };
 346
 347                 nand_clk: clk@01c20080 {
 348                         #clock-cells = <0>;
 349                         compatible = "allwinner,sun4i-a10-mod0-clk";
 350                         reg = <0x01c20080 0x4>;
 351                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 352                         clock-output-names = "nand";
 353                 };
 354
 355                 ms_clk: clk@01c20084 {
 356                         #clock-cells = <0>;
 357                         compatible = "allwinner,sun4i-a10-mod0-clk";
 358                         reg = <0x01c20084 0x4>;
 359                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 360                         clock-output-names = "ms";
 361                 };
 362
 363                 mmc0_clk: clk@01c20088 {
 364                         #clock-cells = <1>;
 365                         compatible = "allwinner,sun4i-a10-mmc-clk";
 366                         reg = <0x01c20088 0x4>;
 367                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 368                         clock-output-names = "mmc0",
 369                                              "mmc0_output",
 370                                              "mmc0_sample";
 371                 };
 372
 373                 mmc1_clk: clk@01c2008c {
 374                         #clock-cells = <1>;
 375                         compatible = "allwinner,sun4i-a10-mmc-clk";
 376                         reg = <0x01c2008c 0x4>;
 377                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 378                         clock-output-names = "mmc1",
 379                                              "mmc1_output",
 380                                              "mmc1_sample";
 381                 };
 382
 383                 mmc2_clk: clk@01c20090 {
 384                         #clock-cells = <1>;
 385                         compatible = "allwinner,sun4i-a10-mmc-clk";
 386                         reg = <0x01c20090 0x4>;
 387                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 388                         clock-output-names = "mmc2",
 389                                              "mmc2_output",
 390                                              "mmc2_sample";
 391                 };
 392
 393                 mmc3_clk: clk@01c20094 {
 394                         #clock-cells = <1>;
 395                         compatible = "allwinner,sun4i-a10-mmc-clk";
 396                         reg = <0x01c20094 0x4>;
 397                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 398                         clock-output-names = "mmc3",
 399                                              "mmc3_output",
 400                                              "mmc3_sample";
 401                 };
 402
 403                 ts_clk: clk@01c20098 {
 404                         #clock-cells = <0>;
 405                         compatible = "allwinner,sun4i-a10-mod0-clk";
 406                         reg = <0x01c20098 0x4>;
 407                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 408                         clock-output-names = "ts";
 409                 };
 410
 411                 ss_clk: clk@01c2009c {
 412                         #clock-cells = <0>;
 413                         compatible = "allwinner,sun4i-a10-mod0-clk";
 414                         reg = <0x01c2009c 0x4>;
 415                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 416                         clock-output-names = "ss";
 417                 };
 418
 419                 spi0_clk: clk@01c200a0 {
 420                         #clock-cells = <0>;
 421                         compatible = "allwinner,sun4i-a10-mod0-clk";
 422                         reg = <0x01c200a0 0x4>;
 423                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 424                         clock-output-names = "spi0";
 425                 };
 426
 427                 spi1_clk: clk@01c200a4 {
 428                         #clock-cells = <0>;
 429                         compatible = "allwinner,sun4i-a10-mod0-clk";
 430                         reg = <0x01c200a4 0x4>;
 431                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 432                         clock-output-names = "spi1";
 433                 };
 434
 435                 spi2_clk: clk@01c200a8 {
 436                         #clock-cells = <0>;
 437                         compatible = "allwinner,sun4i-a10-mod0-clk";
 438                         reg = <0x01c200a8 0x4>;
 439                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 440                         clock-output-names = "spi2";
 441                 };
 442
 443                 pata_clk: clk@01c200ac {
 444                         #clock-cells = <0>;
 445                         compatible = "allwinner,sun4i-a10-mod0-clk";
 446                         reg = <0x01c200ac 0x4>;
 447                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 448                         clock-output-names = "pata";
 449                 };
 450
 451                 ir0_clk: clk@01c200b0 {
 452                         #clock-cells = <0>;
 453                         compatible = "allwinner,sun4i-a10-mod0-clk";
 454                         reg = <0x01c200b0 0x4>;
 455                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 456                         clock-output-names = "ir0";
 457                 };
 458
 459                 ir1_clk: clk@01c200b4 {
 460                         #clock-cells = <0>;
 461                         compatible = "allwinner,sun4i-a10-mod0-clk";
 462                         reg = <0x01c200b4 0x4>;
 463                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 464                         clock-output-names = "ir1";
 465                 };
 466
 467                 usb_clk: clk@01c200cc {
 468                         #clock-cells = <1>;
 469                         #reset-cells = <1>;
 470                         compatible = "allwinner,sun4i-a10-usb-clk";
 471                         reg = <0x01c200cc 0x4>;
 472                         clocks = <&pll6 1>;
 473                         clock-output-names = "usb_ohci0", "usb_ohci1",
 474                                              "usb_phy";
 475                 };
 476
 477                 spi3_clk: clk@01c200d4 {
 478                         #clock-cells = <0>;
 479                         compatible = "allwinner,sun4i-a10-mod0-clk";
 480                         reg = <0x01c200d4 0x4>;
 481                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 482                         clock-output-names = "spi3";
 483                 };
 484         };
 485
 486         soc@01c00000 {
 487                 compatible = "simple-bus";
 488                 #address-cells = <1>;
 489                 #size-cells = <1>;
 490                 ranges;
 491
 492                 sram-controller@01c00000 {
 493                         compatible = "allwinner,sun4i-a10-sram-controller";
 494                         reg = <0x01c00000 0x30>;
 495                         #address-cells = <1>;
 496                         #size-cells = <1>;
 497                         ranges;
 498
 499                         sram_a: sram@00000000 {
 500                                 compatible = "mmio-sram";
 501                                 reg = <0x00000000 0xc000>;
 502                                 #address-cells = <1>;
 503                                 #size-cells = <1>;
 504                                 ranges = <0 0x00000000 0xc000>;
 505
 506                                 emac_sram: sram-section@8000 {
 507                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 508                                         reg = <0x8000 0x4000>;
 509                                         status = "disabled";
 510                                 };
 511                         };
 512
 513                         sram_d: sram@00010000 {
 514                                 compatible = "mmio-sram";
 515                                 reg = <0x00010000 0x1000>;
 516                                 #address-cells = <1>;
 517                                 #size-cells = <1>;
 518                                 ranges = <0 0x00010000 0x1000>;
 519
 520                                 otg_sram: sram-section@0000 {
 521                                         compatible = "allwinner,sun4i-a10-sram-d";
 522                                         reg = <0x0000 0x1000>;
 523                                         status = "disabled";
 524                                 };
 525                         };
 526                 };
 527
 528                 dma: dma-controller@01c02000 {
 529                         compatible = "allwinner,sun4i-a10-dma";
 530                         reg = <0x01c02000 0x1000>;
 531                         interrupts = <27>;
 532                         clocks = <&ahb_gates 6>;
 533                         #dma-cells = <2>;
 534                 };
 535
 536                 spi0: spi@01c05000 {
 537                         compatible = "allwinner,sun4i-a10-spi";
 538                         reg = <0x01c05000 0x1000>;
 539                         interrupts = <10>;
 540                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 541                         clock-names = "ahb", "mod";
 542                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 543                                <&dma SUN4I_DMA_DEDICATED 26>;
 544                         dma-names = "rx", "tx";
 545                         status = "disabled";
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                 };
 549
 550                 spi1: spi@01c06000 {
 551                         compatible = "allwinner,sun4i-a10-spi";
 552                         reg = <0x01c06000 0x1000>;
 553                         interrupts = <11>;
 554                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 555                         clock-names = "ahb", "mod";
 556                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 557                                <&dma SUN4I_DMA_DEDICATED 8>;
 558                         dma-names = "rx", "tx";
 559                         status = "disabled";
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                 };
 563
 564                 emac: ethernet@01c0b000 {
 565                         compatible = "allwinner,sun4i-a10-emac";
 566                         reg = <0x01c0b000 0x1000>;
 567                         interrupts = <55>;
 568                         clocks = <&ahb_gates 17>;
 569                         allwinner,sram = <&emac_sram 1>;
 570                         status = "disabled";
 571                 };
 572
 573                 mdio: mdio@01c0b080 {
 574                         compatible = "allwinner,sun4i-a10-mdio";
 575                         reg = <0x01c0b080 0x14>;
 576                         status = "disabled";
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                 };
 580
 581                 mmc0: mmc@01c0f000 {
 582                         compatible = "allwinner,sun4i-a10-mmc";
 583                         reg = <0x01c0f000 0x1000>;
 584                         clocks = <&ahb_gates 8>,
 585                                  <&mmc0_clk 0>,
 586                                  <&mmc0_clk 1>,
 587                                  <&mmc0_clk 2>;
 588                         clock-names = "ahb",
 589                                       "mmc",
 590                                       "output",
 591                                       "sample";
 592                         interrupts = <32>;
 593                         status = "disabled";
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                 };
 597
 598                 mmc1: mmc@01c10000 {
 599                         compatible = "allwinner,sun4i-a10-mmc";
 600                         reg = <0x01c10000 0x1000>;
 601                         clocks = <&ahb_gates 9>,
 602                                  <&mmc1_clk 0>,
 603                                  <&mmc1_clk 1>,
 604                                  <&mmc1_clk 2>;
 605                         clock-names = "ahb",
 606                                       "mmc",
 607                                       "output",
 608                                       "sample";
 609                         interrupts = <33>;
 610                         status = "disabled";
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                 };
 614
 615                 mmc2: mmc@01c11000 {
 616                         compatible = "allwinner,sun4i-a10-mmc";
 617                         reg = <0x01c11000 0x1000>;
 618                         clocks = <&ahb_gates 10>,
 619                                  <&mmc2_clk 0>,
 620                                  <&mmc2_clk 1>,
 621                                  <&mmc2_clk 2>;
 622                         clock-names = "ahb",
 623                                       "mmc",
 624                                       "output",
 625                                       "sample";
 626                         interrupts = <34>;
 627                         status = "disabled";
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630                 };
 631
 632                 mmc3: mmc@01c12000 {
 633                         compatible = "allwinner,sun4i-a10-mmc";
 634                         reg = <0x01c12000 0x1000>;
 635                         clocks = <&ahb_gates 11>,
 636                                  <&mmc3_clk 0>,
 637                                  <&mmc3_clk 1>,
 638                                  <&mmc3_clk 2>;
 639                         clock-names = "ahb",
 640                                       "mmc",
 641                                       "output",
 642                                       "sample";
 643                         interrupts = <35>;
 644                         status = "disabled";
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647                 };
 648
 649                 usb_otg: usb@01c13000 {
 650                         compatible = "allwinner,sun4i-a10-musb";
 651                         reg = <0x01c13000 0x0400>;
 652                         clocks = <&ahb_gates 0>;
 653                         interrupts = <38>;
 654                         interrupt-names = "mc";
 655                         phys = <&usbphy 0>;
 656                         phy-names = "usb";
 657                         extcon = <&usbphy 0>;
 658                         allwinner,sram = <&otg_sram 1>;
 659                         status = "disabled";
 660                 };
 661
 662                 usbphy: phy@01c13400 {
 663                         #phy-cells = <1>;
 664                         compatible = "allwinner,sun4i-a10-usb-phy";
 665                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 666                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 667                         clocks = <&usb_clk 8>;
 668                         clock-names = "usb_phy";
 669                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 670                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 671                         status = "disabled";
 672                 };
 673
 674                 ehci0: usb@01c14000 {
 675                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 676                         reg = <0x01c14000 0x100>;
 677                         interrupts = <39>;
 678                         clocks = <&ahb_gates 1>;
 679                         phys = <&usbphy 1>;
 680                         phy-names = "usb";
 681                         status = "disabled";
 682                 };
 683
 684                 ohci0: usb@01c14400 {
 685                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 686                         reg = <0x01c14400 0x100>;
 687                         interrupts = <64>;
 688                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 689                         phys = <&usbphy 1>;
 690                         phy-names = "usb";
 691                         status = "disabled";
 692                 };
 693
 694                 crypto: crypto-engine@01c15000 {
 695                         compatible = "allwinner,sun4i-a10-crypto";
 696                         reg = <0x01c15000 0x1000>;
 697                         interrupts = <86>;
 698                         clocks = <&ahb_gates 5>, <&ss_clk>;
 699                         clock-names = "ahb", "mod";
 700                 };
 701
 702                 spi2: spi@01c17000 {
 703                         compatible = "allwinner,sun4i-a10-spi";
 704                         reg = <0x01c17000 0x1000>;
 705                         interrupts = <12>;
 706                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 707                         clock-names = "ahb", "mod";
 708                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 709                                <&dma SUN4I_DMA_DEDICATED 28>;
 710                         dma-names = "rx", "tx";
 711                         status = "disabled";
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714                 };
 715
 716                 ahci: sata@01c18000 {
 717                         compatible = "allwinner,sun4i-a10-ahci";
 718                         reg = <0x01c18000 0x1000>;
 719                         interrupts = <56>;
 720                         clocks = <&pll6 0>, <&ahb_gates 25>;
 721                         status = "disabled";
 722                 };
 723
 724                 ehci1: usb@01c1c000 {
 725                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 726                         reg = <0x01c1c000 0x100>;
 727                         interrupts = <40>;
 728                         clocks = <&ahb_gates 3>;
 729                         phys = <&usbphy 2>;
 730                         phy-names = "usb";
 731                         status = "disabled";
 732                 };
 733
 734                 ohci1: usb@01c1c400 {
 735                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 736                         reg = <0x01c1c400 0x100>;
 737                         interrupts = <65>;
 738                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 739                         phys = <&usbphy 2>;
 740                         phy-names = "usb";
 741                         status = "disabled";
 742                 };
 743
 744                 spi3: spi@01c1f000 {
 745                         compatible = "allwinner,sun4i-a10-spi";
 746                         reg = <0x01c1f000 0x1000>;
 747                         interrupts = <50>;
 748                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 749                         clock-names = "ahb", "mod";
 750                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 751                                <&dma SUN4I_DMA_DEDICATED 30>;
 752                         dma-names = "rx", "tx";
 753                         status = "disabled";
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                 };
 757
 758                 intc: interrupt-controller@01c20400 {
 759                         compatible = "allwinner,sun4i-a10-ic";
 760                         reg = <0x01c20400 0x400>;
 761                         interrupt-controller;
 762                         #interrupt-cells = <1>;
 763                 };
 764
 765                 pio: pinctrl@01c20800 {
 766                         compatible = "allwinner,sun4i-a10-pinctrl";
 767                         reg = <0x01c20800 0x400>;
 768                         interrupts = <28>;
 769                         clocks = <&apb0_gates 5>;
 770                         gpio-controller;
 771                         interrupt-controller;
 772                         #interrupt-cells = <3>;
 773                         #gpio-cells = <3>;
 774
 775                         pwm0_pins_a: pwm0@0 {
 776                                 allwinner,pins = "PB2";
 777                                 allwinner,function = "pwm";
 778                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 779                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 780                         };
 781
 782                         pwm1_pins_a: pwm1@0 {
 783                                 allwinner,pins = "PI3";
 784                                 allwinner,function = "pwm";
 785                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 786                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 787                         };
 788
 789                         uart0_pins_a: uart0@0 {
 790                                 allwinner,pins = "PB22", "PB23";
 791                                 allwinner,function = "uart0";
 792                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 793                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 794                         };
 795
 796                         uart0_pins_b: uart0@1 {
 797                                 allwinner,pins = "PF2", "PF4";
 798                                 allwinner,function = "uart0";
 799                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 800                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 801                         };
 802
 803                         uart1_pins_a: uart1@0 {
 804                                 allwinner,pins = "PA10", "PA11";
 805                                 allwinner,function = "uart1";
 806                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 807                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 808                         };
 809
 810                         i2c0_pins_a: i2c0@0 {
 811                                 allwinner,pins = "PB0", "PB1";
 812                                 allwinner,function = "i2c0";
 813                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 814                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 815                         };
 816
 817                         i2c1_pins_a: i2c1@0 {
 818                                 allwinner,pins = "PB18", "PB19";
 819                                 allwinner,function = "i2c1";
 820                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 821                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 822                         };
 823
 824                         i2c2_pins_a: i2c2@0 {
 825                                 allwinner,pins = "PB20", "PB21";
 826                                 allwinner,function = "i2c2";
 827                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 828                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 829                         };
 830
 831                         emac_pins_a: emac0@0 {
 832                                 allwinner,pins = "PA0", "PA1", "PA2",
 833                                                 "PA3", "PA4", "PA5", "PA6",
 834                                                 "PA7", "PA8", "PA9", "PA10",
 835                                                 "PA11", "PA12", "PA13", "PA14",
 836                                                 "PA15", "PA16";
 837                                 allwinner,function = "emac";
 838                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 839                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 840                         };
 841
 842                         mmc0_pins_a: mmc0@0 {
 843                                 allwinner,pins = "PF0", "PF1", "PF2",
 844                                                  "PF3", "PF4", "PF5";
 845                                 allwinner,function = "mmc0";
 846                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 847                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 848                         };
 849
 850                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 851                                 allwinner,pins = "PH1";
 852                                 allwinner,function = "gpio_in";
 853                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 854                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 855                         };
 856
 857                         ir0_rx_pins_a: ir0@0 {
 858                                 allwinner,pins = "PB4";
 859                                 allwinner,function = "ir0";
 860                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 861                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 862                         };
 863
 864                         ir0_tx_pins_a: ir0@1 {
 865                                 allwinner,pins = "PB3";
 866                                 allwinner,function = "ir0";
 867                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 868                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 869                         };
 870
 871                         ir1_rx_pins_a: ir1@0 {
 872                                 allwinner,pins = "PB23";
 873                                 allwinner,function = "ir1";
 874                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 875                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 876                         };
 877
 878                         ir1_tx_pins_a: ir1@1 {
 879                                 allwinner,pins = "PB22";
 880                                 allwinner,function = "ir1";
 881                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 882                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 883                         };
 884
 885                         spi0_pins_a: spi0@0 {
 886                                 allwinner,pins = "PI11", "PI12", "PI13";
 887                                 allwinner,function = "spi0";
 888                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 889                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 890                         };
 891
 892                         spi0_cs0_pins_a: spi0_cs0@0 {
 893                                 allwinner,pins = "PI10";
 894                                 allwinner,function = "spi0";
 895                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 896                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 897                         };
 898
 899                         spi1_pins_a: spi1@0 {
 900                                 allwinner,pins = "PI17", "PI18", "PI19";
 901                                 allwinner,function = "spi1";
 902                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 903                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 904                         };
 905
 906                         spi1_cs0_pins_a: spi1_cs0@0 {
 907                                 allwinner,pins = "PI16";
 908                                 allwinner,function = "spi1";
 909                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 910                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 911                         };
 912
 913                         spi2_pins_a: spi2@0 {
 914                                 allwinner,pins = "PC20", "PC21", "PC22";
 915                                 allwinner,function = "spi2";
 916                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 917                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 918                         };
 919
 920                         spi2_pins_b: spi2@1 {
 921                                 allwinner,pins = "PB15", "PB16", "PB17";
 922                                 allwinner,function = "spi2";
 923                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 924                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 925                         };
 926
 927                         spi2_cs0_pins_a: spi2_cs0@0 {
 928                                 allwinner,pins = "PC19";
 929                                 allwinner,function = "spi2";
 930                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 931                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 932                         };
 933
 934                         spi2_cs0_pins_b: spi2_cs0@1 {
 935                                 allwinner,pins = "PB14";
 936                                 allwinner,function = "spi2";
 937                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 938                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 939                         };
 940
 941                         ps20_pins_a: ps20@0 {
 942                                 allwinner,pins = "PI20", "PI21";
 943                                 allwinner,function = "ps2";
 944                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 945                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 946                         };
 947
 948                         ps21_pins_a: ps21@0 {
 949                                 allwinner,pins = "PH12", "PH13";
 950                                 allwinner,function = "ps2";
 951                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 952                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 953                         };
 954                 };
 955
 956                 timer@01c20c00 {
 957                         compatible = "allwinner,sun4i-a10-timer";
 958                         reg = <0x01c20c00 0x90>;
 959                         interrupts = <22>;
 960                         clocks = <&osc24M>;
 961                 };
 962
 963                 wdt: watchdog@01c20c90 {
 964                         compatible = "allwinner,sun4i-a10-wdt";
 965                         reg = <0x01c20c90 0x10>;
 966                 };
 967
 968                 rtc: rtc@01c20d00 {
 969                         compatible = "allwinner,sun4i-a10-rtc";
 970                         reg = <0x01c20d00 0x20>;
 971                         interrupts = <24>;
 972                 };
 973
 974                 pwm: pwm@01c20e00 {
 975                         compatible = "allwinner,sun4i-a10-pwm";
 976                         reg = <0x01c20e00 0xc>;
 977                         clocks = <&osc24M>;
 978                         #pwm-cells = <3>;
 979                         status = "disabled";
 980                 };
 981
 982                 ir0: ir@01c21800 {
 983                         compatible = "allwinner,sun4i-a10-ir";
 984                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 985                         clock-names = "apb", "ir";
 986                         interrupts = <5>;
 987                         reg = <0x01c21800 0x40>;
 988                         status = "disabled";
 989                 };
 990
 991                 ir1: ir@01c21c00 {
 992                         compatible = "allwinner,sun4i-a10-ir";
 993                         clocks = <&apb0_gates 7>, <&ir1_clk>;
 994                         clock-names = "apb", "ir";
 995                         interrupts = <6>;
 996                         reg = <0x01c21c00 0x40>;
 997                         status = "disabled";
 998                 };
 999
1000                 lradc: lradc@01c22800 {
1001                         compatible = "allwinner,sun4i-a10-lradc-keys";
1002                         reg = <0x01c22800 0x100>;
1003                         interrupts = <31>;
1004                         status = "disabled";
1005                 };
1006
1007                 sid: eeprom@01c23800 {
1008                         compatible = "allwinner,sun4i-a10-sid";
1009                         reg = <0x01c23800 0x10>;
1010                 };
1011
1012                 rtp: rtp@01c25000 {
1013                         compatible = "allwinner,sun4i-a10-ts";
1014                         reg = <0x01c25000 0x100>;
1015                         interrupts = <29>;
1016                         #thermal-sensor-cells = <0>;
1017                 };
1018
1019                 uart0: serial@01c28000 {
1020                         compatible = "snps,dw-apb-uart";
1021                         reg = <0x01c28000 0x400>;
1022                         interrupts = <1>;
1023                         reg-shift = <2>;
1024                         reg-io-width = <4>;
1025                         clocks = <&apb1_gates 16>;
1026                         status = "disabled";
1027                 };
1028
1029                 uart1: serial@01c28400 {
1030                         compatible = "snps,dw-apb-uart";
1031                         reg = <0x01c28400 0x400>;
1032                         interrupts = <2>;
1033                         reg-shift = <2>;
1034                         reg-io-width = <4>;
1035                         clocks = <&apb1_gates 17>;
1036                         status = "disabled";
1037                 };
1038
1039                 uart2: serial@01c28800 {
1040                         compatible = "snps,dw-apb-uart";
1041                         reg = <0x01c28800 0x400>;
1042                         interrupts = <3>;
1043                         reg-shift = <2>;
1044                         reg-io-width = <4>;
1045                         clocks = <&apb1_gates 18>;
1046                         status = "disabled";
1047                 };
1048
1049                 uart3: serial@01c28c00 {
1050                         compatible = "snps,dw-apb-uart";
1051                         reg = <0x01c28c00 0x400>;
1052                         interrupts = <4>;
1053                         reg-shift = <2>;
1054                         reg-io-width = <4>;
1055                         clocks = <&apb1_gates 19>;
1056                         status = "disabled";
1057                 };
1058
1059                 uart4: serial@01c29000 {
1060                         compatible = "snps,dw-apb-uart";
1061                         reg = <0x01c29000 0x400>;
1062                         interrupts = <17>;
1063                         reg-shift = <2>;
1064                         reg-io-width = <4>;
1065                         clocks = <&apb1_gates 20>;
1066                         status = "disabled";
1067                 };
1068
1069                 uart5: serial@01c29400 {
1070                         compatible = "snps,dw-apb-uart";
1071                         reg = <0x01c29400 0x400>;
1072                         interrupts = <18>;
1073                         reg-shift = <2>;
1074                         reg-io-width = <4>;
1075                         clocks = <&apb1_gates 21>;
1076                         status = "disabled";
1077                 };
1078
1079                 uart6: serial@01c29800 {
1080                         compatible = "snps,dw-apb-uart";
1081                         reg = <0x01c29800 0x400>;
1082                         interrupts = <19>;
1083                         reg-shift = <2>;
1084                         reg-io-width = <4>;
1085                         clocks = <&apb1_gates 22>;
1086                         status = "disabled";
1087                 };
1088
1089                 uart7: serial@01c29c00 {
1090                         compatible = "snps,dw-apb-uart";
1091                         reg = <0x01c29c00 0x400>;
1092                         interrupts = <20>;
1093                         reg-shift = <2>;
1094                         reg-io-width = <4>;
1095                         clocks = <&apb1_gates 23>;
1096                         status = "disabled";
1097                 };
1098
1099                 i2c0: i2c@01c2ac00 {
1100                         compatible = "allwinner,sun4i-a10-i2c";
1101                         reg = <0x01c2ac00 0x400>;
1102                         interrupts = <7>;
1103                         clocks = <&apb1_gates 0>;
1104                         status = "disabled";
1105                         #address-cells = <1>;
1106                         #size-cells = <0>;
1107                 };
1108
1109                 i2c1: i2c@01c2b000 {
1110                         compatible = "allwinner,sun4i-a10-i2c";
1111                         reg = <0x01c2b000 0x400>;
1112                         interrupts = <8>;
1113                         clocks = <&apb1_gates 1>;
1114                         status = "disabled";
1115                         #address-cells = <1>;
1116                         #size-cells = <0>;
1117                 };
1118
1119                 i2c2: i2c@01c2b400 {
1120                         compatible = "allwinner,sun4i-a10-i2c";
1121                         reg = <0x01c2b400 0x400>;
1122                         interrupts = <9>;
1123                         clocks = <&apb1_gates 2>;
1124                         status = "disabled";
1125                         #address-cells = <1>;
1126                         #size-cells = <0>;
1127                 };
1128
1129                 ps20: ps2@01c2a000 {
1130                         compatible = "allwinner,sun4i-a10-ps2";
1131                         reg = <0x01c2a000 0x400>;
1132                         interrupts = <62>;
1133                         clocks = <&apb1_gates 6>;
1134                         status = "disabled";
1135                 };
1136
1137                 ps21: ps2@01c2a400 {
1138                         compatible = "allwinner,sun4i-a10-ps2";
1139                         reg = <0x01c2a400 0x400>;
1140                         interrupts = <63>;
1141                         clocks = <&apb1_gates 7>;
1142                         status = "disabled";
1143                 };
1144         };
1145 };