2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
16 interrupt-parent = <&intc>;
36 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
37 allwinner,pipeline = "de_be0-lcd0-hdmi";
38 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
44 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
45 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
46 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
47 <&ahb_gates 44>, <&ahb_gates 46>;
57 compatible = "arm,cortex-a8";
63 reg = <0x40000000 0x80000000>;
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
74 * yet implemented. It should be dropped when the driver
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 osc24M: clk@01c20050 {
85 compatible = "allwinner,sun4i-a10-osc-clk";
86 reg = <0x01c20050 0x4>;
87 clock-frequency = <24000000>;
88 clock-output-names = "osc24M";
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 clock-output-names = "osc32k";
100 compatible = "allwinner,sun4i-a10-pll1-clk";
101 reg = <0x01c20000 0x4>;
103 clock-output-names = "pll1";
108 compatible = "allwinner,sun4i-a10-pll1-clk";
109 reg = <0x01c20018 0x4>;
111 clock-output-names = "pll4";
116 compatible = "allwinner,sun4i-a10-pll5-clk";
117 reg = <0x01c20020 0x4>;
119 clock-output-names = "pll5_ddr", "pll5_other";
124 compatible = "allwinner,sun4i-a10-pll6-clk";
125 reg = <0x01c20028 0x4>;
127 clock-output-names = "pll6_sata", "pll6_other", "pll6";
133 compatible = "allwinner,sun4i-a10-cpu-clk";
134 reg = <0x01c20054 0x4>;
135 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
136 clock-output-names = "cpu";
141 compatible = "allwinner,sun4i-a10-axi-clk";
142 reg = <0x01c20054 0x4>;
144 clock-output-names = "axi";
147 axi_gates: clk@01c2005c {
149 compatible = "allwinner,sun4i-a10-axi-gates-clk";
150 reg = <0x01c2005c 0x4>;
152 clock-output-names = "axi_dram";
157 compatible = "allwinner,sun4i-a10-ahb-clk";
158 reg = <0x01c20054 0x4>;
160 clock-output-names = "ahb";
163 ahb_gates: clk@01c20060 {
165 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
166 reg = <0x01c20060 0x8>;
168 clock-output-names = "ahb_usb0", "ahb_ehci0",
169 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
170 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
171 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
172 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
173 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
174 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
175 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
176 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
177 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
178 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
181 apb0: apb0@01c20054 {
183 compatible = "allwinner,sun4i-a10-apb0-clk";
184 reg = <0x01c20054 0x4>;
186 clock-output-names = "apb0";
189 apb0_gates: clk@01c20068 {
191 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
192 reg = <0x01c20068 0x4>;
194 clock-output-names = "apb0_codec", "apb0_spdif",
195 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
196 "apb0_ir1", "apb0_keypad";
201 compatible = "allwinner,sun4i-a10-apb1-clk";
202 reg = <0x01c20058 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
204 clock-output-names = "apb1";
207 apb1_gates: clk@01c2006c {
209 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
210 reg = <0x01c2006c 0x4>;
212 clock-output-names = "apb1_i2c0", "apb1_i2c1",
213 "apb1_i2c2", "apb1_can", "apb1_scr",
214 "apb1_ps20", "apb1_ps21", "apb1_uart0",
215 "apb1_uart1", "apb1_uart2", "apb1_uart3",
216 "apb1_uart4", "apb1_uart5", "apb1_uart6",
220 nand_clk: clk@01c20080 {
222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20080 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "nand";
228 ms_clk: clk@01c20084 {
230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c20084 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "ms";
236 mmc0_clk: clk@01c20088 {
238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c20088 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc0";
244 mmc1_clk: clk@01c2008c {
246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c2008c 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc1";
252 mmc2_clk: clk@01c20090 {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20090 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "mmc2";
260 mmc3_clk: clk@01c20094 {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c20094 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "mmc3";
268 ts_clk: clk@01c20098 {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c20098 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "ts";
276 ss_clk: clk@01c2009c {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c2009c 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "ss";
284 spi0_clk: clk@01c200a0 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200a0 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi0";
292 spi1_clk: clk@01c200a4 {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c200a4 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "spi1";
300 spi2_clk: clk@01c200a8 {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200a8 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "spi2";
308 pata_clk: clk@01c200ac {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200ac 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "pata";
316 ir0_clk: clk@01c200b0 {
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c200b0 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "ir0";
324 ir1_clk: clk@01c200b4 {
326 compatible = "allwinner,sun4i-a10-mod0-clk";
327 reg = <0x01c200b4 0x4>;
328 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
329 clock-output-names = "ir1";
332 usb_clk: clk@01c200cc {
335 compatible = "allwinner,sun4i-a10-usb-clk";
336 reg = <0x01c200cc 0x4>;
338 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
341 spi3_clk: clk@01c200d4 {
343 compatible = "allwinner,sun4i-a10-mod0-clk";
344 reg = <0x01c200d4 0x4>;
345 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
346 clock-output-names = "spi3";
351 compatible = "simple-bus";
352 #address-cells = <1>;
356 dma: dma-controller@01c02000 {
357 compatible = "allwinner,sun4i-a10-dma";
358 reg = <0x01c02000 0x1000>;
360 clocks = <&ahb_gates 6>;
365 compatible = "allwinner,sun4i-a10-spi";
366 reg = <0x01c05000 0x1000>;
368 clocks = <&ahb_gates 20>, <&spi0_clk>;
369 clock-names = "ahb", "mod";
370 dmas = <&dma 1 27>, <&dma 1 26>;
371 dma-names = "rx", "tx";
373 #address-cells = <1>;
378 compatible = "allwinner,sun4i-a10-spi";
379 reg = <0x01c06000 0x1000>;
381 clocks = <&ahb_gates 21>, <&spi1_clk>;
382 clock-names = "ahb", "mod";
383 dmas = <&dma 1 9>, <&dma 1 8>;
384 dma-names = "rx", "tx";
386 #address-cells = <1>;
390 emac: ethernet@01c0b000 {
391 compatible = "allwinner,sun4i-a10-emac";
392 reg = <0x01c0b000 0x1000>;
394 clocks = <&ahb_gates 17>;
399 compatible = "allwinner,sun4i-a10-mdio";
400 reg = <0x01c0b080 0x14>;
402 #address-cells = <1>;
407 compatible = "allwinner,sun4i-a10-mmc";
408 reg = <0x01c0f000 0x1000>;
409 clocks = <&ahb_gates 8>, <&mmc0_clk>;
410 clock-names = "ahb", "mmc";
416 compatible = "allwinner,sun4i-a10-mmc";
417 reg = <0x01c10000 0x1000>;
418 clocks = <&ahb_gates 9>, <&mmc1_clk>;
419 clock-names = "ahb", "mmc";
425 compatible = "allwinner,sun4i-a10-mmc";
426 reg = <0x01c11000 0x1000>;
427 clocks = <&ahb_gates 10>, <&mmc2_clk>;
428 clock-names = "ahb", "mmc";
434 compatible = "allwinner,sun4i-a10-mmc";
435 reg = <0x01c12000 0x1000>;
436 clocks = <&ahb_gates 11>, <&mmc3_clk>;
437 clock-names = "ahb", "mmc";
442 usbphy: phy@01c13400 {
444 compatible = "allwinner,sun4i-a10-usb-phy";
445 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
446 reg-names = "phy_ctrl", "pmu1", "pmu2";
447 clocks = <&usb_clk 8>;
448 clock-names = "usb_phy";
449 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
450 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
454 ehci0: usb@01c14000 {
455 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
456 reg = <0x01c14000 0x100>;
458 clocks = <&ahb_gates 1>;
464 ohci0: usb@01c14400 {
465 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
466 reg = <0x01c14400 0x100>;
468 clocks = <&usb_clk 6>, <&ahb_gates 2>;
475 compatible = "allwinner,sun4i-a10-spi";
476 reg = <0x01c17000 0x1000>;
478 clocks = <&ahb_gates 22>, <&spi2_clk>;
479 clock-names = "ahb", "mod";
480 dmas = <&dma 1 29>, <&dma 1 28>;
481 dma-names = "rx", "tx";
483 #address-cells = <1>;
487 ahci: sata@01c18000 {
488 compatible = "allwinner,sun4i-a10-ahci";
489 reg = <0x01c18000 0x1000>;
491 clocks = <&pll6 0>, <&ahb_gates 25>;
495 ehci1: usb@01c1c000 {
496 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
497 reg = <0x01c1c000 0x100>;
499 clocks = <&ahb_gates 3>;
505 ohci1: usb@01c1c400 {
506 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
507 reg = <0x01c1c400 0x100>;
509 clocks = <&usb_clk 7>, <&ahb_gates 4>;
516 compatible = "allwinner,sun4i-a10-spi";
517 reg = <0x01c1f000 0x1000>;
519 clocks = <&ahb_gates 23>, <&spi3_clk>;
520 clock-names = "ahb", "mod";
521 dmas = <&dma 1 31>, <&dma 1 30>;
522 dma-names = "rx", "tx";
524 #address-cells = <1>;
528 intc: interrupt-controller@01c20400 {
529 compatible = "allwinner,sun4i-a10-ic";
530 reg = <0x01c20400 0x400>;
531 interrupt-controller;
532 #interrupt-cells = <1>;
535 pio: pinctrl@01c20800 {
536 compatible = "allwinner,sun4i-a10-pinctrl";
537 reg = <0x01c20800 0x400>;
539 clocks = <&apb0_gates 5>;
541 interrupt-controller;
542 #interrupt-cells = <2>;
546 pwm0_pins_a: pwm0@0 {
547 allwinner,pins = "PB2";
548 allwinner,function = "pwm";
549 allwinner,drive = <0>;
550 allwinner,pull = <0>;
553 pwm1_pins_a: pwm1@0 {
554 allwinner,pins = "PI3";
555 allwinner,function = "pwm";
556 allwinner,drive = <0>;
557 allwinner,pull = <0>;
560 uart0_pins_a: uart0@0 {
561 allwinner,pins = "PB22", "PB23";
562 allwinner,function = "uart0";
563 allwinner,drive = <0>;
564 allwinner,pull = <0>;
567 uart0_pins_b: uart0@1 {
568 allwinner,pins = "PF2", "PF4";
569 allwinner,function = "uart0";
570 allwinner,drive = <0>;
571 allwinner,pull = <0>;
574 uart1_pins_a: uart1@0 {
575 allwinner,pins = "PA10", "PA11";
576 allwinner,function = "uart1";
577 allwinner,drive = <0>;
578 allwinner,pull = <0>;
581 i2c0_pins_a: i2c0@0 {
582 allwinner,pins = "PB0", "PB1";
583 allwinner,function = "i2c0";
584 allwinner,drive = <0>;
585 allwinner,pull = <0>;
588 i2c1_pins_a: i2c1@0 {
589 allwinner,pins = "PB18", "PB19";
590 allwinner,function = "i2c1";
591 allwinner,drive = <0>;
592 allwinner,pull = <0>;
595 i2c2_pins_a: i2c2@0 {
596 allwinner,pins = "PB20", "PB21";
597 allwinner,function = "i2c2";
598 allwinner,drive = <0>;
599 allwinner,pull = <0>;
602 emac_pins_a: emac0@0 {
603 allwinner,pins = "PA0", "PA1", "PA2",
604 "PA3", "PA4", "PA5", "PA6",
605 "PA7", "PA8", "PA9", "PA10",
606 "PA11", "PA12", "PA13", "PA14",
608 allwinner,function = "emac";
609 allwinner,drive = <0>;
610 allwinner,pull = <0>;
613 mmc0_pins_a: mmc0@0 {
614 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
615 allwinner,function = "mmc0";
616 allwinner,drive = <2>;
617 allwinner,pull = <0>;
620 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
621 allwinner,pins = "PH1";
622 allwinner,function = "gpio_in";
623 allwinner,drive = <0>;
624 allwinner,pull = <1>;
628 allwinner,pins = "PB3","PB4";
629 allwinner,function = "ir0";
630 allwinner,drive = <0>;
631 allwinner,pull = <0>;
635 allwinner,pins = "PB22","PB23";
636 allwinner,function = "ir1";
637 allwinner,drive = <0>;
638 allwinner,pull = <0>;
641 spi0_pins_a: spi0@0 {
642 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
643 allwinner,function = "spi0";
644 allwinner,drive = <0>;
645 allwinner,pull = <0>;
648 spi1_pins_a: spi1@0 {
649 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
650 allwinner,function = "spi1";
651 allwinner,drive = <0>;
652 allwinner,pull = <0>;
655 spi2_pins_a: spi2@0 {
656 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
657 allwinner,function = "spi2";
658 allwinner,drive = <0>;
659 allwinner,pull = <0>;
662 spi2_pins_b: spi2@1 {
663 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
664 allwinner,function = "spi2";
665 allwinner,drive = <0>;
666 allwinner,pull = <0>;
671 compatible = "allwinner,sun4i-a10-timer";
672 reg = <0x01c20c00 0x90>;
677 wdt: watchdog@01c20c90 {
678 compatible = "allwinner,sun4i-a10-wdt";
679 reg = <0x01c20c90 0x10>;
683 compatible = "allwinner,sun4i-a10-rtc";
684 reg = <0x01c20d00 0x20>;
689 compatible = "allwinner,sun4i-a10-pwm";
690 reg = <0x01c20e00 0xc>;
697 compatible = "allwinner,sun4i-a10-ir";
698 clocks = <&apb0_gates 6>, <&ir0_clk>;
699 clock-names = "apb", "ir";
701 reg = <0x01c21800 0x40>;
706 compatible = "allwinner,sun4i-a10-ir";
707 clocks = <&apb0_gates 7>, <&ir1_clk>;
708 clock-names = "apb", "ir";
710 reg = <0x01c21c00 0x40>;
714 lradc: lradc@01c22800 {
715 compatible = "allwinner,sun4i-a10-lradc-keys";
716 reg = <0x01c22800 0x100>;
721 sid: eeprom@01c23800 {
722 compatible = "allwinner,sun4i-a10-sid";
723 reg = <0x01c23800 0x10>;
727 compatible = "allwinner,sun4i-a10-ts";
728 reg = <0x01c25000 0x100>;
732 uart0: serial@01c28000 {
733 compatible = "snps,dw-apb-uart";
734 reg = <0x01c28000 0x400>;
738 clocks = <&apb1_gates 16>;
742 uart1: serial@01c28400 {
743 compatible = "snps,dw-apb-uart";
744 reg = <0x01c28400 0x400>;
748 clocks = <&apb1_gates 17>;
752 uart2: serial@01c28800 {
753 compatible = "snps,dw-apb-uart";
754 reg = <0x01c28800 0x400>;
758 clocks = <&apb1_gates 18>;
762 uart3: serial@01c28c00 {
763 compatible = "snps,dw-apb-uart";
764 reg = <0x01c28c00 0x400>;
768 clocks = <&apb1_gates 19>;
772 uart4: serial@01c29000 {
773 compatible = "snps,dw-apb-uart";
774 reg = <0x01c29000 0x400>;
778 clocks = <&apb1_gates 20>;
782 uart5: serial@01c29400 {
783 compatible = "snps,dw-apb-uart";
784 reg = <0x01c29400 0x400>;
788 clocks = <&apb1_gates 21>;
792 uart6: serial@01c29800 {
793 compatible = "snps,dw-apb-uart";
794 reg = <0x01c29800 0x400>;
798 clocks = <&apb1_gates 22>;
802 uart7: serial@01c29c00 {
803 compatible = "snps,dw-apb-uart";
804 reg = <0x01c29c00 0x400>;
808 clocks = <&apb1_gates 23>;
813 compatible = "allwinner,sun4i-a10-i2c";
814 reg = <0x01c2ac00 0x400>;
816 clocks = <&apb1_gates 0>;
818 #address-cells = <1>;
823 compatible = "allwinner,sun4i-a10-i2c";
824 reg = <0x01c2b000 0x400>;
826 clocks = <&apb1_gates 1>;
828 #address-cells = <1>;
833 compatible = "allwinner,sun4i-a10-i2c";
834 reg = <0x01c2b400 0x400>;
836 clocks = <&apb1_gates 2>;
838 #address-cells = <1>;