2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
15 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/dma/sun4i-a10.h>
18 #include <dt-bindings/pinctrl/sun4i-a10.h>
21 interrupt-parent = <&intc>;
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
41 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
42 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
44 <&ahb_gates 44>, <&ahb_gates 46>;
49 compatible = "allwinner,simple-framebuffer",
51 allwinner,pipeline = "de_fe0-de_be0-lcd0";
52 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
58 compatible = "allwinner,simple-framebuffer",
60 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
61 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
62 <&ahb_gates 44>, <&ahb_gates 46>;
72 compatible = "arm,cortex-a8";
75 clock-latency = <244144>; /* 8 32k periods */
85 cooling-min-level = <0>;
86 cooling-max-level = <4>;
93 polling-delay-passive = <250>;
94 polling-delay = <1000>;
95 thermal-sensors = <&rtp>;
100 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
105 cpu_alert0: cpu_alert0 {
107 temperature = <850000>;
114 temperature = <100000>;
123 reg = <0x40000000 0x80000000>;
127 #address-cells = <1>;
132 * This is a dummy clock, to be used as placeholder on
133 * other mux clocks when a specific parent clock is not
134 * yet implemented. It should be dropped when the driver
139 compatible = "fixed-clock";
140 clock-frequency = <0>;
143 osc24M: clk@01c20050 {
145 compatible = "allwinner,sun4i-a10-osc-clk";
146 reg = <0x01c20050 0x4>;
147 clock-frequency = <24000000>;
148 clock-output-names = "osc24M";
153 compatible = "fixed-clock";
154 clock-frequency = <32768>;
155 clock-output-names = "osc32k";
160 compatible = "allwinner,sun4i-a10-pll1-clk";
161 reg = <0x01c20000 0x4>;
163 clock-output-names = "pll1";
168 compatible = "allwinner,sun4i-a10-pll1-clk";
169 reg = <0x01c20018 0x4>;
171 clock-output-names = "pll4";
176 compatible = "allwinner,sun4i-a10-pll5-clk";
177 reg = <0x01c20020 0x4>;
179 clock-output-names = "pll5_ddr", "pll5_other";
184 compatible = "allwinner,sun4i-a10-pll6-clk";
185 reg = <0x01c20028 0x4>;
187 clock-output-names = "pll6_sata", "pll6_other", "pll6";
193 compatible = "allwinner,sun4i-a10-cpu-clk";
194 reg = <0x01c20054 0x4>;
195 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
196 clock-output-names = "cpu";
201 compatible = "allwinner,sun4i-a10-axi-clk";
202 reg = <0x01c20054 0x4>;
204 clock-output-names = "axi";
207 axi_gates: clk@01c2005c {
209 compatible = "allwinner,sun4i-a10-axi-gates-clk";
210 reg = <0x01c2005c 0x4>;
212 clock-output-names = "axi_dram";
217 compatible = "allwinner,sun4i-a10-ahb-clk";
218 reg = <0x01c20054 0x4>;
220 clock-output-names = "ahb";
223 ahb_gates: clk@01c20060 {
225 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
226 reg = <0x01c20060 0x8>;
228 clock-output-names = "ahb_usb0", "ahb_ehci0",
229 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
230 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
231 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
232 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
233 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
234 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
235 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
236 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
237 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
238 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
241 apb0: apb0@01c20054 {
243 compatible = "allwinner,sun4i-a10-apb0-clk";
244 reg = <0x01c20054 0x4>;
246 clock-output-names = "apb0";
249 apb0_gates: clk@01c20068 {
251 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
252 reg = <0x01c20068 0x4>;
254 clock-output-names = "apb0_codec", "apb0_spdif",
255 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
256 "apb0_ir1", "apb0_keypad";
261 compatible = "allwinner,sun4i-a10-apb1-clk";
262 reg = <0x01c20058 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
264 clock-output-names = "apb1";
267 apb1_gates: clk@01c2006c {
269 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
270 reg = <0x01c2006c 0x4>;
272 clock-output-names = "apb1_i2c0", "apb1_i2c1",
273 "apb1_i2c2", "apb1_can", "apb1_scr",
274 "apb1_ps20", "apb1_ps21", "apb1_uart0",
275 "apb1_uart1", "apb1_uart2", "apb1_uart3",
276 "apb1_uart4", "apb1_uart5", "apb1_uart6",
280 nand_clk: clk@01c20080 {
282 compatible = "allwinner,sun4i-a10-mod0-clk";
283 reg = <0x01c20080 0x4>;
284 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
285 clock-output-names = "nand";
288 ms_clk: clk@01c20084 {
290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c20084 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "ms";
296 mmc0_clk: clk@01c20088 {
298 compatible = "allwinner,sun4i-a10-mmc-clk";
299 reg = <0x01c20088 0x4>;
300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clock-output-names = "mmc0",
306 mmc1_clk: clk@01c2008c {
308 compatible = "allwinner,sun4i-a10-mmc-clk";
309 reg = <0x01c2008c 0x4>;
310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
311 clock-output-names = "mmc1",
316 mmc2_clk: clk@01c20090 {
318 compatible = "allwinner,sun4i-a10-mmc-clk";
319 reg = <0x01c20090 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "mmc2",
326 mmc3_clk: clk@01c20094 {
328 compatible = "allwinner,sun4i-a10-mmc-clk";
329 reg = <0x01c20094 0x4>;
330 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
331 clock-output-names = "mmc3",
336 ts_clk: clk@01c20098 {
338 compatible = "allwinner,sun4i-a10-mod0-clk";
339 reg = <0x01c20098 0x4>;
340 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
341 clock-output-names = "ts";
344 ss_clk: clk@01c2009c {
346 compatible = "allwinner,sun4i-a10-mod0-clk";
347 reg = <0x01c2009c 0x4>;
348 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
349 clock-output-names = "ss";
352 spi0_clk: clk@01c200a0 {
354 compatible = "allwinner,sun4i-a10-mod0-clk";
355 reg = <0x01c200a0 0x4>;
356 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
357 clock-output-names = "spi0";
360 spi1_clk: clk@01c200a4 {
362 compatible = "allwinner,sun4i-a10-mod0-clk";
363 reg = <0x01c200a4 0x4>;
364 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
365 clock-output-names = "spi1";
368 spi2_clk: clk@01c200a8 {
370 compatible = "allwinner,sun4i-a10-mod0-clk";
371 reg = <0x01c200a8 0x4>;
372 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
373 clock-output-names = "spi2";
376 pata_clk: clk@01c200ac {
378 compatible = "allwinner,sun4i-a10-mod0-clk";
379 reg = <0x01c200ac 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
381 clock-output-names = "pata";
384 ir0_clk: clk@01c200b0 {
386 compatible = "allwinner,sun4i-a10-mod0-clk";
387 reg = <0x01c200b0 0x4>;
388 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
389 clock-output-names = "ir0";
392 ir1_clk: clk@01c200b4 {
394 compatible = "allwinner,sun4i-a10-mod0-clk";
395 reg = <0x01c200b4 0x4>;
396 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
397 clock-output-names = "ir1";
400 usb_clk: clk@01c200cc {
403 compatible = "allwinner,sun4i-a10-usb-clk";
404 reg = <0x01c200cc 0x4>;
406 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
409 spi3_clk: clk@01c200d4 {
411 compatible = "allwinner,sun4i-a10-mod0-clk";
412 reg = <0x01c200d4 0x4>;
413 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
414 clock-output-names = "spi3";
419 compatible = "simple-bus";
420 #address-cells = <1>;
424 dma: dma-controller@01c02000 {
425 compatible = "allwinner,sun4i-a10-dma";
426 reg = <0x01c02000 0x1000>;
428 clocks = <&ahb_gates 6>;
433 compatible = "allwinner,sun4i-a10-spi";
434 reg = <0x01c05000 0x1000>;
436 clocks = <&ahb_gates 20>, <&spi0_clk>;
437 clock-names = "ahb", "mod";
438 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
439 <&dma SUN4I_DMA_DEDICATED 26>;
440 dma-names = "rx", "tx";
442 #address-cells = <1>;
447 compatible = "allwinner,sun4i-a10-spi";
448 reg = <0x01c06000 0x1000>;
450 clocks = <&ahb_gates 21>, <&spi1_clk>;
451 clock-names = "ahb", "mod";
452 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
453 <&dma SUN4I_DMA_DEDICATED 8>;
454 dma-names = "rx", "tx";
456 #address-cells = <1>;
460 emac: ethernet@01c0b000 {
461 compatible = "allwinner,sun4i-a10-emac";
462 reg = <0x01c0b000 0x1000>;
464 clocks = <&ahb_gates 17>;
468 mdio: mdio@01c0b080 {
469 compatible = "allwinner,sun4i-a10-mdio";
470 reg = <0x01c0b080 0x14>;
472 #address-cells = <1>;
477 compatible = "allwinner,sun4i-a10-mmc";
478 reg = <0x01c0f000 0x1000>;
479 clocks = <&ahb_gates 8>,
492 compatible = "allwinner,sun4i-a10-mmc";
493 reg = <0x01c10000 0x1000>;
494 clocks = <&ahb_gates 9>,
507 compatible = "allwinner,sun4i-a10-mmc";
508 reg = <0x01c11000 0x1000>;
509 clocks = <&ahb_gates 10>,
522 compatible = "allwinner,sun4i-a10-mmc";
523 reg = <0x01c12000 0x1000>;
524 clocks = <&ahb_gates 11>,
536 usbphy: phy@01c13400 {
538 compatible = "allwinner,sun4i-a10-usb-phy";
539 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
540 reg-names = "phy_ctrl", "pmu1", "pmu2";
541 clocks = <&usb_clk 8>;
542 clock-names = "usb_phy";
543 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
544 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
548 ehci0: usb@01c14000 {
549 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
550 reg = <0x01c14000 0x100>;
552 clocks = <&ahb_gates 1>;
558 ohci0: usb@01c14400 {
559 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
560 reg = <0x01c14400 0x100>;
562 clocks = <&usb_clk 6>, <&ahb_gates 2>;
569 compatible = "allwinner,sun4i-a10-spi";
570 reg = <0x01c17000 0x1000>;
572 clocks = <&ahb_gates 22>, <&spi2_clk>;
573 clock-names = "ahb", "mod";
574 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
575 <&dma SUN4I_DMA_DEDICATED 28>;
576 dma-names = "rx", "tx";
578 #address-cells = <1>;
582 ahci: sata@01c18000 {
583 compatible = "allwinner,sun4i-a10-ahci";
584 reg = <0x01c18000 0x1000>;
586 clocks = <&pll6 0>, <&ahb_gates 25>;
590 ehci1: usb@01c1c000 {
591 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
592 reg = <0x01c1c000 0x100>;
594 clocks = <&ahb_gates 3>;
600 ohci1: usb@01c1c400 {
601 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
602 reg = <0x01c1c400 0x100>;
604 clocks = <&usb_clk 7>, <&ahb_gates 4>;
611 compatible = "allwinner,sun4i-a10-spi";
612 reg = <0x01c1f000 0x1000>;
614 clocks = <&ahb_gates 23>, <&spi3_clk>;
615 clock-names = "ahb", "mod";
616 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
617 <&dma SUN4I_DMA_DEDICATED 30>;
618 dma-names = "rx", "tx";
620 #address-cells = <1>;
624 intc: interrupt-controller@01c20400 {
625 compatible = "allwinner,sun4i-a10-ic";
626 reg = <0x01c20400 0x400>;
627 interrupt-controller;
628 #interrupt-cells = <1>;
631 pio: pinctrl@01c20800 {
632 compatible = "allwinner,sun4i-a10-pinctrl";
633 reg = <0x01c20800 0x400>;
635 clocks = <&apb0_gates 5>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
642 pwm0_pins_a: pwm0@0 {
643 allwinner,pins = "PB2";
644 allwinner,function = "pwm";
645 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
646 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
649 pwm1_pins_a: pwm1@0 {
650 allwinner,pins = "PI3";
651 allwinner,function = "pwm";
652 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
653 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
656 uart0_pins_a: uart0@0 {
657 allwinner,pins = "PB22", "PB23";
658 allwinner,function = "uart0";
659 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
660 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
663 uart0_pins_b: uart0@1 {
664 allwinner,pins = "PF2", "PF4";
665 allwinner,function = "uart0";
666 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
667 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
670 uart1_pins_a: uart1@0 {
671 allwinner,pins = "PA10", "PA11";
672 allwinner,function = "uart1";
673 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
674 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
677 i2c0_pins_a: i2c0@0 {
678 allwinner,pins = "PB0", "PB1";
679 allwinner,function = "i2c0";
680 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
681 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
684 i2c1_pins_a: i2c1@0 {
685 allwinner,pins = "PB18", "PB19";
686 allwinner,function = "i2c1";
687 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
688 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
691 i2c2_pins_a: i2c2@0 {
692 allwinner,pins = "PB20", "PB21";
693 allwinner,function = "i2c2";
694 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
698 emac_pins_a: emac0@0 {
699 allwinner,pins = "PA0", "PA1", "PA2",
700 "PA3", "PA4", "PA5", "PA6",
701 "PA7", "PA8", "PA9", "PA10",
702 "PA11", "PA12", "PA13", "PA14",
704 allwinner,function = "emac";
705 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
706 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
709 mmc0_pins_a: mmc0@0 {
710 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
711 allwinner,function = "mmc0";
712 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
713 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
716 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
717 allwinner,pins = "PH1";
718 allwinner,function = "gpio_in";
719 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
720 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
724 allwinner,pins = "PB3","PB4";
725 allwinner,function = "ir0";
726 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
727 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
731 allwinner,pins = "PB22","PB23";
732 allwinner,function = "ir1";
733 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
734 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
737 spi0_pins_a: spi0@0 {
738 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
739 allwinner,function = "spi0";
740 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
741 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
744 spi1_pins_a: spi1@0 {
745 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
746 allwinner,function = "spi1";
747 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
748 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
751 spi2_pins_a: spi2@0 {
752 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
753 allwinner,function = "spi2";
754 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
755 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
758 spi2_pins_b: spi2@1 {
759 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
760 allwinner,function = "spi2";
761 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
762 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
765 ps20_pins_a: ps20@0 {
766 allwinner,pins = "PI20", "PI21";
767 allwinner,function = "ps2";
768 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
769 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
772 ps21_pins_a: ps21@0 {
773 allwinner,pins = "PH12", "PH13";
774 allwinner,function = "ps2";
775 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
776 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
781 compatible = "allwinner,sun4i-a10-timer";
782 reg = <0x01c20c00 0x90>;
787 wdt: watchdog@01c20c90 {
788 compatible = "allwinner,sun4i-a10-wdt";
789 reg = <0x01c20c90 0x10>;
793 compatible = "allwinner,sun4i-a10-rtc";
794 reg = <0x01c20d00 0x20>;
799 compatible = "allwinner,sun4i-a10-pwm";
800 reg = <0x01c20e00 0xc>;
807 compatible = "allwinner,sun4i-a10-ir";
808 clocks = <&apb0_gates 6>, <&ir0_clk>;
809 clock-names = "apb", "ir";
811 reg = <0x01c21800 0x40>;
816 compatible = "allwinner,sun4i-a10-ir";
817 clocks = <&apb0_gates 7>, <&ir1_clk>;
818 clock-names = "apb", "ir";
820 reg = <0x01c21c00 0x40>;
824 lradc: lradc@01c22800 {
825 compatible = "allwinner,sun4i-a10-lradc-keys";
826 reg = <0x01c22800 0x100>;
831 sid: eeprom@01c23800 {
832 compatible = "allwinner,sun4i-a10-sid";
833 reg = <0x01c23800 0x10>;
837 compatible = "allwinner,sun4i-a10-ts";
838 reg = <0x01c25000 0x100>;
840 #thermal-sensor-cells = <0>;
843 uart0: serial@01c28000 {
844 compatible = "snps,dw-apb-uart";
845 reg = <0x01c28000 0x400>;
849 clocks = <&apb1_gates 16>;
853 uart1: serial@01c28400 {
854 compatible = "snps,dw-apb-uart";
855 reg = <0x01c28400 0x400>;
859 clocks = <&apb1_gates 17>;
863 uart2: serial@01c28800 {
864 compatible = "snps,dw-apb-uart";
865 reg = <0x01c28800 0x400>;
869 clocks = <&apb1_gates 18>;
873 uart3: serial@01c28c00 {
874 compatible = "snps,dw-apb-uart";
875 reg = <0x01c28c00 0x400>;
879 clocks = <&apb1_gates 19>;
883 uart4: serial@01c29000 {
884 compatible = "snps,dw-apb-uart";
885 reg = <0x01c29000 0x400>;
889 clocks = <&apb1_gates 20>;
893 uart5: serial@01c29400 {
894 compatible = "snps,dw-apb-uart";
895 reg = <0x01c29400 0x400>;
899 clocks = <&apb1_gates 21>;
903 uart6: serial@01c29800 {
904 compatible = "snps,dw-apb-uart";
905 reg = <0x01c29800 0x400>;
909 clocks = <&apb1_gates 22>;
913 uart7: serial@01c29c00 {
914 compatible = "snps,dw-apb-uart";
915 reg = <0x01c29c00 0x400>;
919 clocks = <&apb1_gates 23>;
924 compatible = "allwinner,sun4i-a10-i2c";
925 reg = <0x01c2ac00 0x400>;
927 clocks = <&apb1_gates 0>;
929 #address-cells = <1>;
934 compatible = "allwinner,sun4i-a10-i2c";
935 reg = <0x01c2b000 0x400>;
937 clocks = <&apb1_gates 1>;
939 #address-cells = <1>;
944 compatible = "allwinner,sun4i-a10-i2c";
945 reg = <0x01c2b400 0x400>;
947 clocks = <&apb1_gates 2>;
949 #address-cells = <1>;
954 compatible = "allwinner,sun4i-a10-ps2";
955 reg = <0x01c2a000 0x400>;
957 clocks = <&apb1_gates 6>;
962 compatible = "allwinner,sun4i-a10-ps2";
963 reg = <0x01c2a400 0x400>;
965 clocks = <&apb1_gates 7>;