arch/arm/boot/dts/stih407-pinctrl.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "st-pincfg.h"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 / {
  12
  13         aliases {
  14                 /* 0-5: PIO_SBC */
  15                 gpio0 = &pio0;
  16                 gpio1 = &pio1;
  17                 gpio2 = &pio2;
  18                 gpio3 = &pio3;
  19                 gpio4 = &pio4;
  20                 gpio5 = &pio5;
  21                 /* 10-19: PIO_FRONT0 */
  22                 gpio6 = &pio10;
  23                 gpio7 = &pio11;
  24                 gpio8 = &pio12;
  25                 gpio9 = &pio13;
  26                 gpio10 = &pio14;
  27                 gpio11 = &pio15;
  28                 gpio12 = &pio16;
  29                 gpio13 = &pio17;
  30                 gpio14 = &pio18;
  31                 gpio15 = &pio19;
  32                 /* 20: PIO_FRONT1 */
  33                 gpio16 = &pio20;
  34                 /* 30-35: PIO_REAR */
  35                 gpio17 = &pio30;
  36                 gpio18 = &pio31;
  37                 gpio19 = &pio32;
  38                 gpio20 = &pio33;
  39                 gpio21 = &pio34;
  40                 gpio22 = &pio35;
  41                 /* 40-42: PIO_FLASH */
  42                 gpio23 = &pio40;
  43                 gpio24 = &pio41;
  44                 gpio25 = &pio42;
  45         };
  46
  47         soc {
  48                 pin-controller-sbc {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         compatible = "st,stih407-sbc-pinctrl";
  52                         st,syscfg = <&syscfg_sbc>;
  53                         reg = <0x0961f080 0x4>;
  54                         reg-names = "irqmux";
  55                         interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
  56                         interrupts-names = "irqmux";
  57                         ranges = <0 0x09610000 0x6000>;
  58
  59                         pio0: gpio@09610000 {
  60                                 gpio-controller;
  61                                 #gpio-cells = <1>;
  62                                 interrupt-controller;
  63                                 #interrupt-cells = <2>;
  64                                 reg = <0x0 0x100>;
  65                                 st,bank-name = "PIO0";
  66                         };
  67                         pio1: gpio@09611000 {
  68                                 gpio-controller;
  69                                 #gpio-cells = <1>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <2>;
  72                                 reg = <0x1000 0x100>;
  73                                 st,bank-name = "PIO1";
  74                         };
  75                         pio2: gpio@09612000 {
  76                                 gpio-controller;
  77                                 #gpio-cells = <1>;
  78                                 interrupt-controller;
  79                                 #interrupt-cells = <2>;
  80                                 reg = <0x2000 0x100>;
  81                                 st,bank-name = "PIO2";
  82                         };
  83                         pio3: gpio@09613000 {
  84                                 gpio-controller;
  85                                 #gpio-cells = <1>;
  86                                 interrupt-controller;
  87                                 #interrupt-cells = <2>;
  88                                 reg = <0x3000 0x100>;
  89                                 st,bank-name = "PIO3";
  90                         };
  91                         pio4: gpio@09614000 {
  92                                 gpio-controller;
  93                                 #gpio-cells = <1>;
  94                                 interrupt-controller;
  95                                 #interrupt-cells = <2>;
  96                                 reg = <0x4000 0x100>;
  97                                 st,bank-name = "PIO4";
  98                         };
  99
 100                         pio5: gpio@09615000 {
 101                                 gpio-controller;
 102                                 #gpio-cells = <1>;
 103                                 interrupt-controller;
 104                                 #interrupt-cells = <2>;
 105                                 reg = <0x5000 0x100>;
 106                                 st,bank-name = "PIO5";
 107                                 st,retime-pin-mask = <0x3f>;
 108                         };
 109
 110                         cec0 {
 111                                 pinctrl_cec0_default: cec0-default {
 112                                         st,pins {
 113                                                 hdmi_cec = <&pio2 4 ALT1 BIDIR>;
 114                                         };
 115                                 };
 116                         };
 117
 118                         rc {
 119                                 pinctrl_ir: ir0 {
 120                                         st,pins {
 121                                                 ir = <&pio4 0 ALT2 IN>;
 122                                         };
 123                                 };
 124
 125                                 pinctrl_uhf: uhf0 {
 126                                         st,pins {
 127                                                 ir = <&pio4 1 ALT2 IN>;
 128                                         };
 129                                 };
 130
 131                                 pinctrl_tx: tx0 {
 132                                         st,pins {
 133                                                 tx = <&pio4 2 ALT2 OUT>;
 134                                         };
 135                                 };
 136
 137                                 pinctrl_tx_od: tx_od0 {
 138                                         st,pins {
 139                                                 tx_od = <&pio4 3 ALT2 OUT>;
 140                                         };
 141                                 };
 142                         };
 143
 144                         /* SBC_ASC0 - UART10 */
 145                         sbc_serial0 {
 146                                 pinctrl_sbc_serial0: sbc_serial0-0 {
 147                                         st,pins {
 148                                                 tx = <&pio3 4 ALT1 OUT>;
 149                                                 rx = <&pio3 5 ALT1 IN>;
 150                                         };
 151                                 };
 152                         };
 153                         /* SBC_ASC1 - UART11 */
 154                         sbc_serial1 {
 155                                 pinctrl_sbc_serial1: sbc_serial1-0 {
 156                                         st,pins {
 157                                                 tx = <&pio2 6 ALT3 OUT>;
 158                                                 rx = <&pio2 7 ALT3 IN>;
 159                                         };
 160                                 };
 161                         };
 162
 163                         i2c10 {
 164                                 pinctrl_i2c10_default: i2c10-default {
 165                                         st,pins {
 166                                                 sda = <&pio4 6 ALT1 BIDIR>;
 167                                                 scl = <&pio4 5 ALT1 BIDIR>;
 168                                         };
 169                                 };
 170                         };
 171
 172                         i2c11 {
 173                                 pinctrl_i2c11_default: i2c11-default {
 174                                         st,pins {
 175                                                 sda = <&pio5 1 ALT1 BIDIR>;
 176                                                 scl = <&pio5 0 ALT1 BIDIR>;
 177                                         };
 178                                 };
 179                         };
 180
 181                         keyscan {
 182                                 pinctrl_keyscan: keyscan {
 183                                         st,pins {
 184                                                 keyin0 = <&pio4 0 ALT6 IN>;
 185                                                 keyin1 = <&pio4 5 ALT4 IN>;
 186                                                 keyin2 = <&pio0 4 ALT2 IN>;
 187                                                 keyin3 = <&pio2 6 ALT2 IN>;
 188
 189                                                 keyout0 = <&pio4 6 ALT4 OUT>;
 190                                                 keyout1 = <&pio1 7 ALT2 OUT>;
 191                                                 keyout2 = <&pio0 6 ALT2 OUT>;
 192                                                 keyout3 = <&pio2 7 ALT2 OUT>;
 193                                         };
 194                                 };
 195                         };
 196
 197                         gmac1 {
 198                                 /*
 199                                  * Almost all the boards based on STiH407 SoC have an embedded
 200                                  * switch where the mdio/mdc have been used for managing the SMI
 201                                  * iface via I2C. For this reason these lines can be allocated
 202                                  * by using dedicated configuration (in case of there will be a
 203                                  * standard PHY transceiver on-board).
 204                                  */
 205                                 pinctrl_rgmii1: rgmii1-0 {
 206                                         st,pins {
 207
 208                                                 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
 209                                                 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
 210                                                 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
 211                                                 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
 212                                                 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
 213                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 214                                                 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
 215                                                 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
 216                                                 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
 217                                                 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
 218                                                 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
 219                                                 rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
 220                                                 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
 221                                                 phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
 222                                         };
 223                                 };
 224
 225                                 pinctrl_rgmii1_mdio: rgmii1-mdio {
 226                                         st,pins {
 227                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
 228                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 229                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 230                                         };
 231                                 };
 232
 233                                 pinctrl_mii1: mii1 {
 234                                         st,pins {
 235                                                 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 236                                                 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 237                                                 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 238                                                 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 239                                                 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 240                                                 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 241                                                 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
 242                                                 col = <&pio0 7 ALT1 IN BYPASS 1000>;
 243
 244                                                 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
 245                                                 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
 246                                                 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
 247                                                 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
 248                                                 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 249                                                 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 250                                                 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 251                                                 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 252
 253                                                 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 254                                                 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 255                                                 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
 256                                                 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
 257                                         };
 258                                 };
 259                         };
 260
 261                         pwm1 {
 262                                 pinctrl_pwm1_chan0_default: pwm1-0-default {
 263                                         st,pins {
 264                                                 pwm-out = <&pio3 0 ALT1 OUT>;
 265                                         };
 266                                 };
 267                                 pinctrl_pwm1_chan1_default: pwm1-1-default {
 268                                         st,pins {
 269                                                 pwm-out = <&pio4 4 ALT1 OUT>;
 270                                         };
 271                                 };
 272                                 pinctrl_pwm1_chan2_default: pwm1-2-default {
 273                                         st,pins {
 274                                                 pwm-out = <&pio4 6 ALT3 OUT>;
 275                                         };
 276                                 };
 277                                 pinctrl_pwm1_chan3_default: pwm1-3-default {
 278                                         st,pins {
 279                                                 pwm-out = <&pio4 7 ALT3 OUT>;
 280                                         };
 281                                 };
 282                         };
 283
 284                         spi10 {
 285                                 pinctrl_spi10_default: spi10-4w-alt1-0 {
 286                                         st,pins {
 287                                                 mtsr = <&pio4 6 ALT1 OUT>;
 288                                                 mrst = <&pio4 7 ALT1 IN>;
 289                                                 scl = <&pio4 5 ALT1 OUT>;
 290                                         };
 291                                 };
 292
 293                                 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
 294                                         st,pins {
 295                                                 mtsr = <&pio4 6 ALT1 BIDIR_PU>;
 296                                                 scl = <&pio4 5 ALT1 OUT>;
 297                                         };
 298                                 };
 299                         };
 300
 301                         spi11 {
 302                                 pinctrl_spi11_default: spi11-4w-alt2-0 {
 303                                         st,pins {
 304                                                 mtsr = <&pio3 1 ALT2 OUT>;
 305                                                 mrst = <&pio3 0 ALT2 IN>;
 306                                                 scl = <&pio3 2 ALT2 OUT>;
 307                                         };
 308                                 };
 309
 310                                 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
 311                                         st,pins {
 312                                                 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
 313                                                 scl = <&pio3 2 ALT2 OUT>;
 314                                         };
 315                                 };
 316                         };
 317
 318                         spi12 {
 319                                 pinctrl_spi12_default: spi12-4w-alt2-0 {
 320                                         st,pins {
 321                                                 mtsr = <&pio3 6 ALT2 OUT>;
 322                                                 mrst = <&pio3 4 ALT2 IN>;
 323                                                 scl = <&pio3 7 ALT2 OUT>;
 324                                         };
 325                                 };
 326
 327                                 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
 328                                         st,pins {
 329                                                 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
 330                                                 scl = <&pio3 7 ALT2 OUT>;
 331                                         };
 332                                 };
 333                         };
 334                 };
 335
 336                 pin-controller-front0 {
 337                         #address-cells = <1>;
 338                         #size-cells = <1>;
 339                         compatible = "st,stih407-front-pinctrl";
 340                         st,syscfg = <&syscfg_front>;
 341                         reg = <0x0920f080 0x4>;
 342                         reg-names = "irqmux";
 343                         interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
 344                         interrupts-names = "irqmux";
 345                         ranges = <0 0x09200000 0x10000>;
 346
 347                         pio10: pio@09200000 {
 348                                 gpio-controller;
 349                                 #gpio-cells = <1>;
 350                                 interrupt-controller;
 351                                 #interrupt-cells = <2>;
 352                                 reg = <0x0 0x100>;
 353                                 st,bank-name = "PIO10";
 354                         };
 355                         pio11: pio@09201000 {
 356                                 gpio-controller;
 357                                 #gpio-cells = <1>;
 358                                 interrupt-controller;
 359                                 #interrupt-cells = <2>;
 360                                 reg = <0x1000 0x100>;
 361                                 st,bank-name = "PIO11";
 362                         };
 363                         pio12: pio@09202000 {
 364                                 gpio-controller;
 365                                 #gpio-cells = <1>;
 366                                 interrupt-controller;
 367                                 #interrupt-cells = <2>;
 368                                 reg = <0x2000 0x100>;
 369                                 st,bank-name = "PIO12";
 370                         };
 371                         pio13: pio@09203000 {
 372                                 gpio-controller;
 373                                 #gpio-cells = <1>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <2>;
 376                                 reg = <0x3000 0x100>;
 377                                 st,bank-name = "PIO13";
 378                         };
 379                         pio14: pio@09204000 {
 380                                 gpio-controller;
 381                                 #gpio-cells = <1>;
 382                                 interrupt-controller;
 383                                 #interrupt-cells = <2>;
 384                                 reg = <0x4000 0x100>;
 385                                 st,bank-name = "PIO14";
 386                         };
 387                         pio15: pio@09205000 {
 388                                 gpio-controller;
 389                                 #gpio-cells = <1>;
 390                                 interrupt-controller;
 391                                 #interrupt-cells = <2>;
 392                                 reg = <0x5000 0x100>;
 393                                 st,bank-name = "PIO15";
 394                         };
 395                         pio16: pio@09206000 {
 396                                 gpio-controller;
 397                                 #gpio-cells = <1>;
 398                                 interrupt-controller;
 399                                 #interrupt-cells = <2>;
 400                                 reg = <0x6000 0x100>;
 401                                 st,bank-name = "PIO16";
 402                         };
 403                         pio17: pio@09207000 {
 404                                 gpio-controller;
 405                                 #gpio-cells = <1>;
 406                                 interrupt-controller;
 407                                 #interrupt-cells = <2>;
 408                                 reg = <0x7000 0x100>;
 409                                 st,bank-name = "PIO17";
 410                         };
 411                         pio18: pio@09208000 {
 412                                 gpio-controller;
 413                                 #gpio-cells = <1>;
 414                                 interrupt-controller;
 415                                 #interrupt-cells = <2>;
 416                                 reg = <0x8000 0x100>;
 417                                 st,bank-name = "PIO18";
 418                         };
 419                         pio19: pio@09209000 {
 420                                 gpio-controller;
 421                                 #gpio-cells = <1>;
 422                                 interrupt-controller;
 423                                 #interrupt-cells = <2>;
 424                                 reg = <0x9000 0x100>;
 425                                 st,bank-name = "PIO19";
 426                         };
 427
 428                         /* Comms */
 429                         serial0 {
 430                                 pinctrl_serial0: serial0-0 {
 431                                         st,pins {
 432                                                 tx = <&pio17 0 ALT1 OUT>;
 433                                                 rx = <&pio17 1 ALT1 IN>;
 434                                         };
 435                                 };
 436                         };
 437
 438                         serial1 {
 439                                 pinctrl_serial1: serial1-0 {
 440                                         st,pins {
 441                                                 tx = <&pio16 0 ALT1 OUT>;
 442                                                 rx = <&pio16 1 ALT1 IN>;
 443                                         };
 444                                 };
 445                         };
 446
 447                         serial2 {
 448                                 pinctrl_serial2: serial2-0 {
 449                                         st,pins {
 450                                                 tx = <&pio15 0 ALT1 OUT>;
 451                                                 rx = <&pio15 1 ALT1 IN>;
 452                                         };
 453                                 };
 454                         };
 455
 456                         mmc1 {
 457                                 pinctrl_sd1: sd1-0 {
 458                                         st,pins {
 459                                                 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
 460                                                 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
 461                                                 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
 462                                                 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
 463                                                 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
 464                                                 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
 465                                                 sd_led = <&pio16 6 ALT6 OUT>;
 466                                                 sd_pwren = <&pio16 7 ALT6 OUT>;
 467                                                 sd_cd = <&pio19 0 ALT6 IN>;
 468                                                 sd_wp = <&pio19 1 ALT6 IN>;
 469                                         };
 470                                 };
 471                         };
 472
 473
 474                         i2c0 {
 475                                 pinctrl_i2c0_default: i2c0-default {
 476                                         st,pins {
 477                                                 sda = <&pio10 6 ALT2 BIDIR>;
 478                                                 scl = <&pio10 5 ALT2 BIDIR>;
 479                                         };
 480                                 };
 481                         };
 482
 483                         i2c1 {
 484                                 pinctrl_i2c1_default: i2c1-default {
 485                                         st,pins {
 486                                                 sda = <&pio11 1 ALT2 BIDIR>;
 487                                                 scl = <&pio11 0 ALT2 BIDIR>;
 488                                         };
 489                                 };
 490                         };
 491
 492                         i2c2 {
 493                                 pinctrl_i2c2_default: i2c2-default {
 494                                         st,pins {
 495                                                 sda = <&pio15 6 ALT2 BIDIR>;
 496                                                 scl = <&pio15 5 ALT2 BIDIR>;
 497                                         };
 498                                 };
 499                         };
 500
 501                         i2c3 {
 502                                 pinctrl_i2c3_default: i2c3-alt1-0 {
 503                                         st,pins {
 504                                                 sda = <&pio18 6 ALT1 BIDIR>;
 505                                                 scl = <&pio18 5 ALT1 BIDIR>;
 506                                         };
 507                                 };
 508                                 pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
 509                                         st,pins {
 510                                                 sda = <&pio17 7 ALT1 BIDIR>;
 511                                                 scl = <&pio17 6 ALT1 BIDIR>;
 512                                         };
 513                                 };
 514                                 pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
 515                                         st,pins {
 516                                                 sda = <&pio13 6 ALT3 BIDIR>;
 517                                                 scl = <&pio13 5 ALT3 BIDIR>;
 518                                         };
 519                                 };
 520                         };
 521
 522                         spi0 {
 523                                 pinctrl_spi0_default: spi0-4w-alt2-0 {
 524                                         st,pins {
 525                                                 mtsr = <&pio10 6 ALT2 OUT>;
 526                                                 mrst = <&pio10 7 ALT2 IN>;
 527                                                 scl = <&pio10 5 ALT2 OUT>;
 528                                         };
 529                                 };
 530
 531                                 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
 532                                         st,pins {
 533                                                 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
 534                                                 scl = <&pio10 5 ALT2 OUT>;
 535                                         };
 536                                 };
 537
 538                                 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
 539                                         st,pins {
 540                                                 mtsr = <&pio19 7 ALT1 OUT>;
 541                                                 mrst = <&pio19 5 ALT1 IN>;
 542                                                 scl = <&pio19 6 ALT1 OUT>;
 543                                         };
 544                                 };
 545
 546                                 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
 547                                         st,pins {
 548                                                 mtsr = <&pio19 7 ALT1 BIDIR_PU>;
 549                                                 scl = <&pio19 6 ALT1 OUT>;
 550                                         };
 551                                 };
 552                         };
 553
 554                         spi1 {
 555                                 pinctrl_spi1_default: spi1-4w-alt2-0 {
 556                                         st,pins {
 557                                                 mtsr = <&pio11 1 ALT2 OUT>;
 558                                                 mrst = <&pio11 2 ALT2 IN>;
 559                                                 scl = <&pio11 0 ALT2 OUT>;
 560                                         };
 561                                 };
 562
 563                                 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
 564                                         st,pins {
 565                                                 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
 566                                                 scl = <&pio11 0 ALT2 OUT>;
 567                                         };
 568                                 };
 569
 570                                 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
 571                                         st,pins {
 572                                                 mtsr = <&pio14 3 ALT1 OUT>;
 573                                                 mrst = <&pio14 4 ALT1 IN>;
 574                                                 scl = <&pio14 2 ALT1 OUT>;
 575                                         };
 576                                 };
 577
 578                                 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
 579                                         st,pins {
 580                                                 mtsr = <&pio14 3 ALT1 BIDIR_PU>;
 581                                                 scl = <&pio14 2 ALT1 OUT>;
 582                                         };
 583                                 };
 584                         };
 585
 586                         spi2 {
 587                                 pinctrl_spi2_default: spi2-4w-alt2-0 {
 588                                         st,pins {
 589                                                 mtsr = <&pio12 6 ALT2 OUT>;
 590                                                 mrst = <&pio12 7 ALT2 IN>;
 591                                                 scl = <&pio12 5 ALT2 OUT>;
 592                                         };
 593                                 };
 594
 595                                 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
 596                                         st,pins {
 597                                                 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
 598                                                 scl = <&pio12 5 ALT2 OUT>;
 599                                         };
 600                                 };
 601
 602                                 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
 603                                         st,pins {
 604                                                 mtsr = <&pio14 6 ALT1 OUT>;
 605                                                 mrst = <&pio14 7 ALT1 IN>;
 606                                                 scl = <&pio14 5 ALT1 OUT>;
 607                                         };
 608                                 };
 609
 610                                 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
 611                                         st,pins {
 612                                                 mtsr = <&pio14 6 ALT1 BIDIR_PU>;
 613                                                 scl = <&pio14 5 ALT1 OUT>;
 614                                         };
 615                                 };
 616
 617                                 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
 618                                         st,pins {
 619                                                 mtsr = <&pio15 6 ALT2 OUT>;
 620                                                 mrst = <&pio15 7 ALT2 IN>;
 621                                                 scl = <&pio15 5 ALT2 OUT>;
 622                                         };
 623                                 };
 624
 625                                 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
 626                                         st,pins {
 627                                                 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
 628                                                 scl = <&pio15 5 ALT2 OUT>;
 629                                         };
 630                                 };
 631                         };
 632
 633                         spi3 {
 634                                 pinctrl_spi3_default: spi3-4w-alt3-0 {
 635                                         st,pins {
 636                                                 mtsr = <&pio13 6 ALT3 OUT>;
 637                                                 mrst = <&pio13 7 ALT3 IN>;
 638                                                 scl = <&pio13 5 ALT3 OUT>;
 639                                         };
 640                                 };
 641
 642                                 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
 643                                         st,pins {
 644                                                 mtsr = <&pio13 6 ALT3 BIDIR_PU>;
 645                                                 scl = <&pio13 5 ALT3 OUT>;
 646                                         };
 647                                 };
 648
 649                                 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
 650                                         st,pins {
 651                                                 mtsr = <&pio17 7 ALT1 OUT>;
 652                                                 mrst = <&pio17 5 ALT1 IN>;
 653                                                 scl = <&pio17 6 ALT1 OUT>;
 654                                         };
 655                                 };
 656
 657                                 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
 658                                         st,pins {
 659                                                 mtsr = <&pio17 7 ALT1 BIDIR_PU>;
 660                                                 scl = <&pio17 6 ALT1 OUT>;
 661                                         };
 662                                 };
 663
 664                                 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
 665                                         st,pins {
 666                                                 mtsr = <&pio18 6 ALT1 OUT>;
 667                                                 mrst = <&pio18 7 ALT1 IN>;
 668                                                 scl = <&pio18 5 ALT1 OUT>;
 669                                         };
 670                                 };
 671
 672                                 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
 673                                         st,pins {
 674                                                 mtsr = <&pio18 6 ALT1 BIDIR_PU>;
 675                                                 scl = <&pio18 5 ALT1 OUT>;
 676                                         };
 677                                 };
 678                         };
 679
 680                         tsin0 {
 681                                 pinctrl_tsin0_parallel: tsin0_parallel {
 682                                         st,pins {
 683                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 684                                                 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 685                                                 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 686                                                 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 687                                                 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 688                                                 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 689                                                 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 690                                                 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 691                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 692                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 693                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 694                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 695                                         };
 696                                 };
 697                                 pinctrl_tsin0_serial: tsin0_serial {
 698                                         st,pins {
 699                                                 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 700                                                 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 701                                                 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 702                                                 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 703                                                 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 704                                         };
 705                                 };
 706                         };
 707
 708                         tsin1 {
 709                                 pinctrl_tsin1_parallel: tsin1_parallel {
 710                                         st,pins {
 711                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 712                                                 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 713                                                 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 714                                                 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 715                                                 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 716                                                 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 717                                                 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 718                                                 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 719                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 720                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 721                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 722                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 723                                         };
 724                                 };
 725                                 pinctrl_tsin1_serial: tsin1_serial {
 726                                         st,pins {
 727                                                 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 728                                                 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
 729                                                 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 730                                                 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 731                                                 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 732                                         };
 733                                 };
 734                         };
 735
 736                         tsin2 {
 737                                 pinctrl_tsin2_parallel: tsin2_parallel {
 738                                         st,pins {
 739                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 740                                                 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 741                                                 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 742                                                 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 743                                                 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 744                                                 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
 745                                                 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 746                                                 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 747                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 748                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 749                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 750                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 751                                         };
 752                                 };
 753                                 pinctrl_tsin2_serial: tsin2_serial {
 754                                         st,pins {
 755                                                 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 756                                                 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 757                                                 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 758                                                 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 759                                                 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 760                                         };
 761                                 };
 762                         };
 763
 764                         tsin3 {
 765                                 pinctrl_tsin3_serial: tsin3_serial {
 766                                         st,pins {
 767                                                 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 768                                                 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
 769                                                 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 770                                                 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 771                                                 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 772                                         };
 773                                 };
 774                         };
 775
 776                         tsin4 {
 777                                 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
 778                                         st,pins {
 779                                                 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 780                                                 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
 781                                                 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 782                                                 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
 783                                                 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 784                                         };
 785                                 };
 786                         };
 787
 788                         tsin5 {
 789                                 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
 790                                         st,pins {
 791                                                 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 792                                                 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 793                                                 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 794                                                 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 795                                                 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 796                                         };
 797                                 };
 798                                 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
 799                                         st,pins {
 800                                                 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 801                                                 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
 802                                                 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 803                                                 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 804                                                 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
 805                                         };
 806                                 };
 807                         };
 808
 809                         tsout0 {
 810                                 pinctrl_tsout0_parallel: tsout0_parallel {
 811                                         st,pins {
 812                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 813                                                 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 814                                                 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 815                                                 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 816                                                 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 817                                                 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 818                                                 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 819                                                 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 820                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 821                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 822                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 823                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 824                                         };
 825                                 };
 826                                 pinctrl_tsout0_serial: tsout0_serial {
 827                                         st,pins {
 828                                                 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 829                                                 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
 830                                                 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 831                                                 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 832                                                 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
 833                                         };
 834                                 };
 835                         };
 836
 837                         tsout1 {
 838                                 pinctrl_tsout1_serial: tsout1_serial {
 839                                         st,pins {
 840                                                 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 841                                                 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
 842                                                 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 843                                                 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 844                                                 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
 845                                         };
 846                                 };
 847                         };
 848
 849                         mtsin0 {
 850                                 pinctrl_mtsin0_parallel: mtsin0_parallel {
 851                                         st,pins {
 852                                                 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 853                                                 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 854                                                 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 855                                                 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 856                                                 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 857                                                 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 858                                                 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 859                                                 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 860                                                 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
 861                                                 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 862                                                 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 863                                                 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
 864                                         };
 865                                 };
 866                         };
 867
 868                         systrace {
 869                                 pinctrl_systrace_default: systrace-default {
 870                                         st,pins {
 871                                                 trc_data0 = <&pio11 3 ALT5 OUT>;
 872                                                 trc_data1 = <&pio11 4 ALT5 OUT>;
 873                                                 trc_data2 = <&pio11 5 ALT5 OUT>;
 874                                                 trc_data3 = <&pio11 6 ALT5 OUT>;
 875                                                 trc_clk   = <&pio11 7 ALT5 OUT>;
 876                                         };
 877                                 };
 878                         };
 879                 };
 880
 881                 pin-controller-front1 {
 882                         #address-cells = <1>;
 883                         #size-cells = <1>;
 884                         compatible = "st,stih407-front-pinctrl";
 885                         st,syscfg = <&syscfg_front>;
 886                         reg = <0x0921f080 0x4>;
 887                         reg-names = "irqmux";
 888                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 889                         interrupts-names = "irqmux";
 890                         ranges = <0 0x09210000 0x10000>;
 891
 892                         tsin4 {
 893                                 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
 894                                         st,pins {
 895                                                 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 896                                                 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
 897                                                 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 898                                                 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 899                                                 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
 900                                         };
 901                                 };
 902                         };
 903
 904                         pio20: pio@09210000 {
 905                                 gpio-controller;
 906                                 #gpio-cells = <1>;
 907                                 interrupt-controller;
 908                                 #interrupt-cells = <2>;
 909                                 reg = <0x0 0x100>;
 910                                 st,bank-name = "PIO20";
 911                         };
 912                 };
 913
 914                 pin-controller-rear {
 915                         #address-cells = <1>;
 916                         #size-cells = <1>;
 917                         compatible = "st,stih407-rear-pinctrl";
 918                         st,syscfg = <&syscfg_rear>;
 919                         reg = <0x0922f080 0x4>;
 920                         reg-names = "irqmux";
 921                         interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
 922                         interrupts-names = "irqmux";
 923                         ranges = <0 0x09220000 0x6000>;
 924
 925                         pio30: gpio@09220000 {
 926                                 gpio-controller;
 927                                 #gpio-cells = <1>;
 928                                 interrupt-controller;
 929                                 #interrupt-cells = <2>;
 930                                 reg = <0x0 0x100>;
 931                                 st,bank-name = "PIO30";
 932                         };
 933                         pio31: gpio@09221000 {
 934                                 gpio-controller;
 935                                 #gpio-cells = <1>;
 936                                 interrupt-controller;
 937                                 #interrupt-cells = <2>;
 938                                 reg = <0x1000 0x100>;
 939                                 st,bank-name = "PIO31";
 940                         };
 941                         pio32: gpio@09222000 {
 942                                 gpio-controller;
 943                                 #gpio-cells = <1>;
 944                                 interrupt-controller;
 945                                 #interrupt-cells = <2>;
 946                                 reg = <0x2000 0x100>;
 947                                 st,bank-name = "PIO32";
 948                         };
 949                         pio33: gpio@09223000 {
 950                                 gpio-controller;
 951                                 #gpio-cells = <1>;
 952                                 interrupt-controller;
 953                                 #interrupt-cells = <2>;
 954                                 reg = <0x3000 0x100>;
 955                                 st,bank-name = "PIO33";
 956                         };
 957                         pio34: gpio@09224000 {
 958                                 gpio-controller;
 959                                 #gpio-cells = <1>;
 960                                 interrupt-controller;
 961                                 #interrupt-cells = <2>;
 962                                 reg = <0x4000 0x100>;
 963                                 st,bank-name = "PIO34";
 964                         };
 965                         pio35: gpio@09225000 {
 966                                 gpio-controller;
 967                                 #gpio-cells = <1>;
 968                                 interrupt-controller;
 969                                 #interrupt-cells = <2>;
 970                                 reg = <0x5000 0x100>;
 971                                 st,bank-name = "PIO35";
 972                                 st,retime-pin-mask = <0x7f>;
 973                         };
 974
 975                         i2c4 {
 976                                 pinctrl_i2c4_default: i2c4-default {
 977                                         st,pins {
 978                                                 sda = <&pio30 1 ALT1 BIDIR>;
 979                                                 scl = <&pio30 0 ALT1 BIDIR>;
 980                                         };
 981                                 };
 982                         };
 983
 984                         i2c5 {
 985                                 pinctrl_i2c5_default: i2c5-default {
 986                                         st,pins {
 987                                                 sda = <&pio34 4 ALT1 BIDIR>;
 988                                                 scl = <&pio34 3 ALT1 BIDIR>;
 989                                         };
 990                                 };
 991                         };
 992
 993                         usb3 {
 994                                 pinctrl_usb3: usb3-2 {
 995                                         st,pins {
 996                                                 usb-oc-detect = <&pio35 4 ALT1 IN>;
 997                                                 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
 998                                                 usb-vbus-valid = <&pio35 6 ALT1 IN>;
 999                                         };
1000                                 };
1001                         };
1002
1003                         pwm0 {
1004                                 pinctrl_pwm0_chan0_default: pwm0-0-default {
1005                                         st,pins {
1006                                                 pwm-out = <&pio31 1 ALT1 OUT>;
1007                                         };
1008                                 };
1009                         };
1010
1011                         spi4 {
1012                                 pinctrl_spi4_default: spi4-4w-alt1-0 {
1013                                         st,pins {
1014                                                 mtsr = <&pio30 1 ALT1 OUT>;
1015                                                 mrst = <&pio30 2 ALT1 IN>;
1016                                                 scl = <&pio30 0 ALT1 OUT>;
1017                                         };
1018                                 };
1019
1020                                 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
1021                                         st,pins {
1022                                                 mtsr = <&pio30 1 ALT1 BIDIR_PU>;
1023                                                 scl = <&pio30 0 ALT1 OUT>;
1024                                         };
1025                                 };
1026
1027                                 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
1028                                         st,pins {
1029                                                 mtsr = <&pio34 1 ALT3 OUT>;
1030                                                 mrst = <&pio34 2 ALT3 IN>;
1031                                                 scl = <&pio34 0 ALT3 OUT>;
1032                                         };
1033                                 };
1034
1035                                 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1036                                         st,pins {
1037                                                 mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1038                                                 scl = <&pio34 0 ALT3 OUT>;
1039                                         };
1040                                 };
1041                         };
1042
1043                         serial3 {
1044                                 pinctrl_serial3: serial3-0 {
1045                                         st,pins {
1046                                                 tx = <&pio31 3 ALT1 OUT>;
1047                                                 rx = <&pio31 4 ALT1 IN>;
1048                                         };
1049                                 };
1050                         };
1051                 };
1052
1053                 pin-controller-flash {
1054                         #address-cells = <1>;
1055                         #size-cells = <1>;
1056                         compatible = "st,stih407-flash-pinctrl";
1057                         st,syscfg = <&syscfg_flash>;
1058                         reg = <0x0923f080 0x4>;
1059                         reg-names = "irqmux";
1060                         interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
1061                         interrupts-names = "irqmux";
1062                         ranges = <0 0x09230000 0x3000>;
1063
1064                         pio40: gpio@09230000 {
1065                                 gpio-controller;
1066                                 #gpio-cells = <1>;
1067                                 interrupt-controller;
1068                                 #interrupt-cells = <2>;
1069                                 reg = <0 0x100>;
1070                                 st,bank-name = "PIO40";
1071                         };
1072                         pio41: gpio@09231000 {
1073                                 gpio-controller;
1074                                 #gpio-cells = <1>;
1075                                 interrupt-controller;
1076                                 #interrupt-cells = <2>;
1077                                 reg = <0x1000 0x100>;
1078                                 st,bank-name = "PIO41";
1079                         };
1080                         pio42: gpio@09232000 {
1081                                 gpio-controller;
1082                                 #gpio-cells = <1>;
1083                                 interrupt-controller;
1084                                 #interrupt-cells = <2>;
1085                                 reg = <0x2000 0x100>;
1086                                 st,bank-name = "PIO42";
1087                         };
1088
1089                         mmc0 {
1090                                 pinctrl_mmc0: mmc0-0 {
1091                                         st,pins {
1092                                                 emmc_clk = <&pio40 6 ALT1 BIDIR>;
1093                                                 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1094                                                 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1095                                                 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1096                                                 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1097                                                 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1098                                                 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1099                                                 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1100                                                 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1101                                                 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1102                                         };
1103                                 };
1104                                 pinctrl_sd0: sd0-0 {
1105                                         st,pins {
1106                                                 sd_clk = <&pio40 6 ALT1 BIDIR>;
1107                                                 sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1108                                                 sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
1109                                                 sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
1110                                                 sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
1111                                                 sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
1112                                                 sd_led = <&pio42 0 ALT2 OUT>;
1113                                                 sd_pwren = <&pio42 2 ALT2 OUT>;
1114                                                 sd_vsel = <&pio42 3 ALT2 OUT>;
1115                                                 sd_cd = <&pio42 4 ALT2 IN>;
1116                                                 sd_wp = <&pio42 5 ALT2 IN>;
1117                                         };
1118                                 };
1119                         };
1120
1121                         fsm {
1122                                 pinctrl_fsm: fsm {
1123                                         st,pins {
1124                                                 spi-fsm-clk = <&pio40 1 ALT1 OUT>;
1125                                                 spi-fsm-cs = <&pio40 0 ALT1 OUT>;
1126                                                 spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
1127                                                 spi-fsm-miso = <&pio40 3 ALT1 IN>;
1128                                                 spi-fsm-hol = <&pio40 5 ALT1 OUT>;
1129                                                 spi-fsm-wp = <&pio40 4 ALT1 OUT>;
1130                                         };
1131                                 };
1132                         };
1133
1134                         nand {
1135                                 pinctrl_nand: nand {
1136                                         st,pins {
1137                                                 nand_cs1 = <&pio40 6 ALT3 OUT>;
1138                                                 nand_cs0 = <&pio40 7 ALT3 OUT>;
1139                                                 nand_d0 = <&pio41 0 ALT3 BIDIR>;
1140                                                 nand_d1 = <&pio41 1 ALT3 BIDIR>;
1141                                                 nand_d2 = <&pio41 2 ALT3 BIDIR>;
1142                                                 nand_d3 = <&pio41 3 ALT3 BIDIR>;
1143                                                 nand_d4 = <&pio41 4 ALT3 BIDIR>;
1144                                                 nand_d5 = <&pio41 5 ALT3 BIDIR>;
1145                                                 nand_d6 = <&pio41 6 ALT3 BIDIR>;
1146                                                 nand_d7 = <&pio41 7 ALT3 BIDIR>;
1147                                                 nand_we = <&pio42 0 ALT3 OUT>;
1148                                                 nand_dqs = <&pio42 1 ALT3 OUT>;
1149                                                 nand_ale = <&pio42 2 ALT3 OUT>;
1150                                                 nand_cle = <&pio42 3 ALT3 OUT>;
1151                                                 nand_rnb = <&pio42 4 ALT3 IN>;
1152                                                 nand_oe = <&pio42 5 ALT3 OUT>;
1153                                         };
1154                                 };
1155                         };
1156                 };
1157         };
1158 };