arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &gmac0;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 timer0 = &timer0;
  29                 timer1 = &timer1;
  30                 timer2 = &timer2;
  31                 timer3 = &timer3;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,cortex-a9";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                         next-level-cache = <&L2>;
  43                 };
  44                 cpu@1 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         reg = <1>;
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         intc: intc@fffed000 {
  53                 compatible = "arm,cortex-a9-gic";
  54                 #interrupt-cells = <3>;
  55                 interrupt-controller;
  56                 reg = <0xfffed000 0x1000>,
  57                       <0xfffec100 0x100>;
  58         };
  59
  60         soc {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 compatible = "simple-bus";
  64                 device_type = "soc";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 amba {
  69                         compatible = "arm,amba-bus";
  70                         #address-cells = <1>;
  71                         #size-cells = <1>;
  72                         ranges;
  73
  74                         pdma: pdma@ffe01000 {
  75                                 compatible = "arm,pl330", "arm,primecell";
  76                                 reg = <0xffe01000 0x1000>;
  77                                 interrupts = <0 180 4>;
  78                                 #dma-cells = <1>;
  79                                 #dma-channels = <8>;
  80                                 #dma-requests = <32>;
  81                         };
  82                 };
  83
  84                 gmac0: stmmac@ff700000 {
  85                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  86                         reg = <0xff700000 0x2000>;
  87                         interrupts = <0 115 4>;
  88                         interrupt-names = "macirq";
  89                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
  90                         phy-mode = "gmii";
  91                 };
  92
  93                 L2: l2-cache@fffef000 {
  94                         compatible = "arm,pl310-cache";
  95                         reg = <0xfffef000 0x1000>;
  96                         interrupts = <0 38 0x04>;
  97                         cache-unified;
  98                         cache-level = <2>;
  99                 };
 100
 101                 /* Local timer */
 102                 timer@fffec600 {
 103                         compatible = "arm,cortex-a9-twd-timer";
 104                         reg = <0xfffec600 0x100>;
 105                         interrupts = <1 13 0xf04>;
 106                 };
 107
 108                 timer0: timer0@ffc08000 {
 109                         compatible = "snps,dw-apb-timer-sp";
 110                         interrupts = <0 167 4>;
 111                         reg = <0xffc08000 0x1000>;
 112                 };
 113
 114                 timer1: timer1@ffc09000 {
 115                         compatible = "snps,dw-apb-timer-sp";
 116                         interrupts = <0 168 4>;
 117                         reg = <0xffc09000 0x1000>;
 118                 };
 119
 120                 timer2: timer2@ffd00000 {
 121                         compatible = "snps,dw-apb-timer-osc";
 122                         interrupts = <0 169 4>;
 123                         reg = <0xffd00000 0x1000>;
 124                 };
 125
 126                 timer3: timer3@ffd01000 {
 127                         compatible = "snps,dw-apb-timer-osc";
 128                         interrupts = <0 170 4>;
 129                         reg = <0xffd01000 0x1000>;
 130                 };
 131
 132                 uart0: serial0@ffc02000 {
 133                         compatible = "snps,dw-apb-uart";
 134                         reg = <0xffc02000 0x1000>;
 135                         interrupts = <0 162 4>;
 136                         reg-shift = <2>;
 137                         reg-io-width = <4>;
 138                 };
 139
 140                 uart1: serial1@ffc03000 {
 141                         compatible = "snps,dw-apb-uart";
 142                         reg = <0xffc03000 0x1000>;
 143                         interrupts = <0 163 4>;
 144                         reg-shift = <2>;
 145                         reg-io-width = <4>;
 146                 };
 147
 148                 rstmgr@ffd05000 {
 149                                 compatible = "altr,rst-mgr";
 150                                 reg = <0xffd05000 0x1000>;
 151                         };
 152
 153                 sysmgr@ffd08000 {
 154                                 compatible = "altr,sys-mgr";
 155                                 reg = <0xffd08000 0x4000>;
 156                         };
 157         };
 158 };