arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &gmac0;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28                 timer0 = &timer0;
  29                 timer1 = &timer1;
  30                 timer2 = &timer2;
  31                 timer3 = &timer3;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,cortex-a9";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                         next-level-cache = <&L2>;
  43                 };
  44                 cpu@1 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         reg = <1>;
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         intc: intc@fffed000 {
  53                 compatible = "arm,cortex-a9-gic";
  54                 #interrupt-cells = <3>;
  55                 interrupt-controller;
  56                 reg = <0xfffed000 0x1000>,
  57                       <0xfffec100 0x100>;
  58         };
  59
  60         soc {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 compatible = "simple-bus";
  64                 device_type = "soc";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 amba {
  69                         compatible = "arm,amba-bus";
  70                         #address-cells = <1>;
  71                         #size-cells = <1>;
  72                         ranges;
  73
  74                         pdma: pdma@ffe01000 {
  75                                 compatible = "arm,pl330", "arm,primecell";
  76                                 reg = <0xffe01000 0x1000>;
  77                                 interrupts = <0 180 4>;
  78                                 #dma-cells = <1>;
  79                                 #dma-channels = <8>;
  80                                 #dma-requests = <32>;
  81                         };
  82                 };
  83
  84                 clkmgr@ffd04000 {
  85                                 compatible = "altr,clk-mgr";
  86                                 reg = <0xffd04000 0x1000>;
  87
  88                                 clocks {
  89                                         #address-cells = <1>;
  90                                         #size-cells = <0>;
  91
  92                                         osc: osc1 {
  93                                                 #clock-cells = <0>;
  94                                                 compatible = "fixed-clock";
  95                                         };
  96
  97                                         main_pll: main_pll {
  98                                                 #address-cells = <1>;
  99                                                 #size-cells = <0>;
 100                                                 #clock-cells = <0>;
 101                                                 compatible = "altr,socfpga-pll-clock";
 102                                                 clocks = <&osc>;
 103                                                 reg = <0x40>;
 104
 105                                                 mpuclk: mpuclk {
 106                                                         #clock-cells = <0>;
 107                                                         compatible = "altr,socfpga-perip-clk";
 108                                                         clocks = <&main_pll>;
 109                                                         fixed-divider = <2>;
 110                                                         reg = <0x48>;
 111                                                 };
 112
 113                                                 mainclk: mainclk {
 114                                                         #clock-cells = <0>;
 115                                                         compatible = "altr,socfpga-perip-clk";
 116                                                         clocks = <&main_pll>;
 117                                                         fixed-divider = <4>;
 118                                                         reg = <0x4C>;
 119                                                 };
 120
 121                                                 dbg_base_clk: dbg_base_clk {
 122                                                         #clock-cells = <0>;
 123                                                         compatible = "altr,socfpga-perip-clk";
 124                                                         clocks = <&main_pll>;
 125                                                         fixed-divider = <4>;
 126                                                         reg = <0x50>;
 127                                                 };
 128
 129                                                 main_qspi_clk: main_qspi_clk {
 130                                                         #clock-cells = <0>;
 131                                                         compatible = "altr,socfpga-perip-clk";
 132                                                         clocks = <&main_pll>;
 133                                                         reg = <0x54>;
 134                                                 };
 135
 136                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
 137                                                         #clock-cells = <0>;
 138                                                         compatible = "altr,socfpga-perip-clk";
 139                                                         clocks = <&main_pll>;
 140                                                         reg = <0x58>;
 141                                                 };
 142
 143                                                 cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
 144                                                         #clock-cells = <0>;
 145                                                         compatible = "altr,socfpga-perip-clk";
 146                                                         clocks = <&main_pll>;
 147                                                         reg = <0x5C>;
 148                                                 };
 149                                         };
 150
 151                                         periph_pll: periph_pll {
 152                                                 #address-cells = <1>;
 153                                                 #size-cells = <0>;
 154                                                 #clock-cells = <0>;
 155                                                 compatible = "altr,socfpga-pll-clock";
 156                                                 clocks = <&osc>;
 157                                                 reg = <0x80>;
 158
 159                                                 emac0_clk: emac0_clk {
 160                                                         #clock-cells = <0>;
 161                                                         compatible = "altr,socfpga-perip-clk";
 162                                                         clocks = <&periph_pll>;
 163                                                         reg = <0x88>;
 164                                                 };
 165
 166                                                 emac1_clk: emac1_clk {
 167                                                         #clock-cells = <0>;
 168                                                         compatible = "altr,socfpga-perip-clk";
 169                                                         clocks = <&periph_pll>;
 170                                                         reg = <0x8C>;
 171                                                 };
 172
 173                                                 per_qspi_clk: per_qsi_clk {
 174                                                         #clock-cells = <0>;
 175                                                         compatible = "altr,socfpga-perip-clk";
 176                                                         clocks = <&periph_pll>;
 177                                                         reg = <0x90>;
 178                                                 };
 179
 180                                                 per_nand_mmc_clk: per_nand_mmc_clk {
 181                                                         #clock-cells = <0>;
 182                                                         compatible = "altr,socfpga-perip-clk";
 183                                                         clocks = <&periph_pll>;
 184                                                         reg = <0x94>;
 185                                                 };
 186
 187                                                 per_base_clk: per_base_clk {
 188                                                         #clock-cells = <0>;
 189                                                         compatible = "altr,socfpga-perip-clk";
 190                                                         clocks = <&periph_pll>;
 191                                                         reg = <0x98>;
 192                                                 };
 193
 194                                                 s2f_usr1_clk: s2f_usr1_clk {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-perip-clk";
 197                                                         clocks = <&periph_pll>;
 198                                                         reg = <0x9C>;
 199                                                 };
 200                                         };
 201
 202                                         sdram_pll: sdram_pll {
 203                                                 #address-cells = <1>;
 204                                                 #size-cells = <0>;
 205                                                 #clock-cells = <0>;
 206                                                 compatible = "altr,socfpga-pll-clock";
 207                                                 clocks = <&osc>;
 208                                                 reg = <0xC0>;
 209
 210                                                 ddr_dqs_clk: ddr_dqs_clk {
 211                                                         #clock-cells = <0>;
 212                                                         compatible = "altr,socfpga-perip-clk";
 213                                                         clocks = <&sdram_pll>;
 214                                                         reg = <0xC8>;
 215                                                 };
 216
 217                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
 218                                                         #clock-cells = <0>;
 219                                                         compatible = "altr,socfpga-perip-clk";
 220                                                         clocks = <&sdram_pll>;
 221                                                         reg = <0xCC>;
 222                                                 };
 223
 224                                                 ddr_dq_clk: ddr_dq_clk {
 225                                                         #clock-cells = <0>;
 226                                                         compatible = "altr,socfpga-perip-clk";
 227                                                         clocks = <&sdram_pll>;
 228                                                         reg = <0xD0>;
 229                                                 };
 230
 231                                                 s2f_usr2_clk: s2f_usr2_clk {
 232                                                         #clock-cells = <0>;
 233                                                         compatible = "altr,socfpga-perip-clk";
 234                                                         clocks = <&sdram_pll>;
 235                                                         reg = <0xD4>;
 236                                                 };
 237                                         };
 238                                 };
 239                         };
 240
 241                 gmac0: stmmac@ff700000 {
 242                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 243                         reg = <0xff700000 0x2000>;
 244                         interrupts = <0 115 4>;
 245                         interrupt-names = "macirq";
 246                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 247                         phy-mode = "gmii";
 248                 };
 249
 250                 L2: l2-cache@fffef000 {
 251                         compatible = "arm,pl310-cache";
 252                         reg = <0xfffef000 0x1000>;
 253                         interrupts = <0 38 0x04>;
 254                         cache-unified;
 255                         cache-level = <2>;
 256                 };
 257
 258                 /* Local timer */
 259                 timer@fffec600 {
 260                         compatible = "arm,cortex-a9-twd-timer";
 261                         reg = <0xfffec600 0x100>;
 262                         interrupts = <1 13 0xf04>;
 263                 };
 264
 265                 timer0: timer0@ffc08000 {
 266                         compatible = "snps,dw-apb-timer-sp";
 267                         interrupts = <0 167 4>;
 268                         reg = <0xffc08000 0x1000>;
 269                 };
 270
 271                 timer1: timer1@ffc09000 {
 272                         compatible = "snps,dw-apb-timer-sp";
 273                         interrupts = <0 168 4>;
 274                         reg = <0xffc09000 0x1000>;
 275                 };
 276
 277                 timer2: timer2@ffd00000 {
 278                         compatible = "snps,dw-apb-timer-osc";
 279                         interrupts = <0 169 4>;
 280                         reg = <0xffd00000 0x1000>;
 281                 };
 282
 283                 timer3: timer3@ffd01000 {
 284                         compatible = "snps,dw-apb-timer-osc";
 285                         interrupts = <0 170 4>;
 286                         reg = <0xffd01000 0x1000>;
 287                 };
 288
 289                 uart0: serial0@ffc02000 {
 290                         compatible = "snps,dw-apb-uart";
 291                         reg = <0xffc02000 0x1000>;
 292                         interrupts = <0 162 4>;
 293                         reg-shift = <2>;
 294                         reg-io-width = <4>;
 295                 };
 296
 297                 uart1: serial1@ffc03000 {
 298                         compatible = "snps,dw-apb-uart";
 299                         reg = <0xffc03000 0x1000>;
 300                         interrupts = <0 163 4>;
 301                         reg-shift = <2>;
 302                         reg-io-width = <4>;
 303                 };
 304
 305                 rstmgr@ffd05000 {
 306                                 compatible = "altr,rst-mgr";
 307                                 reg = <0xffd05000 0x1000>;
 308                         };
 309
 310                 sysmgr@ffd08000 {
 311                                 compatible = "altr,sys-mgr";
 312                                 reg = <0xffd08000 0x4000>;
 313                         };
 314         };
 315 };