arch/arm/boot/dts/sh73a0.dtsi

   1 /*
   2  * Device Tree Source for the SH73A0 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/sh73a0-clock.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,sh73a0";
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         reg = <0>;
  28                         clock-frequency = <1196000000>;
  29                 };
  30                 cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <1>;
  34                         clock-frequency = <1196000000>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@f0001000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xf0001000 0x1000>,
  43                       <0xf0000100 0x100>;
  44         };
  45
  46         sbsc2: memory-controller@fb400000 {
  47                 compatible = "renesas,sbsc-sh73a0";
  48                 reg = <0xfb400000 0x400>;
  49                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
  50                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
  51                 interrupt-names = "sec", "temp";
  52         };
  53
  54         sbsc1: memory-controller@fe400000 {
  55                 compatible = "renesas,sbsc-sh73a0";
  56                 reg = <0xfe400000 0x400>;
  57                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
  58                              <0 36 IRQ_TYPE_LEVEL_HIGH>;
  59                 interrupt-names = "sec", "temp";
  60         };
  61
  62         pmu {
  63                 compatible = "arm,cortex-a9-pmu";
  64                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
  65                              <0 56 IRQ_TYPE_LEVEL_HIGH>;
  66         };
  67
  68         cmt1: timer@e6138000 {
  69                 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
  70                 reg = <0xe6138000 0x200>;
  71                 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
  72
  73                 renesas,channels-mask = <0x3f>;
  74
  75                 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
  76                 clock-names = "fck";
  77                 status = "disabled";
  78         };
  79
  80         irqpin0: irqpin@e6900000 {
  81                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
  82                 #interrupt-cells = <2>;
  83                 interrupt-controller;
  84                 reg = <0xe6900000 4>,
  85                         <0xe6900010 4>,
  86                         <0xe6900020 1>,
  87                         <0xe6900040 1>,
  88                         <0xe6900060 1>;
  89                 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
  90                               0 2 IRQ_TYPE_LEVEL_HIGH
  91                               0 3 IRQ_TYPE_LEVEL_HIGH
  92                               0 4 IRQ_TYPE_LEVEL_HIGH
  93                               0 5 IRQ_TYPE_LEVEL_HIGH
  94                               0 6 IRQ_TYPE_LEVEL_HIGH
  95                               0 7 IRQ_TYPE_LEVEL_HIGH
  96                               0 8 IRQ_TYPE_LEVEL_HIGH>;
  97                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
  98                 control-parent;
  99         };
 100
 101         irqpin1: irqpin@e6900004 {
 102                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 reg = <0xe6900004 4>,
 106                         <0xe6900014 4>,
 107                         <0xe6900024 1>,
 108                         <0xe6900044 1>,
 109                         <0xe6900064 1>;
 110                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
 111                               0 10 IRQ_TYPE_LEVEL_HIGH
 112                               0 11 IRQ_TYPE_LEVEL_HIGH
 113                               0 12 IRQ_TYPE_LEVEL_HIGH
 114                               0 13 IRQ_TYPE_LEVEL_HIGH
 115                               0 14 IRQ_TYPE_LEVEL_HIGH
 116                               0 15 IRQ_TYPE_LEVEL_HIGH
 117                               0 16 IRQ_TYPE_LEVEL_HIGH>;
 118                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 119                 control-parent;
 120         };
 121
 122         irqpin2: irqpin@e6900008 {
 123                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 124                 #interrupt-cells = <2>;
 125                 interrupt-controller;
 126                 reg = <0xe6900008 4>,
 127                         <0xe6900018 4>,
 128                         <0xe6900028 1>,
 129                         <0xe6900048 1>,
 130                         <0xe6900068 1>;
 131                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
 132                               0 18 IRQ_TYPE_LEVEL_HIGH
 133                               0 19 IRQ_TYPE_LEVEL_HIGH
 134                               0 20 IRQ_TYPE_LEVEL_HIGH
 135                               0 21 IRQ_TYPE_LEVEL_HIGH
 136                               0 22 IRQ_TYPE_LEVEL_HIGH
 137                               0 23 IRQ_TYPE_LEVEL_HIGH
 138                               0 24 IRQ_TYPE_LEVEL_HIGH>;
 139                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 140                 control-parent;
 141         };
 142
 143         irqpin3: irqpin@e690000c {
 144                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 reg = <0xe690000c 4>,
 148                         <0xe690001c 4>,
 149                         <0xe690002c 1>,
 150                         <0xe690004c 1>,
 151                         <0xe690006c 1>;
 152                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
 153                               0 26 IRQ_TYPE_LEVEL_HIGH
 154                               0 27 IRQ_TYPE_LEVEL_HIGH
 155                               0 28 IRQ_TYPE_LEVEL_HIGH
 156                               0 29 IRQ_TYPE_LEVEL_HIGH
 157                               0 30 IRQ_TYPE_LEVEL_HIGH
 158                               0 31 IRQ_TYPE_LEVEL_HIGH
 159                               0 32 IRQ_TYPE_LEVEL_HIGH>;
 160                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 161                 control-parent;
 162         };
 163
 164         i2c0: i2c@e6820000 {
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 168                 reg = <0xe6820000 0x425>;
 169                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
 170                               0 168 IRQ_TYPE_LEVEL_HIGH
 171                               0 169 IRQ_TYPE_LEVEL_HIGH
 172                               0 170 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 174                 status = "disabled";
 175         };
 176
 177         i2c1: i2c@e6822000 {
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 181                 reg = <0xe6822000 0x425>;
 182                 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
 183                               0 52 IRQ_TYPE_LEVEL_HIGH
 184                               0 53 IRQ_TYPE_LEVEL_HIGH
 185                               0 54 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 187                 status = "disabled";
 188         };
 189
 190         i2c2: i2c@e6824000 {
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 194                 reg = <0xe6824000 0x425>;
 195                 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
 196                               0 172 IRQ_TYPE_LEVEL_HIGH
 197                               0 173 IRQ_TYPE_LEVEL_HIGH
 198                               0 174 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 200                 status = "disabled";
 201         };
 202
 203         i2c3: i2c@e6826000 {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 207                 reg = <0xe6826000 0x425>;
 208                 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
 209                               0 184 IRQ_TYPE_LEVEL_HIGH
 210                               0 185 IRQ_TYPE_LEVEL_HIGH
 211                               0 186 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 213                 status = "disabled";
 214         };
 215
 216         i2c4: i2c@e6828000 {
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 220                 reg = <0xe6828000 0x425>;
 221                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
 222                               0 188 IRQ_TYPE_LEVEL_HIGH
 223                               0 189 IRQ_TYPE_LEVEL_HIGH
 224                               0 190 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 226                 status = "disabled";
 227         };
 228
 229         mmcif: mmc@e6bd0000 {
 230                 compatible = "renesas,sh-mmcif";
 231                 reg = <0xe6bd0000 0x100>;
 232                 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
 233                               0 141 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 235                 reg-io-width = <4>;
 236                 status = "disabled";
 237         };
 238
 239         sdhi0: sd@ee100000 {
 240                 compatible = "renesas,sdhi-sh73a0";
 241                 reg = <0xee100000 0x100>;
 242                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
 243                               0 84 IRQ_TYPE_LEVEL_HIGH
 244                               0 85 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 246                 cap-sd-highspeed;
 247                 status = "disabled";
 248         };
 249
 250         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
 251         sdhi1: sd@ee120000 {
 252                 compatible = "renesas,sdhi-sh73a0";
 253                 reg = <0xee120000 0x100>;
 254                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
 255                               0 89 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 257                 toshiba,mmc-wrprotect-disable;
 258                 cap-sd-highspeed;
 259                 status = "disabled";
 260         };
 261
 262         sdhi2: sd@ee140000 {
 263                 compatible = "renesas,sdhi-sh73a0";
 264                 reg = <0xee140000 0x100>;
 265                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
 266                               0 105 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 268                 toshiba,mmc-wrprotect-disable;
 269                 cap-sd-highspeed;
 270                 status = "disabled";
 271         };
 272
 273         scifa0: serial@e6c40000 {
 274                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 275                 reg = <0xe6c40000 0x100>;
 276                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 277                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 278                 clock-names = "sci_ick";
 279                 status = "disabled";
 280         };
 281
 282         scifa1: serial@e6c50000 {
 283                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 284                 reg = <0xe6c50000 0x100>;
 285                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 287                 clock-names = "sci_ick";
 288                 status = "disabled";
 289         };
 290
 291         scifa2: serial@e6c60000 {
 292                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 293                 reg = <0xe6c60000 0x100>;
 294                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 296                 clock-names = "sci_ick";
 297                 status = "disabled";
 298         };
 299
 300         scifa3: serial@e6c70000 {
 301                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 302                 reg = <0xe6c70000 0x100>;
 303                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 305                 clock-names = "sci_ick";
 306                 status = "disabled";
 307         };
 308
 309         scifa4: serial@e6c80000 {
 310                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 311                 reg = <0xe6c80000 0x100>;
 312                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 314                 clock-names = "sci_ick";
 315                 status = "disabled";
 316         };
 317
 318         scifa5: serial@e6cb0000 {
 319                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 320                 reg = <0xe6cb0000 0x100>;
 321                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 323                 clock-names = "sci_ick";
 324                 status = "disabled";
 325         };
 326
 327         scifa6: serial@e6cc0000 {
 328                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 329                 reg = <0xe6cc0000 0x100>;
 330                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 332                 clock-names = "sci_ick";
 333                 status = "disabled";
 334         };
 335
 336         scifa7: serial@e6cd0000 {
 337                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 338                 reg = <0xe6cd0000 0x100>;
 339                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 341                 clock-names = "sci_ick";
 342                 status = "disabled";
 343         };
 344
 345         scifb8: serial@e6c30000 {
 346                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 347                 reg = <0xe6c30000 0x100>;
 348                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 350                 clock-names = "sci_ick";
 351                 status = "disabled";
 352         };
 353
 354         pfc: pfc@e6050000 {
 355                 compatible = "renesas,pfc-sh73a0";
 356                 reg = <0xe6050000 0x8000>,
 357                       <0xe605801c 0x1c>;
 358                 gpio-controller;
 359                 #gpio-cells = <2>;
 360                 interrupts-extended =
 361                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 362                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 363                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 364                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 365                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 366                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 367                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 368                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 369         };
 370
 371         sh_fsi2: sound@ec230000 {
 372                 #sound-dai-cells = <1>;
 373                 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 374                 reg = <0xec230000 0x400>;
 375                 interrupts = <0 146 0x4>;
 376                 status = "disabled";
 377         };
 378
 379         clocks {
 380                 #address-cells = <1>;
 381                 #size-cells = <1>;
 382                 ranges;
 383
 384                 /* External root clocks */
 385                 extalr_clk: extalr_clk {
 386                         compatible = "fixed-clock";
 387                         #clock-cells = <0>;
 388                         clock-frequency = <32768>;
 389                         clock-output-names = "extalr";
 390                 };
 391                 extal1_clk: extal1_clk {
 392                         compatible = "fixed-clock";
 393                         #clock-cells = <0>;
 394                         clock-frequency = <26000000>;
 395                         clock-output-names = "extal1";
 396                 };
 397                 extal2_clk: extal2_clk {
 398                         compatible = "fixed-clock";
 399                         #clock-cells = <0>;
 400                         clock-output-names = "extal2";
 401                 };
 402                 extcki_clk: extcki_clk {
 403                         compatible = "fixed-clock";
 404                         #clock-cells = <0>;
 405                         clock-output-names = "extcki";
 406                 };
 407                 fsiack_clk: fsiack_clk {
 408                         compatible = "fixed-clock";
 409                         #clock-cells = <0>;
 410                         clock-frequency = <0>;
 411                         clock-output-names = "fsiack";
 412                 };
 413                 fsibck_clk: fsibck_clk {
 414                         compatible = "fixed-clock";
 415                         #clock-cells = <0>;
 416                         clock-frequency = <0>;
 417                         clock-output-names = "fsibck";
 418                 };
 419
 420                 /* Special CPG clocks */
 421                 cpg_clocks: cpg_clocks@e6150000 {
 422                         compatible = "renesas,sh73a0-cpg-clocks";
 423                         reg = <0xe6150000 0x10000>;
 424                         clocks = <&extal1_clk>, <&extal2_clk>;
 425                         #clock-cells = <1>;
 426                         clock-output-names = "main", "pll0", "pll1", "pll2",
 427                                              "pll3", "dsi0phy", "dsi1phy",
 428                                              "zg", "m3", "b", "m1", "m2",
 429                                              "z", "zx", "hp";
 430                 };
 431
 432                 /* Variable factor clocks (DIV6) */
 433                 vclk1_clk: vclk1_clk@e6150008 {
 434                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 435                         reg = <0xe6150008 4>;
 436                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 437                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 438                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 439                                  <0>;
 440                         #clock-cells = <0>;
 441                         clock-output-names = "vclk1";
 442                 };
 443                 vclk2_clk: vclk2_clk@e615000c {
 444                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 445                         reg = <0xe615000c 4>;
 446                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 447                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 448                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 449                                  <0>;
 450                         #clock-cells = <0>;
 451                         clock-output-names = "vclk2";
 452                 };
 453                 vclk3_clk: vclk3_clk@e615001c {
 454                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 455                         reg = <0xe615001c 4>;
 456                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 457                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 458                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 459                                  <0>;
 460                         #clock-cells = <0>;
 461                         clock-output-names = "vclk3";
 462                 };
 463                 zb_clk: zb_clk@e6150010 {
 464                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 465                         reg = <0xe6150010 4>;
 466                         clocks = <&pll1_div2_clk>, <0>,
 467                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 468                         #clock-cells = <0>;
 469                         clock-output-names = "zb";
 470                 };
 471                 flctl_clk: flctl_clk@e6150014 {
 472                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 473                         reg = <0xe6150014 4>;
 474                         clocks = <&pll1_div2_clk>, <0>,
 475                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 476                         #clock-cells = <0>;
 477                         clock-output-names = "flctlck";
 478                 };
 479                 sdhi0_clk: sdhi0_clk@e6150074 {
 480                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 481                         reg = <0xe6150074 4>;
 482                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 483                                  <&pll1_div13_clk>, <0>;
 484                         #clock-cells = <0>;
 485                         clock-output-names = "sdhi0ck";
 486                 };
 487                 sdhi1_clk: sdhi1_clk@e6150078 {
 488                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 489                         reg = <0xe6150078 4>;
 490                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 491                                  <&pll1_div13_clk>, <0>;
 492                         #clock-cells = <0>;
 493                         clock-output-names = "sdhi1ck";
 494                 };
 495                 sdhi2_clk: sdhi2_clk@e615007c {
 496                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 497                         reg = <0xe615007c 4>;
 498                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 499                                  <&pll1_div13_clk>, <0>;
 500                         #clock-cells = <0>;
 501                         clock-output-names = "sdhi2ck";
 502                 };
 503                 fsia_clk: fsia_clk@e6150018 {
 504                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 505                         reg = <0xe6150018 4>;
 506                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 507                                  <&fsiack_clk>, <&fsiack_clk>;
 508                         #clock-cells = <0>;
 509                         clock-output-names = "fsia";
 510                 };
 511                 fsib_clk: fsib_clk@e6150090 {
 512                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 513                         reg = <0xe6150090 4>;
 514                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 515                                  <&fsibck_clk>, <&fsibck_clk>;
 516                         #clock-cells = <0>;
 517                         clock-output-names = "fsib";
 518                 };
 519                 sub_clk: sub_clk@e6150080 {
 520                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 521                         reg = <0xe6150080 4>;
 522                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 523                                  <&extal2_clk>, <&extal2_clk>;
 524                         #clock-cells = <0>;
 525                         clock-output-names = "sub";
 526                 };
 527                 spua_clk: spua_clk@e6150084 {
 528                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 529                         reg = <0xe6150084 4>;
 530                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 531                                  <&extal2_clk>, <&extal2_clk>;
 532                         #clock-cells = <0>;
 533                         clock-output-names = "spua";
 534                 };
 535                 spuv_clk: spuv_clk@e6150094 {
 536                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 537                         reg = <0xe6150094 4>;
 538                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 539                                  <&extal2_clk>, <&extal2_clk>;
 540                         #clock-cells = <0>;
 541                         clock-output-names = "spuv";
 542                 };
 543                 msu_clk: msu_clk@e6150088 {
 544                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 545                         reg = <0xe6150088 4>;
 546                         clocks = <&pll1_div2_clk>, <0>,
 547                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 548                         #clock-cells = <0>;
 549                         clock-output-names = "msu";
 550                 };
 551                 hsi_clk: hsi_clk@e615008c {
 552                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 553                         reg = <0xe615008c 4>;
 554                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 555                                  <&pll1_div7_clk>, <0>;
 556                         #clock-cells = <0>;
 557                         clock-output-names = "hsi";
 558                 };
 559                 mfg1_clk: mfg1_clk@e6150098 {
 560                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 561                         reg = <0xe6150098 4>;
 562                         clocks = <&pll1_div2_clk>, <0>,
 563                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 564                         #clock-cells = <0>;
 565                         clock-output-names = "mfg1";
 566                 };
 567                 mfg2_clk: mfg2_clk@e615009c {
 568                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 569                         reg = <0xe615009c 4>;
 570                         clocks = <&pll1_div2_clk>, <0>,
 571                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 572                         #clock-cells = <0>;
 573                         clock-output-names = "mfg2";
 574                 };
 575                 dsit_clk: dsit_clk@e6150060 {
 576                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 577                         reg = <0xe6150060 4>;
 578                         clocks = <&pll1_div2_clk>, <0>,
 579                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 580                         #clock-cells = <0>;
 581                         clock-output-names = "dsit";
 582                 };
 583                 dsi0p_clk: dsi0p_clk@e6150064 {
 584                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 585                         reg = <0xe6150064 4>;
 586                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 587                                  <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
 588                                  <&extcki_clk>, <0>, <0>, <0>;
 589                         #clock-cells = <0>;
 590                         clock-output-names = "dsi0pck";
 591                 };
 592
 593                 /* Fixed factor clocks */
 594                 main_div2_clk: main_div2_clk {
 595                         compatible = "fixed-factor-clock";
 596                         clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 597                         #clock-cells = <0>;
 598                         clock-div = <2>;
 599                         clock-mult = <1>;
 600                         clock-output-names = "main_div2";
 601                 };
 602                 pll1_div2_clk: pll1_div2_clk {
 603                         compatible = "fixed-factor-clock";
 604                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 605                         #clock-cells = <0>;
 606                         clock-div = <2>;
 607                         clock-mult = <1>;
 608                         clock-output-names = "pll1_div2";
 609                 };
 610                 pll1_div7_clk: pll1_div7_clk {
 611                         compatible = "fixed-factor-clock";
 612                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 613                         #clock-cells = <0>;
 614                         clock-div = <7>;
 615                         clock-mult = <1>;
 616                         clock-output-names = "pll1_div7";
 617                 };
 618                 pll1_div13_clk: pll1_div13_clk {
 619                         compatible = "fixed-factor-clock";
 620                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 621                         #clock-cells = <0>;
 622                         clock-div = <13>;
 623                         clock-mult = <1>;
 624                         clock-output-names = "pll1_div13";
 625                 };
 626                 twd_clk: twd_clk {
 627                         compatible = "fixed-factor-clock";
 628                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
 629                         #clock-cells = <0>;
 630                         clock-div = <4>;
 631                         clock-mult = <1>;
 632                         clock-output-names = "twd";
 633                 };
 634
 635                 /* Gate clocks */
 636                 mstp0_clks: mstp0_clks@e6150130 {
 637                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 638                         reg = <0xe6150130 4>, <0xe6150030 4>;
 639                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 640                         #clock-cells = <1>;
 641                         clock-indices = <
 642                                 SH73A0_CLK_IIC2
 643                         >;
 644                         clock-output-names =
 645                                 "iic2";
 646                 };
 647                 mstp1_clks: mstp1_clks@e6150134 {
 648                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 649                         reg = <0xe6150134 4>, <0xe6150038 4>;
 650                         clocks = <&cpg_clocks SH73A0_CLK_B>,
 651                                  <&cpg_clocks SH73A0_CLK_B>,
 652                                  <&cpg_clocks SH73A0_CLK_B>,
 653                                  <&cpg_clocks SH73A0_CLK_B>,
 654                                  <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
 655                                  <&cpg_clocks SH73A0_CLK_HP>,
 656                                  <&cpg_clocks SH73A0_CLK_ZG>,
 657                                  <&cpg_clocks SH73A0_CLK_B>;
 658                         #clock-cells = <1>;
 659                         clock-indices = <
 660                                 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
 661                                 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
 662                                 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
 663                                 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
 664                                 SH73A0_CLK_LCDC0
 665                         >;
 666                         clock-output-names =
 667                                 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
 668                                 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
 669                 };
 670                 mstp2_clks: mstp2_clks@e6150138 {
 671                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 672                         reg = <0xe6150138 4>, <0xe6150040 4>;
 673                         clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
 674                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 675                                  <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
 676                                  <&sub_clk>, <&sub_clk>;
 677                         #clock-cells = <1>;
 678                         clock-indices = <
 679                                 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
 680                                 SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
 681                                 SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
 682                                 SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
 683                                 SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
 684                         >;
 685                         clock-output-names =
 686                                 "scifa7", "sy_dmac", "mp_dmac", "scifa5",
 687                                 "scifb", "scifa0", "scifa1", "scifa2",
 688                                 "scifa3", "scifa4";
 689                 };
 690                 mstp3_clks: mstp3_clks@e615013c {
 691                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 692                         reg = <0xe615013c 4>, <0xe6150048 4>;
 693                         clocks = <&sub_clk>, <&extalr_clk>,
 694                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 695                                  <&cpg_clocks SH73A0_CLK_HP>,
 696                                  <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
 697                                  <&sdhi0_clk>, <&sdhi1_clk>,
 698                                  <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
 699                                  <&main_div2_clk>, <&main_div2_clk>,
 700                                  <&main_div2_clk>, <&main_div2_clk>,
 701                                  <&main_div2_clk>;
 702                         #clock-cells = <1>;
 703                         clock-indices = <
 704                                 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
 705                                 SH73A0_CLK_FSI SH73A0_CLK_IRDA
 706                                 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
 707                                 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
 708                                 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
 709                                 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
 710                                 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
 711                                 SH73A0_CLK_TPU4
 712                         >;
 713                         clock-output-names =
 714                                 "scifa6", "cmt1", "fsi", "irda", "iic1",
 715                                 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
 716                                 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
 717                 };
 718                 mstp4_clks: mstp4_clks@e6150140 {
 719                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 720                         reg = <0xe6150140 4>, <0xe615004c 4>;
 721                         clocks = <&cpg_clocks SH73A0_CLK_HP>,
 722                                  <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
 723                         #clock-cells = <1>;
 724                         clock-indices = <
 725                                 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
 726                                 SH73A0_CLK_KEYSC
 727                         >;
 728                         clock-output-names =
 729                                 "iic3", "iic4", "keysc";
 730                 };
 731                 mstp5_clks: mstp5_clks@e6150144 {
 732                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 733                         reg = <0xe6150144 4>, <0xe615003c 4>;
 734                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 735                         #clock-cells = <1>;
 736                         clock-indices = <
 737                                 SH73A0_CLK_INTCA0
 738                         >;
 739                         clock-output-names =
 740                                 "intca0";
 741                 };
 742         };
 743 };