2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/clock/at91.h>
48 #include <dt-bindings/dma/at91.h>
49 #include <dt-bindings/pinctrl/at91.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/gpio/gpio.h>
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
78 compatible = "arm,cortex-a5";
80 next-level-cache = <&L2>;
85 reg = <0x20000000 0x20000000>;
89 slow_xtal: slow_xtal {
90 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 main_xtal: main_xtal {
96 compatible = "fixed-clock";
98 clock-frequency = <0>;
101 adc_op_clk: adc_op_clk{
102 compatible = "fixed-clock";
104 clock-frequency = <1000000>;
108 ns_sram: sram@00210000 {
109 compatible = "mmio-sram";
110 reg = <0x00210000 0x10000>;
114 compatible = "simple-bus";
115 #address-cells = <1>;
119 usb0: gadget@00400000 {
120 #address-cells = <1>;
122 compatible = "atmel,at91sam9rl-udc";
123 reg = <0x00400000 0x100000
125 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
126 clocks = <&udphs_clk>, <&utmi>;
127 clock-names = "pclk", "hclk";
132 atmel,fifo-size = <64>;
133 atmel,nb-banks = <1>;
138 atmel,fifo-size = <1024>;
139 atmel,nb-banks = <3>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <3>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <2>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
194 atmel,fifo-size = <1024>;
195 atmel,nb-banks = <2>;
201 atmel,fifo-size = <1024>;
202 atmel,nb-banks = <2>;
208 atmel,fifo-size = <1024>;
209 atmel,nb-banks = <2>;
215 atmel,fifo-size = <1024>;
216 atmel,nb-banks = <2>;
222 atmel,fifo-size = <1024>;
223 atmel,nb-banks = <2>;
229 atmel,fifo-size = <1024>;
230 atmel,nb-banks = <2>;
236 atmel,fifo-size = <1024>;
237 atmel,nb-banks = <2>;
243 atmel,fifo-size = <1024>;
244 atmel,nb-banks = <2>;
249 usb1: ohci@00500000 {
250 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
251 reg = <0x00500000 0x100000>;
252 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
253 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
255 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
259 usb2: ehci@00600000 {
260 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
261 reg = <0x00600000 0x100000>;
262 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
263 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
264 clock-names = "usb_clk", "ehci_clk", "uhpck";
268 L2: cache-controller@00a00000 {
269 compatible = "arm,pl310-cache";
270 reg = <0x00a00000 0x1000>;
271 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
276 nand0: nand@80000000 {
277 compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
278 #address-cells = <1>;
281 reg = < 0x80000000 0x08000000 /* EBI CS3 */
282 0xfc05c070 0x00000490 /* SMC PMECC regs */
283 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
285 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
286 atmel,nand-addr-offset = <21>;
287 atmel,nand-cmd-offset = <22>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_nand>;
294 compatible = "atmel,sama5d3-nfc";
295 #address-cells = <1>;
298 0x90000000 0x10000000 /* NFC Command Registers */
299 0xfc05c000 0x00000070 /* NFC HSMC regs */
300 0x00100000 0x00100000 /* NFC SRAM banks */
302 clocks = <&hsmc_clk>;
308 compatible = "simple-bus";
309 #address-cells = <1>;
313 dma1: dma-controller@f0004000 {
314 compatible = "atmel,sama5d4-dma";
315 reg = <0xf0004000 0x200>;
316 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
318 clocks = <&dma1_clk>;
319 clock-names = "dma_clk";
322 ramc0: ramc@f0010000 {
323 compatible = "atmel,sama5d3-ddramc";
324 reg = <0xf0010000 0x200>;
325 clocks = <&ddrck>, <&mpddr_clk>;
326 clock-names = "ddrck", "mpddr";
329 dma0: dma-controller@f0014000 {
330 compatible = "atmel,sama5d4-dma";
331 reg = <0xf0014000 0x200>;
332 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
334 clocks = <&dma0_clk>;
335 clock-names = "dma_clk";
339 compatible = "atmel,sama5d3-pmc";
340 reg = <0xf0018000 0x120>;
341 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
342 interrupt-controller;
343 #address-cells = <1>;
345 #interrupt-cells = <1>;
347 main_rc_osc: main_rc_osc {
348 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
350 interrupt-parent = <&pmc>;
351 interrupts = <AT91_PMC_MOSCRCS>;
352 clock-frequency = <12000000>;
353 clock-accuracy = <100000000>;
357 compatible = "atmel,at91rm9200-clk-main-osc";
359 interrupt-parent = <&pmc>;
360 interrupts = <AT91_PMC_MOSCS>;
361 clocks = <&main_xtal>;
365 compatible = "atmel,at91sam9x5-clk-main";
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_MOSCSELS>;
369 clocks = <&main_rc_osc &main_osc>;
373 compatible = "atmel,sama5d3-clk-pll";
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_LOCKA>;
379 atmel,clk-input-range = <12000000 12000000>;
380 #atmel,pll-clk-output-range-cells = <4>;
381 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
385 compatible = "atmel,at91sam9x5-clk-plldiv";
391 compatible = "atmel,at91sam9x5-clk-utmi";
393 interrupt-parent = <&pmc>;
394 interrupts = <AT91_PMC_LOCKU>;
399 compatible = "atmel,at91sam9x5-clk-master";
401 interrupt-parent = <&pmc>;
402 interrupts = <AT91_PMC_MCKRDY>;
403 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
404 atmel,clk-output-range = <125000000 177000000>;
405 atmel,clk-divisors = <1 2 4 3>;
410 compatible = "atmel,sama5d4-clk-h32mx";
415 compatible = "atmel,at91sam9x5-clk-usb";
417 clocks = <&plladiv>, <&utmi>;
421 compatible = "atmel,at91sam9x5-clk-programmable";
422 #address-cells = <1>;
424 interrupt-parent = <&pmc>;
425 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
430 interrupts = <AT91_PMC_PCKRDY(0)>;
436 interrupts = <AT91_PMC_PCKRDY(1)>;
442 interrupts = <AT91_PMC_PCKRDY(2)>;
447 compatible = "atmel,at91sam9x5-clk-smd";
449 clocks = <&plladiv>, <&utmi>;
453 compatible = "atmel,at91rm9200-clk-system";
454 #address-cells = <1>;
507 compatible = "atmel,at91sam9x5-clk-peripheral";
508 #address-cells = <1>;
517 usart0_clk: usart0_clk {
522 usart1_clk: usart1_clk {
547 matrix1_clk: matrix1_clk {
577 uart0_clk: uart0_clk {
582 uart1_clk: uart1_clk {
587 usart2_clk: usart2_clk {
592 usart3_clk: usart3_clk {
597 usart4_clk: usart4_clk {
672 uhphs_clk: uhphs_clk {
677 udphs_clk: udphs_clk {
697 macb0_clk: macb0_clk {
702 macb1_clk: macb1_clk {
712 securam_clk: securam_clk {
734 compatible = "atmel,at91sam9x5-clk-peripheral";
735 #address-cells = <1>;
744 cpkcc_clk: cpkcc_clk {
754 mpddr_clk: mpddr_clk {
759 matrix0_clk: matrix0_clk {
787 compatible = "atmel,hsmci";
788 reg = <0xf8000000 0x600>;
789 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
791 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
792 | AT91_XDMAC_DT_PERID(0))>;
794 pinctrl-names = "default";
795 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
797 #address-cells = <1>;
799 clocks = <&mci0_clk>;
800 clock-names = "mci_clk";
804 #address-cells = <1>;
806 compatible = "atmel,at91rm9200-spi";
807 reg = <0xf8010000 0x100>;
808 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
810 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
811 | AT91_XDMAC_DT_PERID(10))>,
813 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
814 | AT91_XDMAC_DT_PERID(11))>;
815 dma-names = "tx", "rx";
816 pinctrl-names = "default";
817 pinctrl-0 = <&pinctrl_spi0>;
818 clocks = <&spi0_clk>;
819 clock-names = "spi_clk";
824 compatible = "atmel,at91sam9x5-i2c";
825 reg = <0xf8014000 0x4000>;
826 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
828 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
829 | AT91_XDMAC_DT_PERID(2))>,
831 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
832 | AT91_XDMAC_DT_PERID(3))>;
833 dma-names = "tx", "rx";
834 pinctrl-names = "default";
835 pinctrl-0 = <&pinctrl_i2c0>;
836 #address-cells = <1>;
838 clocks = <&twi0_clk>;
842 tcb0: timer@f801c000 {
843 compatible = "atmel,at91sam9x5-tcb";
844 reg = <0xf801c000 0x100>;
845 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
846 clocks = <&tcb0_clk>;
847 clock-names = "t0_clk";
850 macb0: ethernet@f8020000 {
851 compatible = "atmel,sama5d4-gem";
852 reg = <0xf8020000 0x100>;
853 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
854 pinctrl-names = "default";
855 pinctrl-0 = <&pinctrl_macb0_rmii>;
856 clocks = <&macb0_clk>, <&macb0_clk>;
857 clock-names = "hclk", "pclk";
862 compatible = "atmel,at91sam9x5-i2c";
863 reg = <0xf8024000 0x4000>;
864 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
866 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
867 | AT91_XDMAC_DT_PERID(6))>,
869 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
870 | AT91_XDMAC_DT_PERID(7))>;
871 dma-names = "tx", "rx";
872 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_i2c2>;
874 #address-cells = <1>;
876 clocks = <&twi2_clk>;
881 compatible = "atmel,sama5d4-sfr", "syscon";
882 reg = <0xf8028000 0x60>;
886 compatible = "atmel,hsmci";
887 reg = <0xfc000000 0x600>;
888 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
890 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
891 | AT91_XDMAC_DT_PERID(1))>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
896 #address-cells = <1>;
898 clocks = <&mci1_clk>;
899 clock-names = "mci_clk";
902 usart2: serial@fc008000 {
903 compatible = "atmel,at91sam9260-usart";
904 reg = <0xfc008000 0x100>;
905 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
907 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
908 | AT91_XDMAC_DT_PERID(16))>,
910 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
911 | AT91_XDMAC_DT_PERID(17))>;
912 dma-names = "tx", "rx";
913 pinctrl-names = "default";
914 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
915 clocks = <&usart2_clk>;
916 clock-names = "usart";
920 usart3: serial@fc00c000 {
921 compatible = "atmel,at91sam9260-usart";
922 reg = <0xfc00c000 0x100>;
923 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
925 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
926 | AT91_XDMAC_DT_PERID(18))>,
928 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
929 | AT91_XDMAC_DT_PERID(19))>;
930 dma-names = "tx", "rx";
931 pinctrl-names = "default";
932 pinctrl-0 = <&pinctrl_usart3>;
933 clocks = <&usart3_clk>;
934 clock-names = "usart";
938 usart4: serial@fc010000 {
939 compatible = "atmel,at91sam9260-usart";
940 reg = <0xfc010000 0x100>;
941 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
943 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
944 | AT91_XDMAC_DT_PERID(20))>,
946 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
947 | AT91_XDMAC_DT_PERID(21))>;
948 dma-names = "tx", "rx";
949 pinctrl-names = "default";
950 pinctrl-0 = <&pinctrl_usart4>;
951 clocks = <&usart4_clk>;
952 clock-names = "usart";
956 tcb1: timer@fc020000 {
957 compatible = "atmel,at91sam9x5-tcb";
958 reg = <0xfc020000 0x100>;
959 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
960 clocks = <&tcb1_clk>;
961 clock-names = "t0_clk";
965 compatible = "atmel,at91sam9x5-adc";
966 reg = <0xfc034000 0x100>;
967 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
968 pinctrl-names = "default";
970 /* external trigger is conflict with USBA_VBUS */
979 clock-names = "adc_clk", "adc_op_clk";
980 atmel,adc-channels-used = <0x01f>;
981 atmel,adc-startup-time = <40>;
982 atmel,adc-use-external;
983 atmel,adc-vref = <3000>;
984 atmel,adc-res = <8 10>;
985 atmel,adc-sample-hold-time = <11>;
986 atmel,adc-res-names = "lowres", "highres";
987 atmel,adc-ts-pressure-threshold = <10000>;
991 trigger-name = "external-rising";
992 trigger-value = <0x1>;
996 trigger-name = "external-falling";
997 trigger-value = <0x2>;
1001 trigger-name = "external-any";
1002 trigger-value = <0x3>;
1006 trigger-name = "continuous";
1007 trigger-value = <0x6>;
1012 compatible = "atmel,at91sam9g45-rstc";
1013 reg = <0xfc068600 0x10>;
1017 compatible = "atmel,at91sam9x5-shdwc";
1018 reg = <0xfc068610 0x10>;
1021 pit: timer@fc068630 {
1022 compatible = "atmel,at91sam9260-pit";
1023 reg = <0xfc068630 0x10>;
1024 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1029 compatible = "atmel,at91sam9260-wdt";
1030 reg = <0xfc068640 0x10>;
1031 status = "disabled";
1035 compatible = "atmel,at91sam9x5-sckc";
1036 reg = <0xfc068650 0x4>;
1038 slow_rc_osc: slow_rc_osc {
1039 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1041 clock-frequency = <32768>;
1042 clock-accuracy = <250000000>;
1043 atmel,startup-time-usec = <75>;
1046 slow_osc: slow_osc {
1047 compatible = "atmel,at91sam9x5-clk-slow-osc";
1049 clocks = <&slow_xtal>;
1050 atmel,startup-time-usec = <1200000>;
1054 compatible = "atmel,at91sam9x5-clk-slow";
1056 clocks = <&slow_rc_osc &slow_osc>;
1061 compatible = "atmel,at91rm9200-rtc";
1062 reg = <0xfc0686b0 0x30>;
1063 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1066 dbgu: serial@fc069000 {
1067 compatible = "atmel,at91sam9260-usart";
1068 reg = <0xfc069000 0x200>;
1069 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1070 pinctrl-names = "default";
1071 pinctrl-0 = <&pinctrl_dbgu>;
1072 clocks = <&dbgu_clk>;
1073 clock-names = "usart";
1074 status = "disabled";
1079 #address-cells = <1>;
1081 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1082 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1083 /* WARNING: revisit as pin spec has changed */
1086 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1087 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1088 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1089 0x00000000 0x00000000 0x00000000 /* pioD */
1090 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1093 pioA: gpio@fc06a000 {
1094 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1095 reg = <0xfc06a000 0x100>;
1096 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1099 interrupt-controller;
1100 #interrupt-cells = <2>;
1101 clocks = <&pioA_clk>;
1104 pioB: gpio@fc06b000 {
1105 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1106 reg = <0xfc06b000 0x100>;
1107 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1110 interrupt-controller;
1111 #interrupt-cells = <2>;
1112 clocks = <&pioB_clk>;
1115 pioC: gpio@fc06c000 {
1116 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1117 reg = <0xfc06c000 0x100>;
1118 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1121 interrupt-controller;
1122 #interrupt-cells = <2>;
1123 clocks = <&pioC_clk>;
1126 pioD: gpio@fc068000 {
1127 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1128 reg = <0xfc068000 0x100>;
1129 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1134 clocks = <&pioD_clk>;
1135 status = "disabled";
1138 pioE: gpio@fc06d000 {
1139 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1140 reg = <0xfc06d000 0x100>;
1141 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1144 interrupt-controller;
1145 #interrupt-cells = <2>;
1146 clocks = <&pioE_clk>;
1149 /* pinctrl pin settings */
1151 pinctrl_adc0_adtrg: adc0_adtrg {
1153 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1155 pinctrl_adc0_ad0: adc0_ad0 {
1157 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1159 pinctrl_adc0_ad1: adc0_ad1 {
1161 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1163 pinctrl_adc0_ad2: adc0_ad2 {
1165 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1167 pinctrl_adc0_ad3: adc0_ad3 {
1169 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1171 pinctrl_adc0_ad4: adc0_ad4 {
1173 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1178 pinctrl_dbgu: dbgu-0 {
1180 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1181 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1186 pinctrl_i2c0: i2c0-0 {
1188 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1189 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1194 pinctrl_i2c2: i2c2-0 {
1196 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1197 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1202 pinctrl_macb0_rmii: macb0_rmii-0 {
1204 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1205 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1206 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1207 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1208 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1209 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1210 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1211 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1212 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1213 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1219 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1221 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1222 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1223 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1226 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1228 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1229 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1230 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1236 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1238 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1239 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1240 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1243 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1245 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1246 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1247 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1253 pinctrl_nand: nand-0 {
1255 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1256 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1258 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1259 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1261 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1262 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1263 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1264 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1265 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1266 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1267 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1268 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1269 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1270 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1275 pinctrl_spi0: spi0-0 {
1277 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1278 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1279 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1285 pinctrl_usart2: usart2-0 {
1287 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1288 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1291 pinctrl_usart2_rts: usart2_rts-0 {
1292 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1294 pinctrl_usart2_cts: usart2_cts-0 {
1295 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1300 pinctrl_usart3: usart3-0 {
1302 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1303 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1309 pinctrl_usart4: usart4-0 {
1311 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1312 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1315 pinctrl_usart4_rts: usart4_rts-0 {
1316 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1318 pinctrl_usart4_cts: usart4_cts-0 {
1319 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1324 aic: interrupt-controller@fc06e000 {
1325 #interrupt-cells = <3>;
1326 compatible = "atmel,sama5d4-aic";
1327 interrupt-controller;
1328 reg = <0xfc06e000 0x200>;
1329 atmel,external-irqs = <56>;