2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
8 * Licensed under GPLv2 or later.
11 #include "skeleton.dtsi"
12 #include <dt-bindings/dma/at91.h>
13 #include <dt-bindings/pinctrl/at91.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/at91.h>
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
47 compatible = "arm,cortex-a5";
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
58 reg = <0x20000000 0x8000000>;
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
65 clock-frequency = <0>;
68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
71 clock-frequency = <0>;
74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
77 clock-frequency = <20000000>;
82 compatible = "simple-bus";
88 compatible = "simple-bus";
94 compatible = "atmel,hsmci";
95 reg = <0xf0000000 0x600>;
96 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
97 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
102 #address-cells = <1>;
104 clocks = <&mci0_clk>;
105 clock-names = "mci_clk";
109 #address-cells = <1>;
111 compatible = "atmel,at91rm9200-spi";
112 reg = <0xf0004000 0x100>;
113 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
114 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
115 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
116 dma-names = "tx", "rx";
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_spi0>;
119 clocks = <&spi0_clk>;
120 clock-names = "spi_clk";
125 compatible = "atmel,at91sam9g45-ssc";
126 reg = <0xf0008000 0x4000>;
127 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
128 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
129 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
130 dma-names = "tx", "rx";
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
133 clocks = <&ssc0_clk>;
134 clock-names = "pclk";
138 tcb0: timer@f0010000 {
139 compatible = "atmel,at91sam9x5-tcb";
140 reg = <0xf0010000 0x100>;
141 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
142 clocks = <&tcb0_clk>;
143 clock-names = "t0_clk";
147 compatible = "atmel,at91sam9x5-i2c";
148 reg = <0xf0014000 0x4000>;
149 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
150 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
151 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
152 dma-names = "tx", "rx";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c0>;
155 #address-cells = <1>;
157 clocks = <&twi0_clk>;
162 compatible = "atmel,at91sam9x5-i2c";
163 reg = <0xf0018000 0x4000>;
164 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
165 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
166 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
167 dma-names = "tx", "rx";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 #address-cells = <1>;
172 clocks = <&twi1_clk>;
176 usart0: serial@f001c000 {
177 compatible = "atmel,at91sam9260-usart";
178 reg = <0xf001c000 0x100>;
179 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
180 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
181 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
182 dma-names = "tx", "rx";
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_usart0>;
185 clocks = <&usart0_clk>;
186 clock-names = "usart";
190 usart1: serial@f0020000 {
191 compatible = "atmel,at91sam9260-usart";
192 reg = <0xf0020000 0x100>;
193 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
194 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
195 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
196 dma-names = "tx", "rx";
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_usart1>;
199 clocks = <&usart1_clk>;
200 clock-names = "usart";
205 compatible = "atmel,sama5d3-pwm";
206 reg = <0xf002c000 0x300>;
207 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
214 compatible = "atmel,at91sam9g45-isi";
215 reg = <0xf0034000 0x4000>;
216 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
221 compatible = "atmel,hsmci";
222 reg = <0xf8000000 0x600>;
223 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
224 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
229 #address-cells = <1>;
231 clocks = <&mci1_clk>;
232 clock-names = "mci_clk";
236 #address-cells = <1>;
238 compatible = "atmel,at91rm9200-spi";
239 reg = <0xf8008000 0x100>;
240 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
241 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
242 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
243 dma-names = "tx", "rx";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_spi1>;
246 clocks = <&spi1_clk>;
247 clock-names = "spi_clk";
252 compatible = "atmel,at91sam9g45-ssc";
253 reg = <0xf800c000 0x4000>;
254 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
255 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
256 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
257 dma-names = "tx", "rx";
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
260 clocks = <&ssc1_clk>;
261 clock-names = "pclk";
266 #address-cells = <1>;
268 compatible = "atmel,at91sam9x5-adc";
269 reg = <0xf8018000 0x100>;
270 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
271 pinctrl-names = "default";
289 clock-names = "adc_clk", "adc_op_clk";
290 atmel,adc-channels-used = <0xfff>;
291 atmel,adc-startup-time = <40>;
292 atmel,adc-use-external-triggers;
293 atmel,adc-vref = <3000>;
294 atmel,adc-res = <10 12>;
295 atmel,adc-res-names = "lowres", "highres";
300 trigger-name = "external-rising";
301 trigger-value = <0x1>;
306 trigger-name = "external-falling";
307 trigger-value = <0x2>;
312 trigger-name = "external-any";
313 trigger-value = <0x3>;
318 trigger-name = "continuous";
319 trigger-value = <0x6>;
324 compatible = "atmel,at91sam9x5-i2c";
325 reg = <0xf801c000 0x4000>;
326 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
327 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
328 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
329 dma-names = "tx", "rx";
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c2>;
332 #address-cells = <1>;
334 clocks = <&twi2_clk>;
338 usart2: serial@f8020000 {
339 compatible = "atmel,at91sam9260-usart";
340 reg = <0xf8020000 0x100>;
341 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
342 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
343 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
344 dma-names = "tx", "rx";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_usart2>;
347 clocks = <&usart2_clk>;
348 clock-names = "usart";
352 usart3: serial@f8024000 {
353 compatible = "atmel,at91sam9260-usart";
354 reg = <0xf8024000 0x100>;
355 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
356 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
357 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_usart3>;
361 clocks = <&usart3_clk>;
362 clock-names = "usart";
367 compatible = "atmel,at91sam9g46-sha";
368 reg = <0xf8034000 0x100>;
369 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
370 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
373 clock-names = "sha_clk";
377 compatible = "atmel,at91sam9g46-aes";
378 reg = <0xf8038000 0x100>;
379 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
380 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
381 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
382 dma-names = "tx", "rx";
384 clock-names = "aes_clk";
388 compatible = "atmel,at91sam9g46-tdes";
389 reg = <0xf803c000 0x100>;
390 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
391 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
392 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
393 dma-names = "tx", "rx";
394 clocks = <&tdes_clk>;
395 clock-names = "tdes_clk";
398 dma0: dma-controller@ffffe600 {
399 compatible = "atmel,at91sam9g45-dma";
400 reg = <0xffffe600 0x200>;
401 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
403 clocks = <&dma0_clk>;
404 clock-names = "dma_clk";
407 dma1: dma-controller@ffffe800 {
408 compatible = "atmel,at91sam9g45-dma";
409 reg = <0xffffe800 0x200>;
410 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
412 clocks = <&dma1_clk>;
413 clock-names = "dma_clk";
416 ramc0: ramc@ffffea00 {
417 compatible = "atmel,sama5d3-ddramc";
418 reg = <0xffffea00 0x200>;
419 clocks = <&ddrck>, <&mpddr_clk>;
420 clock-names = "ddrck", "mpddr";
423 dbgu: serial@ffffee00 {
424 compatible = "atmel,at91sam9260-usart";
425 reg = <0xffffee00 0x200>;
426 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
427 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
428 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
429 dma-names = "tx", "rx";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_dbgu>;
432 clocks = <&dbgu_clk>;
433 clock-names = "usart";
437 aic: interrupt-controller@fffff000 {
438 #interrupt-cells = <3>;
439 compatible = "atmel,sama5d3-aic";
440 interrupt-controller;
441 reg = <0xfffff000 0x200>;
442 atmel,external-irqs = <47>;
446 #address-cells = <1>;
448 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
449 ranges = <0xfffff200 0xfffff200 0xa00>;
452 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
453 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
454 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
455 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
456 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
459 /* shared pinctrl settings */
461 pinctrl_adc0_adtrg: adc0_adtrg {
463 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
465 pinctrl_adc0_ad0: adc0_ad0 {
467 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
469 pinctrl_adc0_ad1: adc0_ad1 {
471 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
473 pinctrl_adc0_ad2: adc0_ad2 {
475 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
477 pinctrl_adc0_ad3: adc0_ad3 {
479 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
481 pinctrl_adc0_ad4: adc0_ad4 {
483 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
485 pinctrl_adc0_ad5: adc0_ad5 {
487 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
489 pinctrl_adc0_ad6: adc0_ad6 {
491 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
493 pinctrl_adc0_ad7: adc0_ad7 {
495 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
497 pinctrl_adc0_ad8: adc0_ad8 {
499 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
501 pinctrl_adc0_ad9: adc0_ad9 {
503 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
505 pinctrl_adc0_ad10: adc0_ad10 {
507 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
509 pinctrl_adc0_ad11: adc0_ad11 {
511 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
516 pinctrl_dbgu: dbgu-0 {
518 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
519 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
524 pinctrl_i2c0: i2c0-0 {
526 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
527 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
532 pinctrl_i2c1: i2c1-0 {
534 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
535 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
540 pinctrl_i2c2: i2c2-0 {
542 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
543 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
550 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
551 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
552 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
553 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
554 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
555 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
556 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
557 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
558 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
559 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
560 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
561 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
562 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
564 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
566 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
571 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
573 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
574 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
575 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
577 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
579 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
580 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
581 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
583 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
585 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
586 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
587 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
588 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
593 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
595 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
596 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
597 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
599 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
601 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
602 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
603 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
608 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
610 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
611 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
616 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
618 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
620 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
622 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
624 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
626 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
628 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
630 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
633 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
635 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
637 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
639 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
641 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
643 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
645 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
647 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
649 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
651 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
653 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
655 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
658 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
660 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
662 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
664 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
666 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
668 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
670 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
672 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
675 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
677 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
679 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
681 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
683 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
685 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
687 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
689 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
694 pinctrl_spi0: spi0-0 {
696 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
697 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
698 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
703 pinctrl_spi1: spi1-0 {
705 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
706 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
707 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
712 pinctrl_ssc0_tx: ssc0_tx {
714 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
715 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
716 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
719 pinctrl_ssc0_rx: ssc0_rx {
721 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
722 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
723 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
728 pinctrl_ssc1_tx: ssc1_tx {
730 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
731 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
732 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
735 pinctrl_ssc1_rx: ssc1_rx {
737 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
738 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
739 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
744 pinctrl_usart0: usart0-0 {
746 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
747 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
750 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
752 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
753 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
758 pinctrl_usart1: usart1-0 {
760 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
761 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
764 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
766 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
767 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
772 pinctrl_usart2: usart2-0 {
774 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
775 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
778 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
780 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
781 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
786 pinctrl_usart3: usart3-0 {
788 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
789 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
792 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
794 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
795 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
800 pioA: gpio@fffff200 {
801 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
802 reg = <0xfffff200 0x100>;
803 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
806 interrupt-controller;
807 #interrupt-cells = <2>;
808 clocks = <&pioA_clk>;
811 pioB: gpio@fffff400 {
812 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
813 reg = <0xfffff400 0x100>;
814 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
817 interrupt-controller;
818 #interrupt-cells = <2>;
819 clocks = <&pioB_clk>;
822 pioC: gpio@fffff600 {
823 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
824 reg = <0xfffff600 0x100>;
825 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
828 interrupt-controller;
829 #interrupt-cells = <2>;
830 clocks = <&pioC_clk>;
833 pioD: gpio@fffff800 {
834 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
835 reg = <0xfffff800 0x100>;
836 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
839 interrupt-controller;
840 #interrupt-cells = <2>;
841 clocks = <&pioD_clk>;
844 pioE: gpio@fffffa00 {
845 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
846 reg = <0xfffffa00 0x100>;
847 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
850 interrupt-controller;
851 #interrupt-cells = <2>;
852 clocks = <&pioE_clk>;
857 compatible = "atmel,sama5d3-pmc";
858 reg = <0xfffffc00 0x120>;
859 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
860 interrupt-controller;
861 #address-cells = <1>;
863 #interrupt-cells = <1>;
865 main_rc_osc: main_rc_osc {
866 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
868 interrupt-parent = <&pmc>;
869 interrupts = <AT91_PMC_MOSCRCS>;
870 clock-frequency = <12000000>;
871 clock-accuracy = <50000000>;
875 compatible = "atmel,at91rm9200-clk-main-osc";
877 interrupt-parent = <&pmc>;
878 interrupts = <AT91_PMC_MOSCS>;
879 clocks = <&main_xtal>;
883 compatible = "atmel,at91sam9x5-clk-main";
885 interrupt-parent = <&pmc>;
886 interrupts = <AT91_PMC_MOSCSELS>;
887 clocks = <&main_rc_osc &main_osc>;
891 compatible = "atmel,sama5d3-clk-pll";
893 interrupt-parent = <&pmc>;
894 interrupts = <AT91_PMC_LOCKA>;
897 atmel,clk-input-range = <8000000 50000000>;
898 #atmel,pll-clk-output-range-cells = <4>;
899 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
903 compatible = "atmel,at91sam9x5-clk-plldiv";
909 compatible = "atmel,at91sam9x5-clk-utmi";
911 interrupt-parent = <&pmc>;
912 interrupts = <AT91_PMC_LOCKU>;
917 compatible = "atmel,at91sam9x5-clk-master";
919 interrupt-parent = <&pmc>;
920 interrupts = <AT91_PMC_MCKRDY>;
921 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
922 atmel,clk-output-range = <0 166000000>;
923 atmel,clk-divisors = <1 2 4 3>;
927 compatible = "atmel,at91sam9x5-clk-usb";
929 clocks = <&plladiv>, <&utmi>;
933 compatible = "atmel,at91sam9x5-clk-programmable";
934 #address-cells = <1>;
936 interrupt-parent = <&pmc>;
937 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
942 interrupts = <AT91_PMC_PCKRDY(0)>;
948 interrupts = <AT91_PMC_PCKRDY(1)>;
954 interrupts = <AT91_PMC_PCKRDY(2)>;
959 compatible = "atmel,at91sam9x5-clk-smd";
961 clocks = <&plladiv>, <&utmi>;
965 compatible = "atmel,at91rm9200-clk-system";
966 #address-cells = <1>;
1013 compatible = "atmel,at91sam9x5-clk-peripheral";
1014 #address-cells = <1>;
1018 dbgu_clk: dbgu_clk {
1023 hsmc_clk: hsmc_clk {
1028 pioA_clk: pioA_clk {
1033 pioB_clk: pioB_clk {
1038 pioC_clk: pioC_clk {
1043 pioD_clk: pioD_clk {
1048 pioE_clk: pioE_clk {
1053 usart0_clk: usart0_clk {
1056 atmel,clk-output-range = <0 66000000>;
1059 usart1_clk: usart1_clk {
1062 atmel,clk-output-range = <0 66000000>;
1065 usart2_clk: usart2_clk {
1068 atmel,clk-output-range = <0 66000000>;
1071 usart3_clk: usart3_clk {
1074 atmel,clk-output-range = <0 66000000>;
1077 twi0_clk: twi0_clk {
1080 atmel,clk-output-range = <0 16625000>;
1083 twi1_clk: twi1_clk {
1086 atmel,clk-output-range = <0 16625000>;
1089 twi2_clk: twi2_clk {
1092 atmel,clk-output-range = <0 16625000>;
1095 mci0_clk: mci0_clk {
1100 mci1_clk: mci1_clk {
1105 spi0_clk: spi0_clk {
1108 atmel,clk-output-range = <0 133000000>;
1111 spi1_clk: spi1_clk {
1114 atmel,clk-output-range = <0 133000000>;
1117 tcb0_clk: tcb0_clk {
1120 atmel,clk-output-range = <0 133000000>;
1131 atmel,clk-output-range = <0 66000000>;
1134 dma0_clk: dma0_clk {
1139 dma1_clk: dma1_clk {
1144 uhphs_clk: uhphs_clk {
1149 udphs_clk: udphs_clk {
1159 ssc0_clk: ssc0_clk {
1162 atmel,clk-output-range = <0 66000000>;
1165 ssc1_clk: ssc1_clk {
1168 atmel,clk-output-range = <0 66000000>;
1181 tdes_clk: tdes_clk {
1186 trng_clk: trng_clk {
1191 fuse_clk: fuse_clk {
1196 mpddr_clk: mpddr_clk {
1204 compatible = "atmel,at91sam9g45-rstc";
1205 reg = <0xfffffe00 0x10>;
1208 shutdown-controller@fffffe10 {
1209 compatible = "atmel,at91sam9x5-shdwc";
1210 reg = <0xfffffe10 0x10>;
1213 pit: timer@fffffe30 {
1214 compatible = "atmel,at91sam9260-pit";
1215 reg = <0xfffffe30 0xf>;
1216 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1221 compatible = "atmel,at91sam9260-wdt";
1222 reg = <0xfffffe40 0x10>;
1223 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1224 atmel,watchdog-type = "hardware";
1225 atmel,reset-type = "all";
1228 status = "disabled";
1232 compatible = "atmel,at91sam9x5-sckc";
1233 reg = <0xfffffe50 0x4>;
1235 slow_rc_osc: slow_rc_osc {
1236 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1238 clock-frequency = <32768>;
1239 clock-accuracy = <50000000>;
1240 atmel,startup-time-usec = <75>;
1243 slow_osc: slow_osc {
1244 compatible = "atmel,at91sam9x5-clk-slow-osc";
1246 clocks = <&slow_xtal>;
1247 atmel,startup-time-usec = <1200000>;
1251 compatible = "atmel,at91sam9x5-clk-slow";
1253 clocks = <&slow_rc_osc &slow_osc>;
1258 compatible = "atmel,at91rm9200-rtc";
1259 reg = <0xfffffeb0 0x30>;
1260 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1264 usb0: gadget@00500000 {
1265 #address-cells = <1>;
1267 compatible = "atmel,at91sam9rl-udc";
1268 reg = <0x00500000 0x100000
1270 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1271 clocks = <&udphs_clk>, <&utmi>;
1272 clock-names = "pclk", "hclk";
1273 status = "disabled";
1277 atmel,fifo-size = <64>;
1278 atmel,nb-banks = <1>;
1283 atmel,fifo-size = <1024>;
1284 atmel,nb-banks = <3>;
1291 atmel,fifo-size = <1024>;
1292 atmel,nb-banks = <3>;
1299 atmel,fifo-size = <1024>;
1300 atmel,nb-banks = <2>;
1306 atmel,fifo-size = <1024>;
1307 atmel,nb-banks = <2>;
1313 atmel,fifo-size = <1024>;
1314 atmel,nb-banks = <2>;
1320 atmel,fifo-size = <1024>;
1321 atmel,nb-banks = <2>;
1327 atmel,fifo-size = <1024>;
1328 atmel,nb-banks = <2>;
1334 atmel,fifo-size = <1024>;
1335 atmel,nb-banks = <2>;
1340 atmel,fifo-size = <1024>;
1341 atmel,nb-banks = <2>;
1346 atmel,fifo-size = <1024>;
1347 atmel,nb-banks = <2>;
1352 atmel,fifo-size = <1024>;
1353 atmel,nb-banks = <2>;
1358 atmel,fifo-size = <1024>;
1359 atmel,nb-banks = <2>;
1364 atmel,fifo-size = <1024>;
1365 atmel,nb-banks = <2>;
1370 atmel,fifo-size = <1024>;
1371 atmel,nb-banks = <2>;
1376 atmel,fifo-size = <1024>;
1377 atmel,nb-banks = <2>;
1381 usb1: ohci@00600000 {
1382 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1383 reg = <0x00600000 0x100000>;
1384 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1385 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
1387 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
1388 status = "disabled";
1391 usb2: ehci@00700000 {
1392 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1393 reg = <0x00700000 0x100000>;
1394 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1395 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1396 clock-names = "usb_clk", "ehci_clk", "uhpck";
1397 status = "disabled";
1400 nand0: nand@60000000 {
1401 compatible = "atmel,at91rm9200-nand";
1402 #address-cells = <1>;
1405 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1406 0xffffc070 0x00000490 /* SMC PMECC regs */
1407 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1408 0x00110000 0x00018000 /* ROM code */
1410 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1411 atmel,nand-addr-offset = <21>;
1412 atmel,nand-cmd-offset = <22>;
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1416 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1417 status = "disabled";
1420 compatible = "atmel,sama5d3-nfc";
1421 #address-cells = <1>;
1424 0x70000000 0x10000000 /* NFC Command Registers */
1425 0xffffc000 0x00000070 /* NFC HSMC regs */
1426 0x00200000 0x00100000 /* NFC SRAM banks */
1428 clocks = <&hsmc_clk>;