arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts

   1 /*
   2  * ARM Ltd. Fast Models
   3  *
   4  * Versatile Express (VE) system model
   5  * ARMCortexA15x4CT
   6  * ARMCortexA7x4CT
   7  * RTSM_VE_Cortex_A15x4_A7x4.lisa
   8  */
   9
  10 /dts-v1/;
  11
  12 /memreserve/ 0xff000000 0x01000000;
  13
  14 / {
  15         model = "RTSM_VE_CortexA15x4-A7x4";
  16         arm,vexpress,site = <0xf>;
  17         compatible = "arm,rtsm_ve,cortex_a15x4_a7x4", "arm,vexpress";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         chosen { };
  23
  24         aliases {
  25                 serial0 = &v2m_serial0;
  26                 serial1 = &v2m_serial1;
  27                 serial2 = &v2m_serial2;
  28                 serial3 = &v2m_serial3;
  29         };
  30
  31         clusters {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cluster0: cluster@0 {
  36                         reg = <0>;
  37 //                      freqs = <500000000 600000000 700000000 800000000 900000000 1000000000 1100000000 1200000000>;
  38                         cores {
  39                                 #address-cells = <1>;
  40                                 #size-cells = <0>;
  41
  42                                 core0: core@0 {
  43                                         reg = <0>;
  44                                 };
  45
  46                                 core1: core@1 {
  47                                         reg = <1>;
  48                                 };
  49
  50                                 core2: core@2 {
  51                                         reg = <2>;
  52                                 };
  53
  54                                 core3: core@3 {
  55                                         reg = <3>;
  56                                 };
  57
  58                         };
  59                 };
  60
  61                 cluster1: cluster@1 {
  62                         reg = <1>;
  63 //                      freqs = <350000000 400000000 500000000 600000000 700000000 800000000 900000000 1000000000>;
  64                         cores {
  65                                 #address-cells = <1>;
  66                                 #size-cells = <0>;
  67
  68                                 core4: core@0 {
  69                                         reg = <0>;
  70                                 };
  71
  72                                 core5: core@1 {
  73                                         reg = <1>;
  74                                 };
  75
  76                                 core6: core@2 {
  77                                         reg = <2>;
  78                                 };
  79
  80                                 core7: core@3 {
  81                                         reg = <3>;
  82                                 };
  83
  84                         };
  85                 };
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 cpu0: cpu@0 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a15";
  95                         reg = <0>;
  96                         cluster = <&cluster0>;
  97                         core = <&core0>;
  98 //                      clock-frequency = <1000000000>;
  99                         cci-control-port = <&cci_control1>;
 100                 };
 101
 102                 cpu1: cpu@1 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a15";
 105                         reg = <1>;
 106                         cluster = <&cluster0>;
 107                         core = <&core1>;
 108 //                      clock-frequency = <1000000000>;
 109                         cci-control-port = <&cci_control1>;
 110                 };
 111
 112                 cpu2: cpu@2 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a15";
 115                         reg = <2>;
 116                         cluster = <&cluster0>;
 117                         core = <&core2>;
 118 //                      clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control1>;
 120                 };
 121
 122                 cpu3: cpu@3 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a15";
 125                         reg = <3>;
 126                         cluster = <&cluster0>;
 127                         core = <&core3>;
 128 //                      clock-frequency = <1000000000>;
 129                         cci-control-port = <&cci_control1>;
 130                 };
 131
 132                 cpu4: cpu@4 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a7";
 135                         reg = <0x100>;
 136                         cluster = <&cluster1>;
 137                         core = <&core4>;
 138 //                      clock-frequency = <800000000>;
 139                         cci-control-port = <&cci_control2>;
 140                 };
 141
 142                 cpu5: cpu@5 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a7";
 145                         reg = <0x101>;
 146                         cluster = <&cluster1>;
 147                         core = <&core5>;
 148 //                      clock-frequency = <800000000>;
 149                         cci-control-port = <&cci_control2>;
 150                 };
 151
 152                 cpu6: cpu@6 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a7";
 155                         reg = <0x102>;
 156                         cluster = <&cluster1>;
 157                         core = <&core6>;
 158 //                      clock-frequency = <800000000>;
 159                         cci-control-port = <&cci_control2>;
 160                 };
 161
 162                 cpu7: cpu@7 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a7";
 165                         reg = <0x103>;
 166                         cluster = <&cluster1>;
 167                         core = <&core7>;
 168 //                      clock-frequency = <800000000>;
 169                         cci-control-port = <&cci_control2>;
 170                 };
 171         };
 172
 173         memory@80000000 {
 174                 device_type = "memory";
 175                 reg = <0 0x80000000 0 0x80000000>;
 176         };
 177
 178         cci@2c090000 {
 179                 compatible = "arm,cci-400", "arm,cci";
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 reg = <0 0x2c090000 0 0x1000>;
 183                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 184
 185                 cci_control1: slave-if@4000 {
 186                         compatible = "arm,cci-400-ctrl-if";
 187                         interface-type = "ace";
 188                         reg = <0x4000 0x1000>;
 189                 };
 190
 191                 cci_control2: slave-if@5000 {
 192                         compatible = "arm,cci-400-ctrl-if";
 193                         interface-type = "ace";
 194                         reg = <0x5000 0x1000>;
 195                 };
 196         };
 197
 198         dcscb@60000000 {
 199                 compatible = "arm,rtsm,dcscb";
 200                 reg = <0 0x60000000 0 0x1000>;
 201         };
 202
 203         gic: interrupt-controller@2c001000 {
 204                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 205                 #interrupt-cells = <3>;
 206                 #address-cells = <0>;
 207                 interrupt-controller;
 208                 reg = <0 0x2c001000 0 0x1000>,
 209                       <0 0x2c002000 0 0x1000>,
 210                       <0 0x2c004000 0 0x2000>,
 211                       <0 0x2c006000 0 0x2000>;
 212                 interrupts = <1 9 0xf04>;
 213
 214                 gic-cpuif@0 {
 215                         compatible = "arm,gic-cpuif";
 216                         cpuif-id = <0>;
 217                         cpu = <&cpu0>;
 218                 };
 219                 gic-cpuif@1 {
 220                         compatible = "arm,gic-cpuif";
 221                         cpuif-id = <1>;
 222                         cpu = <&cpu1>;
 223                 };
 224                 gic-cpuif@2 {
 225                         compatible = "arm,gic-cpuif";
 226                         cpuif-id = <2>;
 227                         cpu = <&cpu2>;
 228                 };
 229                 gic-cpuif@3 {
 230                         compatible = "arm,gic-cpuif";
 231                         cpuif-id = <3>;
 232                         cpu = <&cpu3>;
 233                 };
 234                 gic-cpuif@4 {
 235                         compatible = "arm,gic-cpuif";
 236                         cpuif-id = <4>;
 237                         cpu = <&cpu4>;
 238                 };
 239                 gic-cpuif@5 {
 240                         compatible = "arm,gic-cpuif";
 241                         cpuif-id = <5>;
 242                         cpu = <&cpu5>;
 243                 };
 244                 gic-cpuif@6 {
 245                         compatible = "arm,gic-cpuif";
 246                         cpuif-id = <6>;
 247                         cpu = <&cpu6>;
 248                 };
 249                 gic-cpuif@7 {
 250                         compatible = "arm,gic-cpuif";
 251                         cpuif-id = <7>;
 252                         cpu = <&cpu7>;
 253                 };
 254         };
 255
 256         timer {
 257                 compatible = "arm,armv7-timer";
 258                 interrupts = <1 13 0xf08>,
 259                              <1 14 0xf08>,
 260                              <1 11 0xf08>,
 261                              <1 10 0xf08>;
 262         };
 263
 264         dcc {
 265                 compatible = "arm,vexpress,config-bus";
 266                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 267
 268                 osc@0 {
 269                         /* ACLK clock to the AXI master port on the test chip */
 270                         compatible = "arm,vexpress-osc";
 271                         arm,vexpress-sysreg,func = <1 0>;
 272                         freq-range = <30000000 50000000>;
 273                         #clock-cells = <0>;
 274                         clock-output-names = "extsaxiclk";
 275                 };
 276
 277                 oscclk1: osc@1 {
 278                         /* Reference clock for the CLCD */
 279                         compatible = "arm,vexpress-osc";
 280                         arm,vexpress-sysreg,func = <1 1>;
 281                         freq-range = <10000000 80000000>;
 282                         #clock-cells = <0>;
 283                         clock-output-names = "clcdclk";
 284                 };
 285
 286                 smbclk: oscclk2: osc@2 {
 287                         /* Reference clock for the test chip internal PLLs */
 288                         compatible = "arm,vexpress-osc";
 289                         arm,vexpress-sysreg,func = <1 2>;
 290                         freq-range = <33000000 100000000>;
 291                         #clock-cells = <0>;
 292                         clock-output-names = "tcrefclk";
 293                 };
 294         };
 295
 296         smb {
 297                 compatible = "simple-bus";
 298
 299                 #address-cells = <2>;
 300                 #size-cells = <1>;
 301                 ranges = <0 0 0 0x08000000 0x04000000>,
 302                          <1 0 0 0x14000000 0x04000000>,
 303                          <2 0 0 0x18000000 0x04000000>,
 304                          <3 0 0 0x1c000000 0x04000000>,
 305                          <4 0 0 0x0c000000 0x04000000>,
 306                          <5 0 0 0x10000000 0x04000000>;
 307
 308                 #interrupt-cells = <1>;
 309                 interrupt-map-mask = <0 0 63>;
 310                 interrupt-map = <0 0  0 &gic 0  0 4>,
 311                                 <0 0  1 &gic 0  1 4>,
 312                                 <0 0  2 &gic 0  2 4>,
 313                                 <0 0  3 &gic 0  3 4>,
 314                                 <0 0  4 &gic 0  4 4>,
 315                                 <0 0  5 &gic 0  5 4>,
 316                                 <0 0  6 &gic 0  6 4>,
 317                                 <0 0  7 &gic 0  7 4>,
 318                                 <0 0  8 &gic 0  8 4>,
 319                                 <0 0  9 &gic 0  9 4>,
 320                                 <0 0 10 &gic 0 10 4>,
 321                                 <0 0 11 &gic 0 11 4>,
 322                                 <0 0 12 &gic 0 12 4>,
 323                                 <0 0 13 &gic 0 13 4>,
 324                                 <0 0 14 &gic 0 14 4>,
 325                                 <0 0 15 &gic 0 15 4>,
 326                                 <0 0 16 &gic 0 16 4>,
 327                                 <0 0 17 &gic 0 17 4>,
 328                                 <0 0 18 &gic 0 18 4>,
 329                                 <0 0 19 &gic 0 19 4>,
 330                                 <0 0 20 &gic 0 20 4>,
 331                                 <0 0 21 &gic 0 21 4>,
 332                                 <0 0 22 &gic 0 22 4>,
 333                                 <0 0 23 &gic 0 23 4>,
 334                                 <0 0 24 &gic 0 24 4>,
 335                                 <0 0 25 &gic 0 25 4>,
 336                                 <0 0 26 &gic 0 26 4>,
 337                                 <0 0 27 &gic 0 27 4>,
 338                                 <0 0 28 &gic 0 28 4>,
 339                                 <0 0 29 &gic 0 29 4>,
 340                                 <0 0 30 &gic 0 30 4>,
 341                                 <0 0 31 &gic 0 31 4>,
 342                                 <0 0 32 &gic 0 32 4>,
 343                                 <0 0 33 &gic 0 33 4>,
 344                                 <0 0 34 &gic 0 34 4>,
 345                                 <0 0 35 &gic 0 35 4>,
 346                                 <0 0 36 &gic 0 36 4>,
 347                                 <0 0 37 &gic 0 37 4>,
 348                                 <0 0 38 &gic 0 38 4>,
 349                                 <0 0 39 &gic 0 39 4>,
 350                                 <0 0 40 &gic 0 40 4>,
 351                                 <0 0 41 &gic 0 41 4>,
 352                                 <0 0 42 &gic 0 42 4>;
 353
 354                 /include/ "rtsm_ve-motherboard.dtsi"
 355         };
 356 };
 357
 358 /include/ "clcd-panels.dtsi"