4 * Versatile Express (VE) system model
7 * RTSM_VE_Cortex_A15x1_A7x1.lisa
12 /memreserve/ 0xff000000 0x01000000;
15 model = "RTSM_VE_CortexA15x1-A7x1";
16 arm,vexpress,site = <0xf>;
17 compatible = "arm,rtsm_ve,cortex_a15x1_a7x1", "arm,vexpress";
18 interrupt-parent = <&gic>;
25 serial0 = &v2m_serial0;
26 serial1 = &v2m_serial1;
27 serial2 = &v2m_serial2;
28 serial3 = &v2m_serial3;
37 // freqs = <500000000 600000000 700000000 800000000 900000000 1000000000 1100000000 1200000000>;
51 // freqs = <350000000 400000000 500000000 600000000 700000000 800000000 900000000 1000000000>;
70 compatible = "arm,cortex-a15";
72 cluster = <&cluster0>;
74 // clock-frequency = <1000000000>;
75 cci-control-port = <&cci_control1>;
80 compatible = "arm,cortex-a7";
82 cluster = <&cluster1>;
84 // clock-frequency = <800000000>;
85 cci-control-port = <&cci_control2>;
90 device_type = "memory";
91 reg = <0 0x80000000 0 0x80000000>;
95 compatible = "arm,cci-400", "arm,cci";
98 reg = <0 0x2c090000 0 0x1000>;
99 ranges = <0x0 0x0 0x2c090000 0x10000>;
101 cci_control1: slave-if@4000 {
102 compatible = "arm,cci-400-ctrl-if";
103 interface-type = "ace";
104 reg = <0x4000 0x1000>;
107 cci_control2: slave-if@5000 {
108 compatible = "arm,cci-400-ctrl-if";
109 interface-type = "ace";
110 reg = <0x5000 0x1000>;
115 compatible = "arm,rtsm,dcscb";
116 reg = <0 0x60000000 0 0x1000>;
119 gic: interrupt-controller@2c001000 {
120 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
121 #interrupt-cells = <3>;
122 #address-cells = <0>;
123 interrupt-controller;
124 reg = <0 0x2c001000 0 0x1000>,
125 <0 0x2c002000 0 0x1000>,
126 <0 0x2c004000 0 0x2000>,
127 <0 0x2c006000 0 0x2000>;
128 interrupts = <1 9 0xf04>;
131 compatible = "arm,gic-cpuif";
136 compatible = "arm,gic-cpuif";
143 compatible = "arm,armv7-timer";
144 interrupts = <1 13 0xf08>,
151 compatible = "arm,vexpress,config-bus";
152 arm,vexpress,config-bridge = <&v2m_sysreg>;
155 /* ACLK clock to the AXI master port on the test chip */
156 compatible = "arm,vexpress-osc";
157 arm,vexpress-sysreg,func = <1 0>;
158 freq-range = <30000000 50000000>;
160 clock-output-names = "extsaxiclk";
164 /* Reference clock for the CLCD */
165 compatible = "arm,vexpress-osc";
166 arm,vexpress-sysreg,func = <1 1>;
167 freq-range = <10000000 80000000>;
169 clock-output-names = "clcdclk";
172 smbclk: oscclk2: osc@2 {
173 /* Reference clock for the test chip internal PLLs */
174 compatible = "arm,vexpress-osc";
175 arm,vexpress-sysreg,func = <1 2>;
176 freq-range = <33000000 100000000>;
178 clock-output-names = "tcrefclk";
183 compatible = "simple-bus";
185 #address-cells = <2>;
187 ranges = <0 0 0 0x08000000 0x04000000>,
188 <1 0 0 0x14000000 0x04000000>,
189 <2 0 0 0x18000000 0x04000000>,
190 <3 0 0 0x1c000000 0x04000000>,
191 <4 0 0 0x0c000000 0x04000000>,
192 <5 0 0 0x10000000 0x04000000>;
194 #interrupt-cells = <1>;
195 interrupt-map-mask = <0 0 63>;
196 interrupt-map = <0 0 0 &gic 0 0 4>,
206 <0 0 10 &gic 0 10 4>,
207 <0 0 11 &gic 0 11 4>,
208 <0 0 12 &gic 0 12 4>,
209 <0 0 13 &gic 0 13 4>,
210 <0 0 14 &gic 0 14 4>,
211 <0 0 15 &gic 0 15 4>,
212 <0 0 16 &gic 0 16 4>,
213 <0 0 17 &gic 0 17 4>,
214 <0 0 18 &gic 0 18 4>,
215 <0 0 19 &gic 0 19 4>,
216 <0 0 20 &gic 0 20 4>,
217 <0 0 21 &gic 0 21 4>,
218 <0 0 22 &gic 0 22 4>,
219 <0 0 23 &gic 0 23 4>,
220 <0 0 24 &gic 0 24 4>,
221 <0 0 25 &gic 0 25 4>,
222 <0 0 26 &gic 0 26 4>,
223 <0 0 27 &gic 0 27 4>,
224 <0 0 28 &gic 0 28 4>,
225 <0 0 29 &gic 0 29 4>,
226 <0 0 30 &gic 0 30 4>,
227 <0 0 31 &gic 0 31 4>,
228 <0 0 32 &gic 0 32 4>,
229 <0 0 33 &gic 0 33 4>,
230 <0 0 34 &gic 0 34 4>,
231 <0 0 35 &gic 0 35 4>,
232 <0 0 36 &gic 0 36 4>,
233 <0 0 37 &gic 0 37 4>,
234 <0 0 38 &gic 0 38 4>,
235 <0 0 39 &gic 0 39 4>,
236 <0 0 40 &gic 0 40 4>,
237 <0 0 41 &gic 0 41 4>,
238 <0 0 42 &gic 0 42 4>;
240 /include/ "rtsm_ve-motherboard.dtsi"
244 /include/ "clcd-panels.dtsi"