arch/arm/boot/dts/rtsm_ve-cortex_a9x2.dts

   1 /*
   2  * ARM Ltd. Fast Models
   3  *
   4  * Versatile Express (VE) system model
   5  * ARMCortexA9MPx2CT
   6  *
   7  * RTSM_VE_Cortex_A9x2.lisa
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "RTSM_VE_CortexA9x2";
  14         arm,vexpress,site = <0xf>;
  15         compatible = "arm,rtsm_ve,cortex_a9x2", "arm,vexpress";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         chosen { };
  21
  22         aliases {
  23                 serial0 = &v2m_serial0;
  24                 serial1 = &v2m_serial1;
  25                 serial2 = &v2m_serial2;
  26                 serial3 = &v2m_serial3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <0>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <1>;
  43                 };
  44         };
  45
  46         memory@80000000 {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x80000000>;
  49         };
  50
  51         scu@2c000000 {
  52                 compatible = "arm,cortex-a9-scu";
  53                 reg = <0x2c000000 0x58>;
  54         };
  55
  56         timer@2c000600 {
  57                 compatible = "arm,cortex-a9-twd-timer";
  58                 reg = <0x2c000600 0x20>;
  59                 interrupts = <1 13 0xf04>;
  60         };
  61
  62         watchdog@2c000620 {
  63                 compatible = "arm,cortex-a9-twd-wdt";
  64                 reg = <0x2c000620 0x20>;
  65                 interrupts = <1 14 0xf04>;
  66         };
  67
  68         gic: interrupt-controller@2c001000 {
  69                 compatible = "arm,cortex-a9-gic";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <0>;
  72                 interrupt-controller;
  73                 reg = <0x2c001000 0x1000>,
  74                       <0x2c000100 0x100>;
  75         };
  76
  77         dcc {
  78                 compatible = "arm,vexpress,config-bus";
  79                 arm,vexpress,config-bridge = <&v2m_sysreg>;
  80
  81                 osc@0 {
  82                         /* ACLK clock to the AXI master port on the test chip */
  83                         compatible = "arm,vexpress-osc";
  84                         arm,vexpress-sysreg,func = <1 0>;
  85                         freq-range = <30000000 50000000>;
  86                         #clock-cells = <0>;
  87                         clock-output-names = "extsaxiclk";
  88                 };
  89
  90                 oscclk1: osc@1 {
  91                         /* Reference clock for the CLCD */
  92                         compatible = "arm,vexpress-osc";
  93                         arm,vexpress-sysreg,func = <1 1>;
  94                         freq-range = <10000000 80000000>;
  95                         #clock-cells = <0>;
  96                         clock-output-names = "clcdclk";
  97                 };
  98
  99                 smbclk: oscclk2: osc@2 {
 100                         /* Reference clock for the test chip internal PLLs */
 101                         compatible = "arm,vexpress-osc";
 102                         arm,vexpress-sysreg,func = <1 2>;
 103                         freq-range = <33000000 100000000>;
 104                         #clock-cells = <0>;
 105                         clock-output-names = "tcrefclk";
 106                 };
 107         };
 108
 109         smb {
 110                 compatible = "simple-bus";
 111
 112                 #address-cells = <2>;
 113                 #size-cells = <1>;
 114                 ranges = <0 0 0x08000000 0x04000000>,
 115                          <1 0 0x14000000 0x04000000>,
 116                          <2 0 0x18000000 0x04000000>,
 117                          <3 0 0x1c000000 0x04000000>,
 118                          <4 0 0x0c000000 0x04000000>,
 119                          <5 0 0x10000000 0x04000000>;
 120
 121                 #interrupt-cells = <1>;
 122                 interrupt-map-mask = <0 0 63>;
 123                 interrupt-map = <0 0  0 &gic 0  0 4>,
 124                                 <0 0  1 &gic 0  1 4>,
 125                                 <0 0  2 &gic 0  2 4>,
 126                                 <0 0  3 &gic 0  3 4>,
 127                                 <0 0  4 &gic 0  4 4>,
 128                                 <0 0  5 &gic 0  5 4>,
 129                                 <0 0  6 &gic 0  6 4>,
 130                                 <0 0  7 &gic 0  7 4>,
 131                                 <0 0  8 &gic 0  8 4>,
 132                                 <0 0  9 &gic 0  9 4>,
 133                                 <0 0 10 &gic 0 10 4>,
 134                                 <0 0 11 &gic 0 11 4>,
 135                                 <0 0 12 &gic 0 12 4>,
 136                                 <0 0 13 &gic 0 13 4>,
 137                                 <0 0 14 &gic 0 14 4>,
 138                                 <0 0 15 &gic 0 15 4>,
 139                                 <0 0 16 &gic 0 16 4>,
 140                                 <0 0 17 &gic 0 17 4>,
 141                                 <0 0 18 &gic 0 18 4>,
 142                                 <0 0 19 &gic 0 19 4>,
 143                                 <0 0 20 &gic 0 20 4>,
 144                                 <0 0 21 &gic 0 21 4>,
 145                                 <0 0 22 &gic 0 22 4>,
 146                                 <0 0 23 &gic 0 23 4>,
 147                                 <0 0 24 &gic 0 24 4>,
 148                                 <0 0 25 &gic 0 25 4>,
 149                                 <0 0 26 &gic 0 26 4>,
 150                                 <0 0 27 &gic 0 27 4>,
 151                                 <0 0 28 &gic 0 28 4>,
 152                                 <0 0 29 &gic 0 29 4>,
 153                                 <0 0 30 &gic 0 30 4>,
 154                                 <0 0 31 &gic 0 31 4>,
 155                                 <0 0 32 &gic 0 32 4>,
 156                                 <0 0 33 &gic 0 33 4>,
 157                                 <0 0 34 &gic 0 34 4>,
 158                                 <0 0 35 &gic 0 35 4>,
 159                                 <0 0 36 &gic 0 36 4>,
 160                                 <0 0 37 &gic 0 37 4>,
 161                                 <0 0 38 &gic 0 38 4>,
 162                                 <0 0 39 &gic 0 39 4>,
 163                                 <0 0 40 &gic 0 40 4>,
 164                                 <0 0 41 &gic 0 41 4>,
 165                                 <0 0 42 &gic 0 42 4>;
 166
 167                 /include/ "rtsm_ve-motherboard.dtsi"
 168         };
 169 };
 170
 171 /include/ "clcd-panels.dtsi"