arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         soc {
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 compatible = "simple-bus";
  27                 ranges;
  28
  29                 gic: interrupt-controller@1013d000 {
  30                         compatible = "arm,cortex-a9-gic";
  31                         interrupt-controller;
  32                         #interrupt-cells = <3>;
  33                         reg = <0x1013d000 0x1000>,
  34                               <0x1013c100 0x0100>;
  35                 };
  36
  37                 L2: l2-cache-controller@10138000 {
  38                         compatible = "arm,pl310-cache";
  39                         reg = <0x10138000 0x1000>;
  40                         cache-unified;
  41                         cache-level = <2>;
  42                 };
  43
  44                 local-timer@1013c600 {
  45                         compatible = "arm,cortex-a9-twd-timer";
  46                         reg = <0x1013c600 0x20>;
  47                         interrupts = <GIC_PPI 13 0x304>;
  48                         clocks = <&dummy150m>;
  49                 };
  50
  51                 uart0: serial@10124000 {
  52                         compatible = "snps,dw-apb-uart";
  53                         reg = <0x10124000 0x400>;
  54                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  55                         reg-shift = <2>;
  56                         reg-io-width = <1>;
  57                         clocks = <&clk_gates1 8>;
  58                         status = "disabled";
  59                 };
  60
  61                 uart1: serial@10126000 {
  62                         compatible = "snps,dw-apb-uart";
  63                         reg = <0x10126000 0x400>;
  64                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  65                         reg-shift = <2>;
  66                         reg-io-width = <1>;
  67                         clocks = <&clk_gates1 10>;
  68                         status = "disabled";
  69                 };
  70
  71                 uart2: serial@20064000 {
  72                         compatible = "snps,dw-apb-uart";
  73                         reg = <0x20064000 0x400>;
  74                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  75                         reg-shift = <2>;
  76                         reg-io-width = <1>;
  77                         clocks = <&clk_gates1 12>;
  78                         status = "disabled";
  79                 };
  80
  81                 uart3: serial@20068000 {
  82                         compatible = "snps,dw-apb-uart";
  83                         reg = <0x20068000 0x400>;
  84                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  85                         reg-shift = <2>;
  86                         reg-io-width = <1>;
  87                         clocks = <&clk_gates1 14>;
  88                         status = "disabled";
  89                 };
  90
  91                 dwmmc@10214000 {
  92                         compatible = "rockchip,rk2928-dw-mshc";
  93                         reg = <0x10214000 0x1000>;
  94                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97
  98                         clocks = <&clk_gates5 10>, <&clk_gates2 11>;
  99                         clock-names = "biu", "ciu";
 100
 101                         status = "disabled";
 102                 };
 103
 104                 dwmmc@10218000 {
 105                         compatible = "rockchip,rk2928-dw-mshc";
 106                         reg = <0x10218000 0x1000>;
 107                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110
 111                         clocks = <&clk_gates5 11>, <&clk_gates2 13>;
 112                         clock-names = "biu", "ciu";
 113
 114                         status = "disabled";
 115                 };
 116         };
 117 };