arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29         };
  30
  31         xin24m: oscillator {
  32                 compatible = "fixed-clock";
  33                 clock-frequency = <24000000>;
  34                 #clock-cells = <0>;
  35                 clock-output-names = "xin24m";
  36         };
  37
  38         L2: l2-cache-controller@10138000 {
  39                 compatible = "arm,pl310-cache";
  40                 reg = <0x10138000 0x1000>;
  41                 cache-unified;
  42                 cache-level = <2>;
  43         };
  44
  45         scu@1013c000 {
  46                 compatible = "arm,cortex-a9-scu";
  47                 reg = <0x1013c000 0x100>;
  48         };
  49
  50         global_timer: global-timer@1013c200 {
  51                 compatible = "arm,cortex-a9-global-timer";
  52                 reg = <0x1013c200 0x20>;
  53                 interrupts = <GIC_PPI 11 0x304>;
  54                 clocks = <&cru CORE_PERI>;
  55         };
  56
  57         local_timer: local-timer@1013c600 {
  58                 compatible = "arm,cortex-a9-twd-timer";
  59                 reg = <0x1013c600 0x20>;
  60                 interrupts = <GIC_PPI 13 0x304>;
  61                 clocks = <&cru CORE_PERI>;
  62         };
  63
  64         gic: interrupt-controller@1013d000 {
  65                 compatible = "arm,cortex-a9-gic";
  66                 interrupt-controller;
  67                 #interrupt-cells = <3>;
  68                 reg = <0x1013d000 0x1000>,
  69                       <0x1013c100 0x0100>;
  70         };
  71
  72         uart0: serial@10124000 {
  73                 compatible = "snps,dw-apb-uart";
  74                 reg = <0x10124000 0x400>;
  75                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <1>;
  78                 clocks = <&cru SCLK_UART0>;
  79                 status = "disabled";
  80         };
  81
  82         uart1: serial@10126000 {
  83                 compatible = "snps,dw-apb-uart";
  84                 reg = <0x10126000 0x400>;
  85                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  86                 reg-shift = <2>;
  87                 reg-io-width = <1>;
  88                 clocks = <&cru SCLK_UART1>;
  89                 status = "disabled";
  90         };
  91
  92         mmc0: dwmmc@10214000 {
  93                 compatible = "rockchip,rk2928-dw-mshc";
  94                 reg = <0x10214000 0x1000>;
  95                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 100                 clock-names = "biu", "ciu";
 101
 102                 status = "disabled";
 103         };
 104
 105         mmc1: dwmmc@10218000 {
 106                 compatible = "rockchip,rk2928-dw-mshc";
 107                 reg = <0x10218000 0x1000>;
 108                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 109                 #address-cells = <1>;
 110                 #size-cells = <0>;
 111
 112                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 113                 clock-names = "biu", "ciu";
 114
 115                 status = "disabled";
 116         };
 117
 118         pmu: pmu@20004000 {
 119                 compatible = "rockchip,rk3066-pmu", "syscon";
 120                 reg = <0x20004000 0x100>;
 121         };
 122
 123         grf: grf@20008000 {
 124                 compatible = "syscon";
 125                 reg = <0x20008000 0x200>;
 126         };
 127
 128         i2c0: i2c@2002d000 {
 129                 compatible = "rockchip,rk3066-i2c";
 130                 reg = <0x2002d000 0x1000>;
 131                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134
 135                 rockchip,grf = <&grf>;
 136                 rockchip,bus-index = <0>;
 137
 138                 clock-names = "i2c";
 139                 clocks = <&cru PCLK_I2C0>;
 140
 141                 status = "disabled";
 142         };
 143
 144         i2c1: i2c@2002f000 {
 145                 compatible = "rockchip,rk3066-i2c";
 146                 reg = <0x2002f000 0x1000>;
 147                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150
 151                 rockchip,grf = <&grf>;
 152
 153                 clocks = <&cru PCLK_I2C1>;
 154                 clock-names = "i2c";
 155
 156                 status = "disabled";
 157         };
 158
 159         i2c2: i2c@20056000 {
 160                 compatible = "rockchip,rk3066-i2c";
 161                 reg = <0x20056000 0x1000>;
 162                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165
 166                 rockchip,grf = <&grf>;
 167
 168                 clocks = <&cru PCLK_I2C2>;
 169                 clock-names = "i2c";
 170
 171                 status = "disabled";
 172         };
 173
 174         i2c3: i2c@2005a000 {
 175                 compatible = "rockchip,rk3066-i2c";
 176                 reg = <0x2005a000 0x1000>;
 177                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180
 181                 rockchip,grf = <&grf>;
 182
 183                 clocks = <&cru PCLK_I2C3>;
 184                 clock-names = "i2c";
 185
 186                 status = "disabled";
 187         };
 188
 189         i2c4: i2c@2005e000 {
 190                 compatible = "rockchip,rk3066-i2c";
 191                 reg = <0x2005e000 0x1000>;
 192                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195
 196                 rockchip,grf = <&grf>;
 197
 198                 clocks = <&cru PCLK_I2C4>;
 199                 clock-names = "i2c";
 200
 201                 status = "disabled";
 202         };
 203
 204         uart2: serial@20064000 {
 205                 compatible = "snps,dw-apb-uart";
 206                 reg = <0x20064000 0x400>;
 207                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 208                 reg-shift = <2>;
 209                 reg-io-width = <1>;
 210                 clocks = <&cru SCLK_UART2>;
 211                 status = "disabled";
 212         };
 213
 214         uart3: serial@20068000 {
 215                 compatible = "snps,dw-apb-uart";
 216                 reg = <0x20068000 0x400>;
 217                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 218                 reg-shift = <2>;
 219                 reg-io-width = <1>;
 220                 clocks = <&cru SCLK_UART3>;
 221                 status = "disabled";
 222         };
 223 };