2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
32 compatible = "fixed-clock";
33 clock-frequency = <24000000>;
35 clock-output-names = "xin24m";
38 L2: l2-cache-controller@10138000 {
39 compatible = "arm,pl310-cache";
40 reg = <0x10138000 0x1000>;
46 compatible = "arm,cortex-a9-scu";
47 reg = <0x1013c000 0x100>;
50 global_timer: global-timer@1013c200 {
51 compatible = "arm,cortex-a9-global-timer";
52 reg = <0x1013c200 0x20>;
53 interrupts = <GIC_PPI 11 0x304>;
54 clocks = <&cru CORE_PERI>;
57 local_timer: local-timer@1013c600 {
58 compatible = "arm,cortex-a9-twd-timer";
59 reg = <0x1013c600 0x20>;
60 interrupts = <GIC_PPI 13 0x304>;
61 clocks = <&cru CORE_PERI>;
64 gic: interrupt-controller@1013d000 {
65 compatible = "arm,cortex-a9-gic";
67 #interrupt-cells = <3>;
68 reg = <0x1013d000 0x1000>,
72 uart0: serial@10124000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x10124000 0x400>;
75 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&cru SCLK_UART0>;
82 uart1: serial@10126000 {
83 compatible = "snps,dw-apb-uart";
84 reg = <0x10126000 0x400>;
85 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&cru SCLK_UART1>;
92 mmc0: dwmmc@10214000 {
93 compatible = "rockchip,rk2928-dw-mshc";
94 reg = <0x10214000 0x1000>;
95 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
100 clock-names = "biu", "ciu";
105 mmc1: dwmmc@10218000 {
106 compatible = "rockchip,rk2928-dw-mshc";
107 reg = <0x10218000 0x1000>;
108 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
109 #address-cells = <1>;
112 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
113 clock-names = "biu", "ciu";
119 compatible = "rockchip,rk3066-pmu", "syscon";
120 reg = <0x20004000 0x100>;
124 compatible = "syscon";
125 reg = <0x20008000 0x200>;
129 compatible = "rockchip,rk3066-i2c";
130 reg = <0x2002d000 0x1000>;
131 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
132 #address-cells = <1>;
135 rockchip,grf = <&grf>;
136 rockchip,bus-index = <0>;
139 clocks = <&cru PCLK_I2C0>;
145 compatible = "rockchip,rk3066-i2c";
146 reg = <0x2002f000 0x1000>;
147 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
148 #address-cells = <1>;
151 rockchip,grf = <&grf>;
153 clocks = <&cru PCLK_I2C1>;
160 compatible = "rockchip,rk3066-i2c";
161 reg = <0x20056000 0x1000>;
162 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <1>;
166 rockchip,grf = <&grf>;
168 clocks = <&cru PCLK_I2C2>;
175 compatible = "rockchip,rk3066-i2c";
176 reg = <0x2005a000 0x1000>;
177 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>;
181 rockchip,grf = <&grf>;
183 clocks = <&cru PCLK_I2C3>;
190 compatible = "rockchip,rk3066-i2c";
191 reg = <0x2005e000 0x1000>;
192 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
196 rockchip,grf = <&grf>;
198 clocks = <&cru PCLK_I2C4>;
204 uart2: serial@20064000 {
205 compatible = "snps,dw-apb-uart";
206 reg = <0x20064000 0x400>;
207 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cru SCLK_UART2>;
214 uart3: serial@20068000 {
215 compatible = "snps,dw-apb-uart";
216 reg = <0x20068000 0x400>;
217 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru SCLK_UART3>;