2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
27 clock-output-names = "xin24m";
33 compatible = "simple-bus";
37 compatible = "arm,cortex-a9-scu";
38 reg = <0x1013c000 0x100>;
42 compatible = "rockchip,rk3066-pmu", "syscon";
43 reg = <0x20004000 0x100>;
47 compatible = "syscon";
48 reg = <0x20008000 0x200>;
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
66 global-timer@1013c200 {
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x1013c200 0x20>;
69 interrupts = <GIC_PPI 11 0x304>;
70 clocks = <&cru CORE_PERI>;
73 local-timer@1013c600 {
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x1013c600 0x20>;
76 interrupts = <GIC_PPI 13 0x304>;
77 clocks = <&cru CORE_PERI>;
80 uart0: serial@10124000 {
81 compatible = "snps,dw-apb-uart";
82 reg = <0x10124000 0x400>;
83 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&cru SCLK_UART0>;
90 uart1: serial@10126000 {
91 compatible = "snps,dw-apb-uart";
92 reg = <0x10126000 0x400>;
93 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&cru SCLK_UART1>;
100 uart2: serial@20064000 {
101 compatible = "snps,dw-apb-uart";
102 reg = <0x20064000 0x400>;
103 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cru SCLK_UART2>;
110 uart3: serial@20068000 {
111 compatible = "snps,dw-apb-uart";
112 reg = <0x20068000 0x400>;
113 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru SCLK_UART3>;
121 compatible = "rockchip,rk2928-dw-mshc";
122 reg = <0x10214000 0x1000>;
123 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
127 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
128 clock-names = "biu", "ciu";
134 compatible = "rockchip,rk2928-dw-mshc";
135 reg = <0x10218000 0x1000>;
136 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
137 #address-cells = <1>;
140 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
141 clock-names = "biu", "ciu";