arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29         };
  30
  31         xin24m: oscillator {
  32                 compatible = "fixed-clock";
  33                 clock-frequency = <24000000>;
  34                 #clock-cells = <0>;
  35                 clock-output-names = "xin24m";
  36         };
  37
  38         L2: l2-cache-controller@10138000 {
  39                 compatible = "arm,pl310-cache";
  40                 reg = <0x10138000 0x1000>;
  41                 cache-unified;
  42                 cache-level = <2>;
  43         };
  44
  45         scu@1013c000 {
  46                 compatible = "arm,cortex-a9-scu";
  47                 reg = <0x1013c000 0x100>;
  48         };
  49
  50         global_timer: global-timer@1013c200 {
  51                 compatible = "arm,cortex-a9-global-timer";
  52                 reg = <0x1013c200 0x20>;
  53                 interrupts = <GIC_PPI 11 0x304>;
  54                 clocks = <&cru CORE_PERI>;
  55         };
  56
  57         local_timer: local-timer@1013c600 {
  58                 compatible = "arm,cortex-a9-twd-timer";
  59                 reg = <0x1013c600 0x20>;
  60                 interrupts = <GIC_PPI 13 0x304>;
  61                 clocks = <&cru CORE_PERI>;
  62         };
  63
  64         gic: interrupt-controller@1013d000 {
  65                 compatible = "arm,cortex-a9-gic";
  66                 interrupt-controller;
  67                 #interrupt-cells = <3>;
  68                 reg = <0x1013d000 0x1000>,
  69                       <0x1013c100 0x0100>;
  70         };
  71
  72         uart0: serial@10124000 {
  73                 compatible = "snps,dw-apb-uart";
  74                 reg = <0x10124000 0x400>;
  75                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  76                 reg-shift = <2>;
  77                 reg-io-width = <1>;
  78                 clock-names = "baudclk", "apb_pclk";
  79                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  80                 status = "disabled";
  81         };
  82
  83         uart1: serial@10126000 {
  84                 compatible = "snps,dw-apb-uart";
  85                 reg = <0x10126000 0x400>;
  86                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  87                 reg-shift = <2>;
  88                 reg-io-width = <1>;
  89                 clock-names = "baudclk", "apb_pclk";
  90                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  91                 status = "disabled";
  92         };
  93
  94         usb_otg: usb@10180000 {
  95                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
  96                 reg = <0x10180000 0x40000>;
  97                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  98                 clocks = <&cru HCLK_OTG0>;
  99                 clock-names = "otg";
 100                 status = "disabled";
 101         };
 102
 103         usb_host: usb@101c0000 {
 104                 compatible = "snps,dwc2";
 105                 reg = <0x101c0000 0x40000>;
 106                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 107                 clocks = <&cru HCLK_OTG1>;
 108                 clock-names = "otg";
 109                 status = "disabled";
 110         };
 111
 112         mmc0: dwmmc@10214000 {
 113                 compatible = "rockchip,rk2928-dw-mshc";
 114                 reg = <0x10214000 0x1000>;
 115                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118
 119                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 120                 clock-names = "biu", "ciu";
 121
 122                 status = "disabled";
 123         };
 124
 125         mmc1: dwmmc@10218000 {
 126                 compatible = "rockchip,rk2928-dw-mshc";
 127                 reg = <0x10218000 0x1000>;
 128                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 133                 clock-names = "biu", "ciu";
 134
 135                 status = "disabled";
 136         };
 137
 138         pmu: pmu@20004000 {
 139                 compatible = "rockchip,rk3066-pmu", "syscon";
 140                 reg = <0x20004000 0x100>;
 141         };
 142
 143         grf: grf@20008000 {
 144                 compatible = "syscon";
 145                 reg = <0x20008000 0x200>;
 146         };
 147
 148         i2c0: i2c@2002d000 {
 149                 compatible = "rockchip,rk3066-i2c";
 150                 reg = <0x2002d000 0x1000>;
 151                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 152                 #address-cells = <1>;
 153                 #size-cells = <0>;
 154
 155                 rockchip,grf = <&grf>;
 156
 157                 clock-names = "i2c";
 158                 clocks = <&cru PCLK_I2C0>;
 159
 160                 status = "disabled";
 161         };
 162
 163         i2c1: i2c@2002f000 {
 164                 compatible = "rockchip,rk3066-i2c";
 165                 reg = <0x2002f000 0x1000>;
 166                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169
 170                 rockchip,grf = <&grf>;
 171
 172                 clocks = <&cru PCLK_I2C1>;
 173                 clock-names = "i2c";
 174
 175                 status = "disabled";
 176         };
 177
 178         pwm0: pwm@20030000 {
 179                 compatible = "rockchip,rk2928-pwm";
 180                 reg = <0x20030000 0x10>;
 181                 #pwm-cells = <2>;
 182                 clocks = <&cru PCLK_PWM01>;
 183                 status = "disabled";
 184         };
 185
 186         pwm1: pwm@20030010 {
 187                 compatible = "rockchip,rk2928-pwm";
 188                 reg = <0x20030010 0x10>;
 189                 #pwm-cells = <2>;
 190                 clocks = <&cru PCLK_PWM01>;
 191                 status = "disabled";
 192         };
 193
 194         wdt: watchdog@2004c000 {
 195                 compatible = "snps,dw-wdt";
 196                 reg = <0x2004c000 0x100>;
 197                 clocks = <&cru PCLK_WDT>;
 198                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 199                 status = "disabled";
 200         };
 201
 202         pwm2: pwm@20050020 {
 203                 compatible = "rockchip,rk2928-pwm";
 204                 reg = <0x20050020 0x10>;
 205                 #pwm-cells = <2>;
 206                 clocks = <&cru PCLK_PWM23>;
 207                 status = "disabled";
 208         };
 209
 210         pwm3: pwm@20050030 {
 211                 compatible = "rockchip,rk2928-pwm";
 212                 reg = <0x20050030 0x10>;
 213                 #pwm-cells = <2>;
 214                 clocks = <&cru PCLK_PWM23>;
 215                 status = "disabled";
 216         };
 217
 218         i2c2: i2c@20056000 {
 219                 compatible = "rockchip,rk3066-i2c";
 220                 reg = <0x20056000 0x1000>;
 221                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224
 225                 rockchip,grf = <&grf>;
 226
 227                 clocks = <&cru PCLK_I2C2>;
 228                 clock-names = "i2c";
 229
 230                 status = "disabled";
 231         };
 232
 233         i2c3: i2c@2005a000 {
 234                 compatible = "rockchip,rk3066-i2c";
 235                 reg = <0x2005a000 0x1000>;
 236                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 237                 #address-cells = <1>;
 238                 #size-cells = <0>;
 239
 240                 rockchip,grf = <&grf>;
 241
 242                 clocks = <&cru PCLK_I2C3>;
 243                 clock-names = "i2c";
 244
 245                 status = "disabled";
 246         };
 247
 248         i2c4: i2c@2005e000 {
 249                 compatible = "rockchip,rk3066-i2c";
 250                 reg = <0x2005e000 0x1000>;
 251                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254
 255                 rockchip,grf = <&grf>;
 256
 257                 clocks = <&cru PCLK_I2C4>;
 258                 clock-names = "i2c";
 259
 260                 status = "disabled";
 261         };
 262
 263         uart2: serial@20064000 {
 264                 compatible = "snps,dw-apb-uart";
 265                 reg = <0x20064000 0x400>;
 266                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg-shift = <2>;
 268                 reg-io-width = <1>;
 269                 clock-names = "baudclk", "apb_pclk";
 270                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 271                 status = "disabled";
 272         };
 273
 274         uart3: serial@20068000 {
 275                 compatible = "snps,dw-apb-uart";
 276                 reg = <0x20068000 0x400>;
 277                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 278                 reg-shift = <2>;
 279                 reg-io-width = <1>;
 280                 clock-names = "baudclk", "apb_pclk";
 281                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 282                 status = "disabled";
 283         };
 284
 285         saradc: saradc@2006c000 {
 286                 compatible = "rockchip,saradc";
 287                 reg = <0x2006c000 0x100>;
 288                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 289                 #io-channel-cells = <1>;
 290                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 291                 clock-names = "saradc", "apb_pclk";
 292                 status = "disabled";
 293         };
 294 };