2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
32 compatible = "fixed-clock";
33 clock-frequency = <24000000>;
35 clock-output-names = "xin24m";
38 L2: l2-cache-controller@10138000 {
39 compatible = "arm,pl310-cache";
40 reg = <0x10138000 0x1000>;
46 compatible = "arm,cortex-a9-scu";
47 reg = <0x1013c000 0x100>;
50 global_timer: global-timer@1013c200 {
51 compatible = "arm,cortex-a9-global-timer";
52 reg = <0x1013c200 0x20>;
53 interrupts = <GIC_PPI 11 0x304>;
54 clocks = <&cru CORE_PERI>;
57 local_timer: local-timer@1013c600 {
58 compatible = "arm,cortex-a9-twd-timer";
59 reg = <0x1013c600 0x20>;
60 interrupts = <GIC_PPI 13 0x304>;
61 clocks = <&cru CORE_PERI>;
64 gic: interrupt-controller@1013d000 {
65 compatible = "arm,cortex-a9-gic";
67 #interrupt-cells = <3>;
68 reg = <0x1013d000 0x1000>,
72 uart0: serial@10124000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x10124000 0x400>;
75 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
78 clock-names = "baudclk", "apb_pclk";
79 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
83 uart1: serial@10126000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x10126000 0x400>;
86 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
89 clock-names = "baudclk", "apb_pclk";
90 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
94 mmc0: dwmmc@10214000 {
95 compatible = "rockchip,rk2928-dw-mshc";
96 reg = <0x10214000 0x1000>;
97 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
102 clock-names = "biu", "ciu";
107 mmc1: dwmmc@10218000 {
108 compatible = "rockchip,rk2928-dw-mshc";
109 reg = <0x10218000 0x1000>;
110 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
114 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
115 clock-names = "biu", "ciu";
121 compatible = "rockchip,rk3066-pmu", "syscon";
122 reg = <0x20004000 0x100>;
126 compatible = "syscon";
127 reg = <0x20008000 0x200>;
131 compatible = "rockchip,rk3066-i2c";
132 reg = <0x2002d000 0x1000>;
133 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
134 #address-cells = <1>;
137 rockchip,grf = <&grf>;
140 clocks = <&cru PCLK_I2C0>;
146 compatible = "rockchip,rk3066-i2c";
147 reg = <0x2002f000 0x1000>;
148 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
149 #address-cells = <1>;
152 rockchip,grf = <&grf>;
154 clocks = <&cru PCLK_I2C1>;
161 compatible = "rockchip,rk2928-pwm";
162 reg = <0x20030000 0x10>;
164 clocks = <&cru PCLK_PWM01>;
169 compatible = "rockchip,rk2928-pwm";
170 reg = <0x20030010 0x10>;
172 clocks = <&cru PCLK_PWM01>;
176 wdt: watchdog@2004c000 {
177 compatible = "snps,dw-wdt";
178 reg = <0x2004c000 0x100>;
179 clocks = <&cru PCLK_WDT>;
180 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "rockchip,rk2928-pwm";
186 reg = <0x20050020 0x10>;
188 clocks = <&cru PCLK_PWM23>;
193 compatible = "rockchip,rk2928-pwm";
194 reg = <0x20050030 0x10>;
196 clocks = <&cru PCLK_PWM23>;
201 compatible = "rockchip,rk3066-i2c";
202 reg = <0x20056000 0x1000>;
203 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
204 #address-cells = <1>;
207 rockchip,grf = <&grf>;
209 clocks = <&cru PCLK_I2C2>;
216 compatible = "rockchip,rk3066-i2c";
217 reg = <0x2005a000 0x1000>;
218 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
222 rockchip,grf = <&grf>;
224 clocks = <&cru PCLK_I2C3>;
231 compatible = "rockchip,rk3066-i2c";
232 reg = <0x2005e000 0x1000>;
233 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
234 #address-cells = <1>;
237 rockchip,grf = <&grf>;
239 clocks = <&cru PCLK_I2C4>;
245 uart2: serial@20064000 {
246 compatible = "snps,dw-apb-uart";
247 reg = <0x20064000 0x400>;
248 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
251 clock-names = "baudclk", "apb_pclk";
252 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
256 uart3: serial@20068000 {
257 compatible = "snps,dw-apb-uart";
258 reg = <0x20068000 0x400>;
259 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
262 clock-names = "baudclk", "apb_pclk";
263 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
267 saradc: saradc@2006c000 {
268 compatible = "rockchip,saradc";
269 reg = <0x2006c000 0x100>;
270 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";