2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
27 clock-output-names = "xin24m";
30 L2: l2-cache-controller@10138000 {
31 compatible = "arm,pl310-cache";
32 reg = <0x10138000 0x1000>;
38 compatible = "arm,cortex-a9-scu";
39 reg = <0x1013c000 0x100>;
42 global_timer: global-timer@1013c200 {
43 compatible = "arm,cortex-a9-global-timer";
44 reg = <0x1013c200 0x20>;
45 interrupts = <GIC_PPI 11 0x304>;
46 clocks = <&cru CORE_PERI>;
49 local_timer: local-timer@1013c600 {
50 compatible = "arm,cortex-a9-twd-timer";
51 reg = <0x1013c600 0x20>;
52 interrupts = <GIC_PPI 13 0x304>;
53 clocks = <&cru CORE_PERI>;
56 gic: interrupt-controller@1013d000 {
57 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
60 reg = <0x1013d000 0x1000>,
64 uart0: serial@10124000 {
65 compatible = "snps,dw-apb-uart";
66 reg = <0x10124000 0x400>;
67 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&cru SCLK_UART0>;
74 uart1: serial@10126000 {
75 compatible = "snps,dw-apb-uart";
76 reg = <0x10126000 0x400>;
77 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&cru SCLK_UART1>;
84 mmc0: dwmmc@10214000 {
85 compatible = "rockchip,rk2928-dw-mshc";
86 reg = <0x10214000 0x1000>;
87 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
92 clock-names = "biu", "ciu";
97 mmc1: dwmmc@10218000 {
98 compatible = "rockchip,rk2928-dw-mshc";
99 reg = <0x10218000 0x1000>;
100 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
101 #address-cells = <1>;
104 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
105 clock-names = "biu", "ciu";
111 compatible = "rockchip,rk3066-pmu", "syscon";
112 reg = <0x20004000 0x100>;
116 compatible = "syscon";
117 reg = <0x20008000 0x200>;
120 uart2: serial@20064000 {
121 compatible = "snps,dw-apb-uart";
122 reg = <0x20064000 0x400>;
123 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru SCLK_UART2>;
130 uart3: serial@20068000 {
131 compatible = "snps,dw-apb-uart";
132 reg = <0x20068000 0x400>;
133 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&cru SCLK_UART3>;