arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 mshc0 = &emmc;
  30                 mshc1 = &mmc0;
  31                 mshc2 = &mmc1;
  32                 spi0 = &spi0;
  33                 spi1 = &spi1;
  34         };
  35
  36         xin24m: oscillator {
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <24000000>;
  39                 #clock-cells = <0>;
  40                 clock-output-names = "xin24m";
  41         };
  42
  43         L2: l2-cache-controller@10138000 {
  44                 compatible = "arm,pl310-cache";
  45                 reg = <0x10138000 0x1000>;
  46                 cache-unified;
  47                 cache-level = <2>;
  48         };
  49
  50         scu@1013c000 {
  51                 compatible = "arm,cortex-a9-scu";
  52                 reg = <0x1013c000 0x100>;
  53         };
  54
  55         global_timer: global-timer@1013c200 {
  56                 compatible = "arm,cortex-a9-global-timer";
  57                 reg = <0x1013c200 0x20>;
  58                 interrupts = <GIC_PPI 11 0x304>;
  59                 clocks = <&cru CORE_PERI>;
  60         };
  61
  62         local_timer: local-timer@1013c600 {
  63                 compatible = "arm,cortex-a9-twd-timer";
  64                 reg = <0x1013c600 0x20>;
  65                 interrupts = <GIC_PPI 13 0x304>;
  66                 clocks = <&cru CORE_PERI>;
  67         };
  68
  69         gic: interrupt-controller@1013d000 {
  70                 compatible = "arm,cortex-a9-gic";
  71                 interrupt-controller;
  72                 #interrupt-cells = <3>;
  73                 reg = <0x1013d000 0x1000>,
  74                       <0x1013c100 0x0100>;
  75         };
  76
  77         uart0: serial@10124000 {
  78                 compatible = "snps,dw-apb-uart";
  79                 reg = <0x10124000 0x400>;
  80                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  81                 reg-shift = <2>;
  82                 reg-io-width = <1>;
  83                 clock-names = "baudclk", "apb_pclk";
  84                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  85                 status = "disabled";
  86         };
  87
  88         uart1: serial@10126000 {
  89                 compatible = "snps,dw-apb-uart";
  90                 reg = <0x10126000 0x400>;
  91                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  92                 reg-shift = <2>;
  93                 reg-io-width = <1>;
  94                 clock-names = "baudclk", "apb_pclk";
  95                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  96                 status = "disabled";
  97         };
  98
  99         usb_otg: usb@10180000 {
 100                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 101                 reg = <0x10180000 0x40000>;
 102                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 103                 clocks = <&cru HCLK_OTG0>;
 104                 clock-names = "otg";
 105                 status = "disabled";
 106         };
 107
 108         usb_host: usb@101c0000 {
 109                 compatible = "snps,dwc2";
 110                 reg = <0x101c0000 0x40000>;
 111                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 112                 clocks = <&cru HCLK_OTG1>;
 113                 clock-names = "otg";
 114                 status = "disabled";
 115         };
 116
 117         mmc0: dwmmc@10214000 {
 118                 compatible = "rockchip,rk2928-dw-mshc";
 119                 reg = <0x10214000 0x1000>;
 120                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 121
 122                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 123                 clock-names = "biu", "ciu";
 124
 125                 status = "disabled";
 126         };
 127
 128         mmc1: dwmmc@10218000 {
 129                 compatible = "rockchip,rk2928-dw-mshc";
 130                 reg = <0x10218000 0x1000>;
 131                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 132
 133                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 134                 clock-names = "biu", "ciu";
 135
 136                 status = "disabled";
 137         };
 138
 139         emmc: dwmmc@1021c000 {
 140                 compatible = "rockchip,rk2928-dw-mshc";
 141                 reg = <0x1021c000 0x1000>;
 142                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 143
 144                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 145                 clock-names = "biu", "ciu";
 146
 147                 status = "disabled";
 148         };
 149
 150         pmu: pmu@20004000 {
 151                 compatible = "rockchip,rk3066-pmu", "syscon";
 152                 reg = <0x20004000 0x100>;
 153         };
 154
 155         grf: grf@20008000 {
 156                 compatible = "syscon";
 157                 reg = <0x20008000 0x200>;
 158         };
 159
 160         i2c0: i2c@2002d000 {
 161                 compatible = "rockchip,rk3066-i2c";
 162                 reg = <0x2002d000 0x1000>;
 163                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 164                 #address-cells = <1>;
 165                 #size-cells = <0>;
 166
 167                 rockchip,grf = <&grf>;
 168
 169                 clock-names = "i2c";
 170                 clocks = <&cru PCLK_I2C0>;
 171
 172                 status = "disabled";
 173         };
 174
 175         i2c1: i2c@2002f000 {
 176                 compatible = "rockchip,rk3066-i2c";
 177                 reg = <0x2002f000 0x1000>;
 178                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181
 182                 rockchip,grf = <&grf>;
 183
 184                 clocks = <&cru PCLK_I2C1>;
 185                 clock-names = "i2c";
 186
 187                 status = "disabled";
 188         };
 189
 190         pwm0: pwm@20030000 {
 191                 compatible = "rockchip,rk2928-pwm";
 192                 reg = <0x20030000 0x10>;
 193                 #pwm-cells = <2>;
 194                 clocks = <&cru PCLK_PWM01>;
 195                 status = "disabled";
 196         };
 197
 198         pwm1: pwm@20030010 {
 199                 compatible = "rockchip,rk2928-pwm";
 200                 reg = <0x20030010 0x10>;
 201                 #pwm-cells = <2>;
 202                 clocks = <&cru PCLK_PWM01>;
 203                 status = "disabled";
 204         };
 205
 206         wdt: watchdog@2004c000 {
 207                 compatible = "snps,dw-wdt";
 208                 reg = <0x2004c000 0x100>;
 209                 clocks = <&cru PCLK_WDT>;
 210                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 211                 status = "disabled";
 212         };
 213
 214         pwm2: pwm@20050020 {
 215                 compatible = "rockchip,rk2928-pwm";
 216                 reg = <0x20050020 0x10>;
 217                 #pwm-cells = <2>;
 218                 clocks = <&cru PCLK_PWM23>;
 219                 status = "disabled";
 220         };
 221
 222         pwm3: pwm@20050030 {
 223                 compatible = "rockchip,rk2928-pwm";
 224                 reg = <0x20050030 0x10>;
 225                 #pwm-cells = <2>;
 226                 clocks = <&cru PCLK_PWM23>;
 227                 status = "disabled";
 228         };
 229
 230         i2c2: i2c@20056000 {
 231                 compatible = "rockchip,rk3066-i2c";
 232                 reg = <0x20056000 0x1000>;
 233                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236
 237                 rockchip,grf = <&grf>;
 238
 239                 clocks = <&cru PCLK_I2C2>;
 240                 clock-names = "i2c";
 241
 242                 status = "disabled";
 243         };
 244
 245         i2c3: i2c@2005a000 {
 246                 compatible = "rockchip,rk3066-i2c";
 247                 reg = <0x2005a000 0x1000>;
 248                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251
 252                 rockchip,grf = <&grf>;
 253
 254                 clocks = <&cru PCLK_I2C3>;
 255                 clock-names = "i2c";
 256
 257                 status = "disabled";
 258         };
 259
 260         i2c4: i2c@2005e000 {
 261                 compatible = "rockchip,rk3066-i2c";
 262                 reg = <0x2005e000 0x1000>;
 263                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266
 267                 rockchip,grf = <&grf>;
 268
 269                 clocks = <&cru PCLK_I2C4>;
 270                 clock-names = "i2c";
 271
 272                 status = "disabled";
 273         };
 274
 275         uart2: serial@20064000 {
 276                 compatible = "snps,dw-apb-uart";
 277                 reg = <0x20064000 0x400>;
 278                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 279                 reg-shift = <2>;
 280                 reg-io-width = <1>;
 281                 clock-names = "baudclk", "apb_pclk";
 282                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 283                 status = "disabled";
 284         };
 285
 286         uart3: serial@20068000 {
 287                 compatible = "snps,dw-apb-uart";
 288                 reg = <0x20068000 0x400>;
 289                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 290                 reg-shift = <2>;
 291                 reg-io-width = <1>;
 292                 clock-names = "baudclk", "apb_pclk";
 293                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 294                 status = "disabled";
 295         };
 296
 297         saradc: saradc@2006c000 {
 298                 compatible = "rockchip,saradc";
 299                 reg = <0x2006c000 0x100>;
 300                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 301                 #io-channel-cells = <1>;
 302                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 303                 clock-names = "saradc", "apb_pclk";
 304                 status = "disabled";
 305         };
 306
 307         spi0: spi@20070000 {
 308                 compatible = "rockchip,rk3066-spi";
 309                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 310                 clock-names = "spiclk", "apb_pclk";
 311                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 312                 reg = <0x20070000 0x1000>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         spi1: spi@20074000 {
 319                 compatible = "rockchip,rk3066-spi";
 320                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 321                 clock-names = "spiclk", "apb_pclk";
 322                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 323                 reg = <0x20074000 0x1000>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328 };