arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                                 rockchip,priority = <2 2>;
 134                         };
 135                         vio1_isp_w1 {
 136                                 reg = <0xffad0180 0x20>;
 137                         };
 138                         vio0_vop {
 139                                 reg = <0xffad0400 0x20>;
 140                                 rockchip,priority = <2 2>;
 141                         };
 142                         vio0_vip {
 143                                 reg = <0xffad0480 0x20>;
 144                         };
 145                         vio0_iep {
 146                                 reg = <0xffad0500 0x20>;
 147                         };
 148                         vio2_rga_r {
 149                                 reg = <0xffad0800 0x20>;
 150                         };
 151                         vio2_rga_w {
 152                                 reg = <0xffad0880 0x20>;
 153                         };
 154                         vio1_isp_r {
 155                                 reg = <0xffad0900 0x20>;
 156                         };
 157                         /* service video */
 158                         video {
 159                                 reg = <0xffae0000 0x20>;
 160                         };
 161                         /* service hevc */
 162                         hevc_r {
 163                                 reg = <0xffaf0000 0x20>;
 164                         };
 165                         hevc_w {
 166                                 reg = <0xffaf0080 0x20>;
 167                         };
 168                 };
 169
 170                 msch {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         msch@0 {
 176                                 reg = <0xffac0000 0x40>;
 177                                 rockchip,read-latency = <0x34>;
 178                         };
 179                         msch@1 {
 180                                 reg = <0xffac0080 0x40>;
 181                                 rockchip,read-latency = <0x34>;
 182                         };
 183                 };
 184         };
 185
 186         sram: sram@ff710000 {
 187                 compatible = "mmio-sram";
 188                 reg = <0xff710000 0x8000>; /* 32k */
 189                 map-exec;
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 195                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 196                 clock-frequency = <24000000>;
 197         };
 198
 199         timer@ff810000 {
 200                 compatible = "rockchip,timer";
 201                 reg = <0xff810000 0x20>;
 202                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 203                 rockchip,broadcast = <1>;
 204         };
 205
 206         watchdog: wdt@2004c000 {
 207                 compatible = "rockchip,watch dog";
 208                 reg = <0xff800000 0x100>;
 209                 clocks = <&pclk_pd_alive>;
 210                 clock-names = "pclk_wdt";
 211                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,irq = <1>;
 213                 rockchip,timeout = <60>;
 214                 rockchip,atboot = <1>;
 215                 rockchip,debug = <0>;
 216                 status = "disabled";
 217         };
 218
 219         amba {
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222                 compatible = "arm,amba-bus";
 223                 interrupt-parent = <&gic>;
 224                 ranges;
 225
 226                 pdma0: pdma@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0xffb20000 0x4000>;
 229                         clocks = <&clk_gates10 12>;
 230                         clock-names = "apb_pclk";
 231                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 233                         #dma-cells = <1>;
 234                 };
 235
 236                 pdma1: pdma@ff250000 {
 237                         compatible = "arm,pl330", "arm,primecell";
 238                         reg = <0xff250000 0x4000>;
 239                         clocks = <&clk_gates6 3>;
 240                         clock-names = "apb_pclk";
 241                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 243                         #dma-cells = <1>;
 244                 };
 245         };
 246
 247         reset: reset@ff7601b8{
 248                 compatible = "rockchip,reset";
 249                 reg = <0xff7601b8 0x30>;
 250                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 251                 #reset-cells = <1>;
 252         };
 253
 254         nandc0: nandc@0xff400000 {
 255                 compatible = "rockchip,rk-nandc";
 256                 reg = <0xff400000 0x4000>;
 257                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 258                 nandc_id = <0>;
 259                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 260                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 261         };
 262
 263         nandc1: nandc@0xff410000 {
 264             compatible = "rockchip,rk-nandc";
 265                 reg = <0xff410000 0x4000>;
 266                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 267                 nandc_id = <1>;
 268                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 269                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 270         };
 271
 272         nandc0reg: nandc0@0xff400000 {
 273                 compatible = "rockchip,rk-nandc";
 274                 reg = <0xff400000 0x4000>;
 275         };
 276
 277         emmc: rksdmmc@ff0f0000 {
 278                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 279                 reg = <0xff0f0000 0x4000>;
 280                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 //pinctrl-names = "default",,"suspend";
 284                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 285                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 286                 clock-names = "clk_mmc", "hclk_mmc";
 287                 num-slots = <1>;
 288                 fifo-depth = <0x100>;
 289                 bus-width = <8>;
 290                 tune_regsbase = <0x218>;
 291         };
 292
 293         sdmmc: rksdmmc@ff0c0000 {
 294                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 295                 reg = <0xff0c0000 0x4000>;
 296                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 pinctrl-names = "default", "idle";
 300                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 301                 pinctrl-1 = <&sdmmc0_gpio>;
 302                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 303                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 304                 clock-names = "clk_mmc", "hclk_mmc";
 305                 num-slots = <1>;
 306                 fifo-depth = <0x100>;
 307                 bus-width = <4>;
 308                 tune_regsbase = <0x200>;
 309         };
 310
 311         sdio: rksdmmc@ff0d0000 {
 312                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 313                 reg = <0xff0d0000 0x4000>;
 314                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 pinctrl-names = "default","idle";
 318                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 319                              &sdio0_intn &sdio0_bus4>;
 320                 pinctrl-1 = <&sdio0_gpio>;
 321                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 322                 clock-names = "clk_mmc", "hclk_mmc";
 323                 num-slots = <1>;
 324                 fifo-depth = <0x100>;
 325                 bus-width = <4>;
 326                 tune_regsbase = <0x208>;
 327         };
 328
 329         sdio1: rksdmmc@ff0e0000 {
 330                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 331                 reg = <0xff0e0000 0x4000>;
 332                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 //pinctrl-names = "default","suspend";
 336                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 337                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 338                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 339                 clock-names = "clk_mmc", "hclk_mmc";
 340                 num-slots = <1>;
 341                 fifo-depth = <0x100>;
 342                 bus-width = <4>;
 343                 status = "disabled";
 344         };
 345
 346         spi0: spi@ff110000 {
 347                 compatible = "rockchip,rockchip-spi";
 348                 reg = <0xff110000 0x1000>;
 349                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 354                 rockchip,spi-src-clk = <0>;
 355                 num-cs = <2>;
 356                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 357                 clock-names = "spi","pclk_spi0";
 358                 dmas = <&pdma1 11>, <&pdma1 12>;
 359                 #dma-cells = <2>;
 360                 dma-names = "tx", "rx";
 361                 status = "disabled";
 362         };
 363
 364         spi1: spi@ff120000 {
 365                 compatible = "rockchip,rockchip-spi";
 366                 reg = <0xff120000 0x1000>;
 367                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 372                 rockchip,spi-src-clk = <1>;
 373                 num-cs = <1>;
 374                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 375                 clock-names = "spi","pclk_spi1";
 376                 dmas = <&pdma1 13>, <&pdma1 14>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 status = "disabled";
 380         };
 381
 382         spi2: spi@ff130000 {
 383                 compatible = "rockchip,rockchip-spi";
 384                 reg = <0xff130000 0x1000>;
 385                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 390                 rockchip,spi-src-clk = <2>;
 391                 num-cs = <2>;
 392                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 393                 clock-names = "spi","pclk_spi2";
 394                 dmas = <&pdma1 15>, <&pdma1 16>;
 395                 #dma-cells = <2>;
 396                 dma-names = "tx", "rx";
 397                 status = "disabled";
 398         };
 399
 400         uart_bt: serial@ff180000 {
 401                 compatible = "rockchip,serial";
 402                 reg = <0xff180000 0x100>;
 403                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 404                 clock-frequency = <24000000>;
 405                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 406                 clock-names = "sclk_uart", "pclk_uart";
 407                 reg-shift = <2>;
 408                 reg-io-width = <4>;
 409                 dmas = <&pdma1 1>, <&pdma1 2>;
 410                 #dma-cells = <2>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 413                 status = "disabled";
 414         };
 415
 416         uart_bb: serial@ff190000 {
 417                 compatible = "rockchip,serial";
 418                 reg = <0xff190000 0x100>;
 419                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 420                 clock-frequency = <24000000>;
 421                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 422                 clock-names = "sclk_uart", "pclk_uart";
 423                 reg-shift = <2>;
 424                 reg-io-width = <4>;
 425                 dmas = <&pdma1 3>, <&pdma1 4>;
 426                 #dma-cells = <2>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 429                 status = "disabled";
 430         };
 431
 432         uart_dbg: serial@ff690000 {
 433                 compatible = "rockchip,serial";
 434                 reg = <0xff690000 0x100>;
 435                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 436                 clock-frequency = <24000000>;
 437                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 438                 clock-names = "sclk_uart", "pclk_uart";
 439                 reg-shift = <2>;
 440                 reg-io-width = <4>;
 441                 dmas = <&pdma0 4>, <&pdma0 5>;
 442                 #dma-cells = <2>;
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&uart2_xfer>;
 445                 status = "disabled";
 446         };
 447
 448         uart_gps: serial@ff1b0000 {
 449                 compatible = "rockchip,serial";
 450                 reg = <0xff1b0000 0x100>;
 451                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 452                 clock-frequency = <24000000>;
 453                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 454                 clock-names = "sclk_uart", "pclk_uart";
 455                 current-speed = <115200>;
 456                 reg-shift = <2>;
 457                 reg-io-width = <4>;
 458                 dmas = <&pdma1 7>, <&pdma1 8>;
 459                 #dma-cells = <2>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 462                 status = "disabled";
 463         };
 464
 465         uart_exp: serial@ff1c0000 {
 466                 compatible = "rockchip,serial";
 467                 reg = <0xff1c0000 0x100>;
 468                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 469                 clock-frequency = <24000000>;
 470                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 471                 clock-names = "sclk_uart", "pclk_uart";
 472                 reg-shift = <2>;
 473                 reg-io-width = <4>;
 474                 dmas = <&pdma1 9>, <&pdma1 10>;
 475                 #dma-cells = <2>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 478                 status = "disabled";
 479         };
 480
 481         fiq-debugger {
 482                 compatible = "rockchip,fiq-debugger";
 483                 rockchip,serial-id = <2>;
 484                 rockchip,signal-irq = <106>;
 485                 rockchip,wake-irq = <0>;
 486                 status = "disabled";
 487         };
 488
 489         rockchip_clocks_init: clocks-init{
 490                 compatible = "rockchip,clocks-init";
 491                 rockchip,clocks-init-parent =
 492                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 493                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 494                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 495                         <&usbphy_480m &otgphy2_480m>;
 496                 rockchip,clocks-init-rate =
 497                         <&clk_core 792000000>,  <&clk_gpll 297000000>,
 498                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 499                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 500                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 501                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 502                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 503                         <&clk_gpu 200000000>,   /*<&aclk_vio0 300000000>,
 504                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/
 505                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 506                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 507                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 508                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 509                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 510                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 511                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 512                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 513                 /* rockchip,clocks-uboot-has-init =
 514                         <&aclk_vio0>; */
 515         };
 516
 517         clocks-enable {
 518                 compatible = "rockchip,clocks-enable";
 519                 clocks =
 520                                 /*PLL*/
 521                                 <&clk_dpll>, <&clk_gpll>,
 522
 523                                 /*PD_CORE*/
 524                                 <&clk_gates0 2>, <&clk_core0>,
 525                                 <&clk_core1>, <&clk_core2>,
 526                                 <&clk_core3>, <&clk_l2ram>,
 527                                 <&aclk_core_m0>, <&aclk_core_mp>,
 528                                 <&atclk_core>, <&pclk_dbg_src>,
 529                                 <&clk_gates12 9>, <&clk_gates12 10>,
 530                                 <&clk_gates12 11>,
 531
 532                                 /*PD_BUS*/
 533                                 <&aclk_bus>, <&clk_gates0 3>,
 534                                 <&hclk_bus>, <&pclk_bus>,
 535                                 <&clk_gates13 8>,
 536                                 <&clk_gates0 7>,
 537
 538                                 /*TIMER*/
 539                                 <&clk_gates1 0>, <&clk_gates1 1>,
 540                                 <&clk_gates1 2>, <&clk_gates1 3>,
 541                                 <&clk_gates1 4>, <&clk_gates1 5>,
 542
 543                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 544
 545                                 /*PD_PERI*/
 546                                 <&aclk_peri>, <&hclk_peri>,
 547                                 <&pclk_peri>,
 548
 549                                 /*JTAG*/
 550                                 /*<&clk_gates4 14>,*/
 551
 552                                 /*aclk_bus*/
 553                                 <&clk_gates10 5>,/*aclk_intmem0*/
 554                                 <&clk_gates10 6>,/*aclk_intmem1*/
 555                                 <&clk_gates10 7>,/*aclk_intmem2*/
 556                                 /*<&clk_gates10 12>,*//*aclk_dma1*/
 557                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 558                                 <&clk_gates10 4>,/*aclk_intmem*/
 559
 560                                 /*hclk_bus*/
 561                                 <&clk_gates10 9>,/*hclk_rom*/
 562
 563                                 /*pclk_bus*/
 564                                 <&clk_gates10 1>,/*pclk_timer*/
 565                                 <&clk_gates10 9>,/*rom*/
 566                                 <&clk_gates10 13>,/*aclk strc*/
 567
 568                                 <&clk_gates12 8>,/*aclk strc*/
 569
 570                                 /*aclk_peri*/
 571                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 572                                 /*<&clk_gates6 3>,*//*aclk_dmac2*/
 573                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 574                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 575
 576                                 /*hclk_peri*/
 577                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 578                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 579                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 580                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 581
 582                                 /*pclk_peri*/
 583                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 584
 585                                 /*pclk_pd_alive*/
 586                                 <&clk_gates14 11>,/*pclk_grf*/
 587                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 588
 589                                 /*pclk_pd_pmu*/
 590                                 <&clk_gates17 0>,/*pclk_pmu*/
 591                                 <&clk_gates17 1>,/*pclk_intmem1*/
 592                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 593                                 <&clk_gates17 3>,/*pclk_sgrf*/
 594
 595                                 /*UART*/
 596                                 <&clk_gates11 9>,/*pclk_uart2*/
 597
 598                                 /*480M*/
 599                                 <&usbphy_480m>;
 600         };
 601
 602         i2c0: i2c@ff650000 {
 603                 compatible = "rockchip,rk30-i2c";
 604                 reg = <0xff650000 0x1000>;
 605                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 pinctrl-names = "default", "gpio";
 609                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 610                 pinctrl-1 = <&i2c0_gpio>;
 611                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 612                 clocks = <&clk_gates10 2>;
 613                 rockchip,check-idle = <1>;
 614                 status = "disabled";
 615         };
 616
 617         i2c1: i2c@ff140000 {
 618                 compatible = "rockchip,rk30-i2c";
 619                 reg = <0xff140000 0x1000>;
 620                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 pinctrl-names = "default", "gpio";
 624                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 625                 pinctrl-1 = <&i2c1_gpio>;
 626                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 627                 clocks = <&clk_gates6 13>;
 628                 rockchip,check-idle = <1>;
 629                 status = "disabled";
 630         };
 631
 632         i2c2: i2c@ff660000 {
 633                 compatible = "rockchip,rk30-i2c";
 634                 reg = <0xff660000 0x1000>;
 635                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 pinctrl-names = "default", "gpio";
 639                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 640                 pinctrl-1 = <&i2c2_gpio>;
 641                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 642                 clocks = <&clk_gates10 3>;
 643                 rockchip,check-idle = <1>;
 644                 status = "disabled";
 645         };
 646
 647         i2c3: i2c@ff150000 {
 648                 compatible = "rockchip,rk30-i2c";
 649                 reg = <0xff150000 0x1000>;
 650                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 pinctrl-names = "default", "gpio";
 654                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 655                 pinctrl-1 = <&i2c3_gpio>;
 656                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 657                 clocks = <&clk_gates6 14>;
 658                 rockchip,check-idle = <1>;
 659                 status = "disabled";
 660         };
 661
 662         i2c4: i2c@ff160000 {
 663                 compatible = "rockchip,rk30-i2c";
 664                 reg = <0xff160000 0x1000>;
 665                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 666                 #address-cells = <1>;
 667                 #size-cells = <0>;
 668                 pinctrl-names = "default", "gpio";
 669                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 670                 pinctrl-1 = <&i2c4_gpio>;
 671                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 672                 clocks = <&clk_gates6 15>;
 673                 rockchip,check-idle = <1>;
 674                 status = "disabled";
 675         };
 676
 677         i2c5: i2c@ff170000 {
 678                 compatible = "rockchip,rk30-i2c";
 679                 reg = <0xff170000 0x1000>;
 680                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 681                 #address-cells = <1>;
 682                 #size-cells = <0>;
 683                 pinctrl-names = "default", "gpio";
 684                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 685                 pinctrl-1 = <&i2c5_gpio>;
 686                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 687                 clocks = <&clk_gates7 0>;
 688                 rockchip,check-idle = <1>;
 689                 status = "disabled";
 690         };
 691
 692         fb: fb{
 693                 compatible = "rockchip,rk-fb";
 694                 rockchip,disp-mode = <DUAL>;
 695         };
 696
 697         rk_screen: rk_screen{
 698                         compatible = "rockchip,screen";
 699         };
 700
 701         dsihost0: mipi@ff960000{
 702                 compatible = "rockchip,rk32-dsi";
 703                 rockchip,prop = <0>;
 704                 reg = <0xff960000 0x4000>;
 705                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 706                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 707                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 708                 status = "disabled";
 709         };
 710
 711         dsihost1: mipi@ff964000{
 712                 compatible = "rockchip,rk32-dsi";
 713                 rockchip,prop = <1>;
 714                 reg = <0xff964000 0x4000>;
 715                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 717                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 718                 status = "disabled";
 719         };
 720
 721         lvds: lvds@ff96c000 {
 722                 compatible = "rockchip,rk32-lvds";
 723                 reg = <0xff96c000 0x4000>;
 724                 clocks = <&clk_gates16 7>;
 725                 clock-names = "pclk_lvds";
 726         };
 727
 728         edp: edp@ff970000 {
 729                 compatible = "rockchip,rk32-edp";
 730                 reg = <0xff970000 0x4000>;
 731                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 733                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 734         };
 735
 736         hdmi: hdmi@ff980000 {
 737                 compatible = "rockchip,rk3288-hdmi";
 738                 reg = <0xff980000 0x20000>;
 739                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 740                 pinctrl-names = "default", "sleep";
 741                 pinctrl-0 = <&i2c5_sda &i2c5_scl &hdmi_cec>;
 742                 pinctrl-1 = <&i2c5_gpio>;
 743                 clocks = <&clk_gates16 9>, <&clk_gates5 12>, <&clk_gates5 11>;
 744                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 745                 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;
 746                 rockchip,hdmi_audio_source = <0>;
 747                 rockchip,hdcp_enable = <0>;
 748                 rockchip,cec_enable = <0>;
 749                 status = "disabled";
 750         };
 751
 752         lcdc0: lcdc@ff930000 {
 753                 compatible = "rockchip,rk3288-lcdc";
 754                 rockchip,prop = <PRMRY>;
 755                 rockchip,pwr18 = <0>;
 756                 rockchip,iommu-enabled = <0>;
 757                 reg = <0xff930000 0x10000>;
 758                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 759                 pinctrl-names = "default", "gpio";
 760                 pinctrl-0 = <&lcdc0_lcdc>;
 761                 pinctrl-1 = <&lcdc0_gpio>;
 762                 status = "disabled";
 763                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 764                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 765         };
 766
 767         lcdc1: lcdc@ff940000 {
 768                 compatible = "rockchip,rk3288-lcdc";
 769                 rockchip,prop = <EXTEND>;
 770                 rockchip,pwr18 = <0>;
 771                 rockchip,iommu-enabled = <0>;
 772                 reg = <0xff940000 0x10000>;
 773                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 774                 status = "disabled";
 775                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 776                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 777         };
 778
 779         adc: adc@ff100000 {
 780                 compatible = "rockchip,saradc";
 781                 reg = <0xff100000 0x100>;
 782                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 783                 #io-channel-cells = <1>;
 784                 io-channel-ranges;
 785                 rockchip,adc-vref = <1800>;
 786                 clock-frequency = <1000000>;
 787                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 788                 clock-names = "saradc", "pclk_saradc";
 789                 status = "disabled";
 790         };
 791
 792         rga@ff920000 {
 793                 compatible = "rockchip,rk3288-rga2";
 794                 reg = <0xff920000 0x1000>;
 795                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 797                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 798         };
 799
 800         i2s: rockchip-i2s@0xff890000 {
 801                 compatible = "rockchip-i2s";
 802                 reg = <0xff890000 0x10000>;
 803                 i2s-id = <0>;
 804                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 805                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 806                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 807                 dmas = <&pdma0 0>, <&pdma0 1>;
 808                 //#dma-cells = <2>;
 809                 dma-names = "tx", "rx";
 810                 pinctrl-names = "default", "sleep";
 811                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 812                 pinctrl-1 = <&i2s_gpio>;
 813         };
 814
 815         spdif: rockchip-spdif@0xff8b0000 {
 816                 compatible = "rockchip-spdif";
 817                 reg = <0xff8b0000 0x10000>;     //8channel
 818                 //reg = <ff880000 0x10000>;//2channel
 819                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 820                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 821                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 822                 dmas = <&pdma0 3>;
 823                 //dmas = <&pdma0 2>; //2channel
 824                 //#dma-cells = <1>;
 825                 dma-names = "tx";
 826                 pinctrl-names = "default";
 827                 pinctrl-0 = <&spdif_tx>;
 828         };
 829
 830         vop1pwm: pwm@ff9401a0 {
 831                 compatible = "rockchip,vop-pwm";
 832                 reg = <0xff9401a0 0x10>;
 833                 #pwm-cells = <2>;
 834                 pinctrl-names = "default";
 835                 pinctrl-0 = <&vop1_pwm_pin>;
 836                 clocks = <&clk_gates13 11>, <&clk_gates15 7>, <&clk_gates15 8>;
 837                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 838                 status = "disabled";
 839         };
 840
 841         vop0pwm: pwm@ff9301a0 {
 842                 compatible = "rockchip,vop-pwm";
 843                 reg = <0xff9301a0 0x10>;
 844                 #pwm-cells = <2>;
 845                 pinctrl-names = "default";
 846                 pinctrl-0 = <&vop0_pwm_pin>;
 847                 clocks = <&clk_gates13 10>, <&clk_gates15 5>, <&clk_gates15 6>;
 848                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 849                 status = "disabled";
 850         };
 851
 852         pwm0: pwm@ff680000 {
 853                 compatible = "rockchip,rk-pwm";
 854                 reg = <0xff680000 0x10>;
 855                 #pwm-cells = <2>;
 856                 pinctrl-names = "default";
 857                 pinctrl-0 = <&pwm0_pin>;
 858                 clocks = <&clk_gates11 11>;
 859                 clock-names = "pclk_pwm";
 860                 status = "disabled";
 861         };
 862
 863         pwm1: pwm@ff680010 {
 864                 compatible = "rockchip,rk-pwm";
 865                 reg = <0xff680010 0x10>;
 866                 #pwm-cells = <2>;
 867                 pinctrl-names = "default";
 868                 pinctrl-0 = <&pwm1_pin>;
 869                 clocks = <&clk_gates11 11>;
 870                 clock-names = "pclk_pwm";
 871                 status = "disabled";
 872         };
 873
 874         pwm2: pwm@ff680020 {
 875                 compatible = "rockchip,rk-pwm";
 876                 reg = <0xff680020 0x10>;
 877                 #pwm-cells = <2>;
 878                 pinctrl-names = "default";
 879                 pinctrl-0 = <&pwm2_pin>;
 880                 clocks = <&clk_gates11 11>;
 881                 clock-names = "pclk_pwm";
 882                 status = "disabled";
 883         };
 884
 885         pwm3: pwm@ff680030 {
 886                 compatible = "rockchip,rk-pwm";
 887                 reg = <0xff680030 0x10>;
 888                 #pwm-cells = <2>;
 889                 pinctrl-names = "default";
 890                 pinctrl-0 = <&pwm3_pin>;
 891                 clocks = <&clk_gates11 11>;
 892                 clock-names = "pclk_pwm";
 893                 status = "disabled";
 894         };
 895
 896         remotectl: pwm@ff680000 {
 897                 compatible = "rockchip,remotectl-pwm";
 898                 reg = <0xff680000 0x10>;
 899                 #pwm-cells = <2>;
 900                 pinctrl-names = "default";
 901                 pinctrl-0 = <&pwm0_pin>;
 902                 clocks = <&clk_gates11 11>;
 903                 clock-names = "pclk_pwm";
 904                 remote_pwm_id = <0>;
 905                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 906                 status = "disabled";
 907         };
 908
 909         dvfs {
 910
 911                 vd_arm: vd_arm {
 912                         regulator_name = "vdd_arm";
 913                         suspend_volt = <1000>; //mV
 914                         pd_core {
 915                                 clk_core_dvfs_table: clk_core {
 916                                         operating-points = <
 917                                                 /* KHz    uV */
 918                                                 312000 1100000
 919                                                 504000 1100000
 920                                                 816000 1100000
 921                                                 1008000 1100000
 922                                                 >;
 923                                         channel = <0>;
 924                                         temp-limit-enable = <1>;
 925                                         target-temp = <80>;
 926                                         min_temp_limit = <48>;
 927                                         normal-temp-limit = <
 928                                         /*delta-temp    delta-freq*/
 929                                                 3       96000
 930                                                 6       144000
 931                                                 9       192000
 932                                                 15      384000
 933                                                 >;
 934                                         performance-temp-limit = <
 935                                                 /*temp    freq*/
 936                                                 100     816000
 937                                                 >;
 938                                         status = "okay";
 939                                         regu-mode-table = <
 940                                                 /*freq     mode*/
 941                                                 1008000    4
 942                                                 0          3
 943                                         >;
 944                                         regu-mode-en = <0>;
 945                                 };
 946                         };
 947                 };
 948
 949                 vd_logic: vd_logic {
 950                         regulator_name = "vdd_logic";
 951                         suspend_volt = <1000>; //mV
 952                         pd_ddr {
 953                                 clk_ddr_dvfs_table: clk_ddr {
 954                                         operating-points = <
 955                                                 /* KHz    uV */
 956                                                 200000 1200000
 957                                                 300000 1200000
 958                                                 400000 1200000
 959                                                 >;
 960                                         bd-freq-table = <
 961                                                 /* bandwidth   freq */
 962                                                 5000           800000
 963                                                 3500           456000
 964                                                 2600           396000
 965                                                 2000           324000
 966                                                 >;
 967                                         channel = <2>;
 968                                         status = "disabled";
 969                                 };
 970                         };
 971
 972                         pd_vio {
 973                                 aclk_vio1_dvfs_table: aclk_vio1 {
 974                                         operating-points = <
 975                                                 /* KHz    uV */
 976                                                 100000 1100000
 977                                                 500000 1100000
 978                                                 >;
 979                                         status = "okay";
 980                                 };
 981                         };
 982                 };
 983
 984                 vd_gpu: vd_gpu {
 985                         regulator_name = "vdd_gpu";
 986                         suspend_volt = <1000>; //mV
 987                         pd_gpu {
 988                                 clk_gpu_dvfs_table: clk_gpu {
 989                                         operating-points = <
 990                                                 /* KHz    uV */
 991                                                 200000 1200000
 992                                                 300000 1200000
 993                                                 400000 1200000
 994                                                 >;
 995                                         channel = <1>;
 996                                         temp-limit-enable = <0>;
 997                                         target-temp = <90>;
 998                                         min_temp_limit = <200>;
 999                                         normal-temp-limit = <
1000                                         /*delta-temp    delta-freq*/
1001                                                 3       50000
1002                                                 6       150000
1003                                                 15      250000
1004                                                 >;
1005                                         status = "okay";
1006                                         regu-mode-table = <
1007                                                 /*freq     mode*/
1008                                                 200000     4
1009                                                 0          3
1010                                         >;
1011                                         regu-mode-en = <0>;
1012                                 };
1013                         };
1014                 };
1015         };
1016
1017         ion {
1018                 compatible = "rockchip,ion";
1019                 #address-cells = <1>;
1020                 #size-cells = <0>;
1021
1022                 ion_drm: rockchip,ion-heap@5 {
1023                         compatible = "rockchip,ion-heap";
1024                         rockchip,ion_heap = <5>;
1025                         reg = <0x00000000 0x00000000>;
1026                 };
1027                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1028                         compatible = "rockchip,ion-heap";
1029                         rockchip,ion_heap = <4>;
1030                         reg = <0x00000000 0x28000000>; /* 640MB */
1031                 };
1032                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1033                         compatible = "rockchip,ion-heap";
1034                         rockchip,ion_heap = <0>;
1035                 };
1036         };
1037
1038         vpu: vpu_service@ff9a0000 {
1039                 compatible = "vpu_service";
1040                 iommu_enabled = <0>;
1041                 reg = <0xff9a0000 0x800>;
1042                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1043                 interrupt-names = "irq_enc", "irq_dec";
1044                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1045                 clock-names = "aclk_vcodec", "hclk_vcodec";
1046                 name = "vpu_service";
1047                 dev_mode = <0>;
1048                 //status = "disabled";
1049         };
1050
1051         hevc: hevc_service@ff9c0000 {
1052                 compatible = "rockchip,hevc_service";
1053                 iommu_enabled = <0>;
1054                 reg = <0xff9c0000 0x800>;
1055                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "irq_dec";
1057                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1058                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1059                 dev_mode = <1>;
1060                 name = "hevc_service";
1061                 //status = "disabled";
1062         };
1063
1064         iep: iep@ff900000 {
1065                 compatible = "rockchip,iep";
1066                 iommu_enabled = <0>;
1067                 reg = <0xff900000 0x800>;
1068                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1069                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1070                 clock-names = "aclk_iep", "hclk_iep";
1071                 status = "okay";
1072         };
1073
1074         dwc_control_usb: dwc-control-usb@ff770284 {
1075                 compatible = "rockchip,rk3288-dwc-control-usb";
1076                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1077                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1078                       <0xff770320 0x14>, <0xff770334 0x14>,
1079                       <0xff770348 0x10>, <0xff770358 0x08>,
1080                       <0xff770360 0x08>;
1081                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1082                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1083                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1084                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1085                             "GRF_UOC4_BASE";
1086                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1087                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1088                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1089                 interrupt-names = "otg_id", "otg_bvalid",
1090                                   "otg_linestate", "host0_linestate",
1091                                   "host1_linestate";
1092                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1093                          <&otgphy1_480m>, <&otgphy2_480m>;
1094                 clock-names = "hclk_usb_peri", "usbphy_480m",
1095                               "usbphy1_480m", "usbphy2_480m";
1096
1097                 usb_bc {
1098                         compatible = "synopsys,phy";
1099                                         /* offset bit mask */
1100                         rk_usb,bvalid     = <0x288 14 1>;
1101                         rk_usb,iddig      = <0x288 17 1>;
1102                         rk_usb,dcdenb     = <0x328 14 1>;
1103                         rk_usb,vdatsrcenb = <0x328  7 1>;
1104                         rk_usb,vdatdetenb = <0x328  6 1>;
1105                         rk_usb,chrgsel    = <0x328  5 1>;
1106                         rk_usb,chgdet     = <0x2cc 23 1>;
1107                         rk_usb,fsvminus   = <0x2cc 25 1>;
1108                         rk_usb,fsvplus    = <0x2cc 24 1>;
1109                 };
1110         };
1111
1112         usb0: usb@ff580000 {
1113                 compatible = "rockchip,rk3288_usb20_otg";
1114                 reg = <0xff580000 0x40000>;
1115                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1116                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1117                 clock-names = "clk_usbphy0", "hclk_usb0";
1118                 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1119                                 <&reset RK3288_SOFT_RST_USBOTGC>;
1120                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1121                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1122                 rockchip,usb-mode = <0>;
1123         };
1124
1125         usb1: usb@ff540000 {
1126                 compatible = "rockchip,rk3288_usb20_host";
1127                 reg = <0xff540000 0x40000>;
1128                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1129                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1130                          <&usbphy_480m>;
1131                 clock-names = "clk_usbphy1", "hclk_usb1",
1132                               "usbphy_480m";
1133                 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1134                                 <&reset RK3288_SOFT_RST_USBHOST1C>;
1135                 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1136         };
1137
1138         usb2: usb@ff500000 {
1139                 compatible = "rockchip,rk3288_rk_ehci_host";
1140                 reg = <0xff500000 0x20000>;
1141                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1142                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1143                 clock-names = "clk_usbphy2", "hclk_usb2";
1144                 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1145                                 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1146                 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1147         };
1148
1149         usb3: usb@ff520000 {
1150                 compatible = "rockchip,rk3288_rk_ohci_host";
1151                 reg = <0xff520000 0x20000>;
1152                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1153                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1154                 clock-names = "clk_usbphy3", "hclk_usb3";
1155                 status = "disabled";
1156         };
1157
1158         usb4: usb@ff5c0000 {
1159                 compatible = "rockchip,rk3288_rk_ehci1_host";
1160                 reg = <0xff5c0000 0x40000>;
1161                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1162                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1163                          <&ehci1phy_12m>, <&usbphy_480m>,
1164                          <&otgphy1_480m>, <&otgphy2_480m>;
1165                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1166                               "ehci1phy_12m", "usbphy_480m",
1167                               "ehci1_usbphy1", "ehci1_usbphy2";
1168                 resets = <&reset RK3288_SOFT_RST_EHCI1>, <&reset RK3288_SOFT_RST_EHCI1_AUX>,
1169                                 <&reset RK3288_SOFT_RST_EHCI1PHY>;
1170                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1171         };
1172
1173         gmac: eth@ff290000 {
1174                 compatible = "rockchip,rk3288-gmac";
1175                 reg = <0xff290000 0x10000>;
1176                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1177                 interrupt-names = "macirq";
1178                 clocks = <&clk_mac>, <&clk_gates5 0>,
1179                          <&clk_gates5 1>, <&clk_gates5 2>,
1180                          <&clk_gates5 3>, <&clk_gates8 0>,
1181                          <&clk_gates8 1>;
1182                 clock-names = "clk_mac", "mac_clk_rx",
1183                               "mac_clk_tx", "clk_mac_ref",
1184                               "clk_mac_refout", "aclk_mac",
1185                               "pclk_mac";
1186                 phy-mode = "rgmii";
1187                 pinctrl-names = "default";
1188                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1189         };
1190
1191         gpu {
1192                 compatible = "arm,malit764",
1193                              "arm,malit76x",
1194                              "arm,malit7xx",
1195                              "arm,mali-midgard";
1196                 reg = <0xffa30000 0x10000>;
1197                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1198                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1199                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1200                 interrupt-names = "JOB", "MMU", "GPU";
1201         };
1202
1203         iep_mmu {
1204                 dbgname = "iep";
1205                 compatible = "rockchip,iep_mmu";
1206                 reg = <0xff900800 0x100>;
1207                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1208                 interrupt-names = "iep_mmu";
1209         };
1210
1211         vip_mmu {
1212                 dbgname = "vip";
1213                 compatible = "rockchip,vip_mmu";
1214                 reg = <0xff950800 0x100>;
1215                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1216                 interrupt-names = "vip_mmu";
1217         };
1218
1219         vopb_mmu {
1220                 dbgname = "vopb";
1221                 compatible = "rockchip,vopb_mmu";
1222                 reg = <0xff930300 0x100>;
1223                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1224                 interrupt-names = "vopb_mmu";
1225         };
1226
1227         vopl_mmu {
1228                 dbgname = "vopl";
1229                 compatible = "rockchip,vopl_mmu";
1230                 reg = <0xff940300 0x100>;
1231                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1232                 interrupt-names = "vopl_mmu";
1233         };
1234
1235         hevc_mmu {
1236                 dbgname = "hevc";
1237                 compatible = "rockchip,hevc_mmu";
1238                 reg = <0xff9c0440 0x40>,
1239                       <0xff9c0480 0x40>;
1240                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1241                 interrupt-names = "hevc_mmu";
1242         };
1243
1244         vpu_mmu {
1245                 dbgname = "vpu";
1246                 compatible = "rockchip,vpu_mmu";
1247                 reg = <0xff9a0800 0x100>;
1248                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1249                 interrupt-names = "vpu_mmu";
1250         };
1251
1252         isp_mmu {
1253                 dbgname = "isp_mmu";
1254                 compatible = "rockchip,isp_mmu";
1255                 reg = <0xff914000 0x100>,
1256                       <0xff915000 0x100>;
1257                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1258                 interrupt-names = "isp_mmu";
1259         };
1260
1261         rockchip_suspend {
1262                 rockchip,ctrbits = <
1263                         (0
1264                          |RKPM_CTR_PWR_DMNS
1265                          |RKPM_CTR_GTCLKS
1266                          |RKPM_CTR_PLLS
1267                  //      |RKPM_CTR_GPIOS
1268                 //       |RKPM_CTR_SYSCLK_DIV
1269                 //       |RKPM_CTR_IDLEAUTO_MD
1270                 //       |RKPM_CTR_ARMOFF_LPMD
1271                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1272                         )
1273                         >;
1274                 rockchip,pmic-suspend_gpios = <
1275                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1276                         >;
1277                 rockchip,pmic-resume_gpios = <
1278                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1279                         >;
1280         };
1281
1282         isp: isp@ff910000{
1283                 compatible = "rockchip,isp";
1284                 reg = <0xff910000 0x10000>;
1285                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1286                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1287                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1288                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1289                 pinctrl-0 = <&isp_mipi>;
1290                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1291                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1292                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1293                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1294                 pinctrl-5 = <&isp_mipi>;
1295                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1296                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1297                 pinctrl-8 = <&isp_flash_trigger>;
1298                 rockchip,isp,mipiphy = <2>;
1299                 rockchip,isp,cifphy = <1>;
1300                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1301                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1302                 rockchip,isp,iommu_enable = <1>;
1303                 status = "okay";
1304         };
1305         cif: cif@ff950000 {
1306              compatible = "rockchip,cif";
1307              reg = <0xff950000 0x10000>;
1308              interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1309              clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
1310              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out";
1311              pinctrl-names = "cif_pin_all";
1312              pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1313              status = "okay";
1314              };
1315
1316         tsadc: tsadc@ff280000 {
1317                 compatible = "rockchip,tsadc";
1318                 reg = <0xff280000 0x100>;
1319                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1320                 #io-channel-cells = <1>;
1321                 io-channel-ranges;
1322                 clock-frequency = <10000>;
1323                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1324                 clock-names = "tsadc", "pclk_tsadc";
1325                 pinctrl-names = "default", "tsadc_int";
1326                 pinctrl-0 = <&tsadc_gpio>;
1327                 pinctrl-1 = <&tsadc_int>;
1328                 tsadc-ht-temp = <120>;
1329                 tsadc-ht-reset-cru = <1>;
1330                 tsadc-ht-pull-gpio = <0>;
1331                 status = "okay";
1332         };
1333
1334         lcdc_vdd_domain: lcdc-vdd-domain {
1335                 compatible = "rockchip,io_vol_domain";
1336                 pinctrl-names = "default", "1.8V", "3.3V";
1337                 pinctrl-0 = <&lcdc_vcc>;
1338                 pinctrl-1 = <&lcdc_vcc_18>;
1339                 pinctrl-2 = <&lcdc_vcc_33>;
1340         };
1341
1342         dpio_vdd_domain: dpio-vdd-domain {
1343                 compatible = "rockchip,io_vol_domain";
1344                 pinctrl-names = "default", "1.8V", "3.3V";
1345                 pinctrl-0 = <&dvp_vcc>;
1346                 pinctrl-1 = <&dvp_vcc_18>;
1347                 pinctrl-2 = <&dvp_vcc_33>;
1348         };
1349
1350         flash0_vdd_domain: flash0-vdd-domain {
1351                 compatible = "rockchip,io_vol_domain";
1352                 pinctrl-names = "default", "1.8V", "3.3V";
1353                 pinctrl-0 = <&flash0_vcc>;
1354                 pinctrl-1 = <&flash0_vcc_18>;
1355                 pinctrl-2 = <&flash0_vcc_33>;
1356         };
1357
1358         flash1_vdd_domain: flash1-vdd-domain {
1359                 compatible = "rockchip,io_vol_domain";
1360                 pinctrl-names = "default", "1.8V", "3.3V";
1361                 pinctrl-0 = <&flash1_vcc>;
1362                 pinctrl-1 = <&flash1_vcc_18>;
1363                 pinctrl-2 = <&flash1_vcc_33>;
1364         };
1365
1366         apio3_vdd_domain: apio3-vdd-domain {
1367                 compatible = "rockchip,io_vol_domain";
1368                 pinctrl-names = "default", "1.8V", "3.3V";
1369                 pinctrl-0 = <&wifi_vcc>;
1370                 pinctrl-1 = <&wifi_vcc_18>;
1371                 pinctrl-2 = <&wifi_vcc_33>;
1372         };
1373
1374         apio5_vdd_domain: apio5-vdd-domain {
1375                 compatible = "rockchip,io_vol_domain";
1376                 pinctrl-names = "default", "1.8V", "3.3V";
1377                 pinctrl-0 = <&bb_vcc>;
1378                 pinctrl-1 = <&bb_vcc_18>;
1379                 pinctrl-2 = <&bb_vcc_33>;
1380         };
1381
1382         apio4_vdd_domain: apio4-vdd-domain {
1383                 compatible = "rockchip,io_vol_domain";
1384                 pinctrl-names = "default", "1.8V", "3.3V";
1385                 pinctrl-0 = <&audio_vcc>;
1386                 pinctrl-1 = <&audio_vcc_18>;
1387                 pinctrl-2 = <&audio_vcc_33>;
1388         };
1389
1390         apio1_vdd_domain: apio0-vdd-domain {
1391                 compatible = "rockchip,io_vol_domain";
1392                 pinctrl-names = "default", "1.8V", "3.3V";
1393                 pinctrl-0 = <&gpio30_vcc>;
1394                 pinctrl-1 = <&gpio30_vcc_18>;
1395                 pinctrl-2 = <&gpio30_vcc_33>;
1396         };
1397
1398         apio2_vdd_domain: apio2-vdd-domain {
1399                 compatible = "rockchip,io_vol_domain";
1400                 pinctrl-names = "default", "1.8V", "3.3V";
1401                 pinctrl-0 = <&gpio1830_vcc>;
1402                 pinctrl-1 = <&gpio1830_vcc_18>;
1403                 pinctrl-2 = <&gpio1830_vcc_33>;
1404         };
1405
1406         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1407                 compatible = "rockchip,io_vol_domain";
1408                 pinctrl-names = "default", "1.8V", "3.3V";
1409                 pinctrl-0 = <&sdcard_vcc>;
1410                 pinctrl-1 = <&sdcard_vcc_18>;
1411                 pinctrl-2 = <&sdcard_vcc_33>;
1412         };
1413
1414         chosen {
1415                 bootargs = "vmalloc=496M";
1416         };
1417 };