arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                                 rockchip,priority = <2 2>;
 134                         };
 135                         vio1_isp_w1 {
 136                                 reg = <0xffad0180 0x20>;
 137                         };
 138                         vio0_vop {
 139                                 reg = <0xffad0400 0x20>;
 140                                 rockchip,priority = <2 2>;
 141                         };
 142                         vio0_vip {
 143                                 reg = <0xffad0480 0x20>;
 144                         };
 145                         vio0_iep {
 146                                 reg = <0xffad0500 0x20>;
 147                         };
 148                         vio2_rga_r {
 149                                 reg = <0xffad0800 0x20>;
 150                         };
 151                         vio2_rga_w {
 152                                 reg = <0xffad0880 0x20>;
 153                         };
 154                         vio1_isp_r {
 155                                 reg = <0xffad0900 0x20>;
 156                         };
 157                         /* service video */
 158                         video {
 159                                 reg = <0xffae0000 0x20>;
 160                         };
 161                         /* service hevc */
 162                         hevc_r {
 163                                 reg = <0xffaf0000 0x20>;
 164                         };
 165                         hevc_w {
 166                                 reg = <0xffaf0080 0x20>;
 167                         };
 168                 };
 169
 170                 msch {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         msch@0 {
 176                                 reg = <0xffac0000 0x40>;
 177                                 rockchip,read-latency = <0x34>;
 178                         };
 179                         msch@1 {
 180                                 reg = <0xffac0080 0x40>;
 181                                 rockchip,read-latency = <0x34>;
 182                         };
 183                 };
 184         };
 185
 186         sram: sram@ff710000 {
 187                 compatible = "mmio-sram";
 188                 reg = <0xff710000 0x8000>; /* 32k */
 189                 map-exec;
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 195                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 196                 clock-frequency = <24000000>;
 197         };
 198
 199         timer@ff810000 {
 200                 compatible = "rockchip,timer";
 201                 reg = <0xff810000 0x20>;
 202                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 203                 rockchip,broadcast = <1>;
 204         };
 205
 206         watchdog: wdt@2004c000 {
 207                 compatible = "rockchip,watch dog";
 208                 reg = <0xff800000 0x100>;
 209                 clocks = <&pclk_pd_alive>;
 210                 clock-names = "pclk_wdt";
 211                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,irq = <1>;
 213                 rockchip,timeout = <60>;
 214                 rockchip,atboot = <1>;
 215                 rockchip,debug = <0>;
 216                 status = "disabled";
 217         };
 218
 219         amba {
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222                 compatible = "arm,amba-bus";
 223                 interrupt-parent = <&gic>;
 224                 ranges;
 225
 226                 pdma0: pdma@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0xffb20000 0x4000>;
 229                         clocks = <&clk_gates10 12>;
 230                         clock-names = "apb_pclk";
 231                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 233                         #dma-cells = <1>;
 234                 };
 235
 236                 pdma1: pdma@ff250000 {
 237                         compatible = "arm,pl330", "arm,primecell";
 238                         reg = <0xff250000 0x4000>;
 239                         clocks = <&clk_gates6 3>;
 240                         clock-names = "apb_pclk";
 241                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 243                         #dma-cells = <1>;
 244                 };
 245         };
 246
 247         reset: reset@ff7601b8{
 248                 compatible = "rockchip,reset";
 249                 reg = <0xff7601b8 0x30>;
 250                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 251                 #reset-cells = <1>;
 252         };
 253
 254         nandc0: nandc@0xff400000 {
 255                 compatible = "rockchip,rk-nandc";
 256                 reg = <0xff400000 0x4000>;
 257                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 258                 nandc_id = <0>;
 259                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 260                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 261         };
 262
 263         nandc1: nandc@0xff410000 {
 264             compatible = "rockchip,rk-nandc";
 265                 reg = <0xff410000 0x4000>;
 266                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 267                 nandc_id = <1>;
 268                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 269                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 270         };
 271
 272         nandc0reg: nandc0@0xff400000 {
 273                 compatible = "rockchip,rk-nandc";
 274                 reg = <0xff400000 0x4000>;
 275         };
 276
 277         emmc: rksdmmc@ff0f0000 {
 278                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 279                 reg = <0xff0f0000 0x4000>;
 280                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 //pinctrl-names = "default",,"suspend";
 284                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 285                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 286                 clock-names = "clk_mmc", "hclk_mmc";
 287                 num-slots = <1>;
 288                 fifo-depth = <0x100>;
 289                 bus-width = <8>;
 290                 tune_regsbase = <0x218>;
 291                 cru_regsbase = <0x1d8>;
 292                 cru_reset_offset = <3>;
 293         };
 294
 295         sdmmc: rksdmmc@ff0c0000 {
 296                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 297                 reg = <0xff0c0000 0x4000>;
 298                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 pinctrl-names = "default", "idle";
 302                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 303                 pinctrl-1 = <&sdmmc0_gpio>;
 304                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 305                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 306                 clock-names = "clk_mmc", "hclk_mmc";
 307                 num-slots = <1>;
 308                 fifo-depth = <0x100>;
 309                 bus-width = <4>;
 310                 tune_regsbase = <0x200>;
 311                 cru_regsbase = <0x1d8>;
 312                 cru_reset_offset = <0>;
 313         };
 314
 315         sdio: rksdmmc@ff0d0000 {
 316                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 317                 reg = <0xff0d0000 0x4000>;
 318                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 pinctrl-names = "default","idle";
 322                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 323                              &sdio0_intn &sdio0_bus4>;
 324                 pinctrl-1 = <&sdio0_gpio>;
 325                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 326                 clock-names = "clk_mmc", "hclk_mmc";
 327                 num-slots = <1>;
 328                 fifo-depth = <0x100>;
 329                 bus-width = <4>;
 330                 tune_regsbase = <0x208>;
 331                 cru_regsbase = <0x1d8>;
 332                 cru_reset_offset = <1>;
 333         };
 334
 335         sdio1: rksdmmc@ff0e0000 {
 336                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 337                 reg = <0xff0e0000 0x4000>;
 338                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 //pinctrl-names = "default","suspend";
 342                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 343                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 344                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 345                 clock-names = "clk_mmc", "hclk_mmc";
 346                 num-slots = <1>;
 347                 fifo-depth = <0x100>;
 348                 bus-width = <4>;
 349                 cru_regsbase = <0x1d8>;
 350                 cru_reset_offset = <2>;
 351                 status = "disabled";
 352         };
 353
 354         spi0: spi@ff110000 {
 355                 compatible = "rockchip,rockchip-spi";
 356                 reg = <0xff110000 0x1000>;
 357                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 362                 rockchip,spi-src-clk = <0>;
 363                 num-cs = <2>;
 364                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 365                 clock-names = "spi","pclk_spi0";
 366                 dmas = <&pdma1 11>, <&pdma1 12>;
 367                 #dma-cells = <2>;
 368                 dma-names = "tx", "rx";
 369                 status = "disabled";
 370         };
 371
 372         spi1: spi@ff120000 {
 373                 compatible = "rockchip,rockchip-spi";
 374                 reg = <0xff120000 0x1000>;
 375                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 380                 rockchip,spi-src-clk = <1>;
 381                 num-cs = <1>;
 382                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 383                 clock-names = "spi","pclk_spi1";
 384                 dmas = <&pdma1 13>, <&pdma1 14>;
 385                 #dma-cells = <2>;
 386                 dma-names = "tx", "rx";
 387                 status = "disabled";
 388         };
 389
 390         spi2: spi@ff130000 {
 391                 compatible = "rockchip,rockchip-spi";
 392                 reg = <0xff130000 0x1000>;
 393                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 398                 rockchip,spi-src-clk = <2>;
 399                 num-cs = <2>;
 400                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 401                 clock-names = "spi","pclk_spi2";
 402                 dmas = <&pdma1 15>, <&pdma1 16>;
 403                 #dma-cells = <2>;
 404                 dma-names = "tx", "rx";
 405                 status = "disabled";
 406         };
 407
 408         uart_bt: serial@ff180000 {
 409                 compatible = "rockchip,serial";
 410                 reg = <0xff180000 0x100>;
 411                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 412                 clock-frequency = <24000000>;
 413                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 414                 clock-names = "sclk_uart", "pclk_uart";
 415                 reg-shift = <2>;
 416                 reg-io-width = <4>;
 417                 dmas = <&pdma1 1>, <&pdma1 2>;
 418                 #dma-cells = <2>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 421                 status = "disabled";
 422         };
 423
 424         uart_bb: serial@ff190000 {
 425                 compatible = "rockchip,serial";
 426                 reg = <0xff190000 0x100>;
 427                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 428                 clock-frequency = <24000000>;
 429                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 430                 clock-names = "sclk_uart", "pclk_uart";
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 dmas = <&pdma1 3>, <&pdma1 4>;
 434                 #dma-cells = <2>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 437                 status = "disabled";
 438         };
 439
 440         uart_dbg: serial@ff690000 {
 441                 compatible = "rockchip,serial";
 442                 reg = <0xff690000 0x100>;
 443                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 444                 clock-frequency = <24000000>;
 445                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 446                 clock-names = "sclk_uart", "pclk_uart";
 447                 reg-shift = <2>;
 448                 reg-io-width = <4>;
 449                 dmas = <&pdma0 4>, <&pdma0 5>;
 450                 #dma-cells = <2>;
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&uart2_xfer>;
 453                 status = "disabled";
 454         };
 455
 456         uart_gps: serial@ff1b0000 {
 457                 compatible = "rockchip,serial";
 458                 reg = <0xff1b0000 0x100>;
 459                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 460                 clock-frequency = <24000000>;
 461                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 462                 clock-names = "sclk_uart", "pclk_uart";
 463                 current-speed = <115200>;
 464                 reg-shift = <2>;
 465                 reg-io-width = <4>;
 466                 dmas = <&pdma1 7>, <&pdma1 8>;
 467                 #dma-cells = <2>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 470                 status = "disabled";
 471         };
 472
 473         uart_exp: serial@ff1c0000 {
 474                 compatible = "rockchip,serial";
 475                 reg = <0xff1c0000 0x100>;
 476                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 477                 clock-frequency = <24000000>;
 478                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 479                 clock-names = "sclk_uart", "pclk_uart";
 480                 reg-shift = <2>;
 481                 reg-io-width = <4>;
 482                 dmas = <&pdma1 9>, <&pdma1 10>;
 483                 #dma-cells = <2>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 486                 status = "disabled";
 487         };
 488
 489         fiq-debugger {
 490                 compatible = "rockchip,fiq-debugger";
 491                 rockchip,serial-id = <2>;
 492                 rockchip,signal-irq = <106>;
 493                 rockchip,wake-irq = <0>;
 494                 status = "disabled";
 495         };
 496
 497         rockchip_clocks_init: clocks-init{
 498                 compatible = "rockchip,clocks-init";
 499                 rockchip,clocks-init-parent =
 500                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 501                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 502                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 503                         <&usbphy_480m &otgphy2_480m>;
 504                 rockchip,clocks-init-rate =
 505                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 506                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 507                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 508                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 509                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 510                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 511                         <&clk_gpu 200000000>,   /*<&aclk_vio0 300000000>,
 512                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/
 513                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 514                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 515                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 516                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 517                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 518                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 519                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 520                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 521                 /* rockchip,clocks-uboot-has-init =
 522                         <&aclk_vio0>; */
 523         };
 524
 525         clocks-enable {
 526                 compatible = "rockchip,clocks-enable";
 527                 clocks =
 528                                 /*PLL*/
 529                                 <&clk_dpll>, <&clk_gpll>,
 530
 531                                 /*PD_CORE*/
 532                                 <&clk_gates0 2>, <&clk_core0>,
 533                                 <&clk_core1>, <&clk_core2>,
 534                                 <&clk_core3>, <&clk_l2ram>,
 535                                 <&aclk_core_m0>, <&aclk_core_mp>,
 536                                 <&atclk_core>, <&pclk_dbg_src>,
 537                                 <&clk_gates12 9>, <&clk_gates12 10>,
 538                                 <&clk_gates12 11>,
 539
 540                                 /*PD_BUS*/
 541                                 <&aclk_bus>, <&clk_gates0 3>,
 542                                 <&hclk_bus>, <&pclk_bus>,
 543                                 <&clk_gates13 8>,
 544                                 <&clk_gates0 7>,
 545
 546                                 /*TIMER*/
 547                                 <&clk_gates1 0>, <&clk_gates1 1>,
 548                                 <&clk_gates1 2>, <&clk_gates1 3>,
 549                                 <&clk_gates1 4>, <&clk_gates1 5>,
 550
 551                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 552
 553                                 /*PD_PERI*/
 554                                 <&aclk_peri>, <&hclk_peri>,
 555                                 <&pclk_peri>,
 556
 557                                 /*JTAG*/
 558                                 /*<&clk_gates4 14>,*/
 559
 560                                 /*aclk_bus*/
 561                                 <&clk_gates10 5>,/*aclk_intmem0*/
 562                                 <&clk_gates10 6>,/*aclk_intmem1*/
 563                                 <&clk_gates10 7>,/*aclk_intmem2*/
 564                                 /*<&clk_gates10 12>,*//*aclk_dma1*/
 565                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 566                                 <&clk_gates10 4>,/*aclk_intmem*/
 567
 568                                 /*hclk_bus*/
 569                                 <&clk_gates10 9>,/*hclk_rom*/
 570
 571                                 /*pclk_bus*/
 572                                 <&clk_gates10 1>,/*pclk_timer*/
 573                                 <&clk_gates10 9>,/*rom*/
 574                                 <&clk_gates10 13>,/*aclk strc*/
 575
 576                                 <&clk_gates12 8>,/*aclk strc*/
 577
 578                                 /*aclk_peri*/
 579                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 580                                 /*<&clk_gates6 3>,*//*aclk_dmac2*/
 581                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 582                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 583
 584                                 /*hclk_peri*/
 585                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 586                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 587                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 588                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 589
 590                                 /*pclk_peri*/
 591                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 592
 593                                 /*pclk_pd_alive*/
 594                                 <&clk_gates14 11>,/*pclk_grf*/
 595                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 596
 597                                 /*pclk_pd_pmu*/
 598                                 <&clk_gates17 0>,/*pclk_pmu*/
 599                                 <&clk_gates17 1>,/*pclk_intmem1*/
 600                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 601                                 <&clk_gates17 3>,/*pclk_sgrf*/
 602
 603                                 /*UART*/
 604                                 <&clk_gates11 9>,/*pclk_uart2*/
 605
 606                                 /*480M*/
 607                                 <&usbphy_480m>;
 608         };
 609
 610         i2c0: i2c@ff650000 {
 611                 compatible = "rockchip,rk30-i2c";
 612                 reg = <0xff650000 0x1000>;
 613                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 pinctrl-names = "default", "gpio";
 617                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 618                 pinctrl-1 = <&i2c0_gpio>;
 619                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 620                 clocks = <&clk_gates10 2>;
 621                 rockchip,check-idle = <1>;
 622                 status = "disabled";
 623         };
 624
 625         i2c1: i2c@ff140000 {
 626                 compatible = "rockchip,rk30-i2c";
 627                 reg = <0xff140000 0x1000>;
 628                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 629                 #address-cells = <1>;
 630                 #size-cells = <0>;
 631                 pinctrl-names = "default", "gpio";
 632                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 633                 pinctrl-1 = <&i2c1_gpio>;
 634                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 635                 clocks = <&clk_gates6 13>;
 636                 rockchip,check-idle = <1>;
 637                 status = "disabled";
 638         };
 639
 640         i2c2: i2c@ff660000 {
 641                 compatible = "rockchip,rk30-i2c";
 642                 reg = <0xff660000 0x1000>;
 643                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 pinctrl-names = "default", "gpio";
 647                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 648                 pinctrl-1 = <&i2c2_gpio>;
 649                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 650                 clocks = <&clk_gates10 3>;
 651                 rockchip,check-idle = <1>;
 652                 status = "disabled";
 653         };
 654
 655         i2c3: i2c@ff150000 {
 656                 compatible = "rockchip,rk30-i2c";
 657                 reg = <0xff150000 0x1000>;
 658                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 pinctrl-names = "default", "gpio";
 662                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 663                 pinctrl-1 = <&i2c3_gpio>;
 664                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 665                 clocks = <&clk_gates6 14>;
 666                 rockchip,check-idle = <1>;
 667                 status = "disabled";
 668         };
 669
 670         i2c4: i2c@ff160000 {
 671                 compatible = "rockchip,rk30-i2c";
 672                 reg = <0xff160000 0x1000>;
 673                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 pinctrl-names = "default", "gpio";
 677                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 678                 pinctrl-1 = <&i2c4_gpio>;
 679                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 680                 clocks = <&clk_gates6 15>;
 681                 rockchip,check-idle = <1>;
 682                 status = "disabled";
 683         };
 684
 685         i2c5: i2c@ff170000 {
 686                 compatible = "rockchip,rk30-i2c";
 687                 reg = <0xff170000 0x1000>;
 688                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 pinctrl-names = "default", "gpio";
 692                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 693                 pinctrl-1 = <&i2c5_gpio>;
 694                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 695                 clocks = <&clk_gates7 0>;
 696                 rockchip,check-idle = <1>;
 697                 status = "disabled";
 698         };
 699
 700         fb: fb{
 701                 compatible = "rockchip,rk-fb";
 702                 rockchip,disp-mode = <DUAL>;
 703         };
 704
 705         rk_screen: rk_screen{
 706                         compatible = "rockchip,screen";
 707         };
 708
 709         dsihost0: mipi@ff960000{
 710                 compatible = "rockchip,rk32-dsi";
 711                 rockchip,prop = <0>;
 712                 reg = <0xff960000 0x4000>;
 713                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 715                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 716                 status = "disabled";
 717         };
 718
 719         dsihost1: mipi@ff964000{
 720                 compatible = "rockchip,rk32-dsi";
 721                 rockchip,prop = <1>;
 722                 reg = <0xff964000 0x4000>;
 723                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 725                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 726                 status = "disabled";
 727         };
 728
 729         lvds: lvds@ff96c000 {
 730                 compatible = "rockchip,rk32-lvds";
 731                 reg = <0xff96c000 0x4000>;
 732                 clocks = <&clk_gates16 7>;
 733                 clock-names = "pclk_lvds";
 734         };
 735
 736         edp: edp@ff970000 {
 737                 compatible = "rockchip,rk32-edp";
 738                 reg = <0xff970000 0x4000>;
 739                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 740                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 741                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 742         };
 743
 744         hdmi: hdmi@ff980000 {
 745                 compatible = "rockchip,rk3288-hdmi";
 746                 reg = <0xff980000 0x20000>;
 747                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 748                 pinctrl-names = "default", "sleep";
 749                 pinctrl-0 = <&i2c5_sda &i2c5_scl &hdmi_cec>;
 750                 pinctrl-1 = <&i2c5_gpio>;
 751                 clocks = <&clk_gates16 9>, <&clk_gates5 12>, <&clk_gates5 11>;
 752                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 753                 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;
 754                 rockchip,hdmi_audio_source = <0>;
 755                 rockchip,hdcp_enable = <0>;
 756                 rockchip,cec_enable = <0>;
 757                 status = "disabled";
 758         };
 759
 760         lcdc0: lcdc@ff930000 {
 761                 compatible = "rockchip,rk3288-lcdc";
 762                 rockchip,prop = <PRMRY>;
 763                 rockchip,pwr18 = <0>;
 764                 rockchip,iommu-enabled = <0>;
 765                 reg = <0xff930000 0x10000>;
 766                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 767                 pinctrl-names = "default", "gpio";
 768                 pinctrl-0 = <&lcdc0_lcdc>;
 769                 pinctrl-1 = <&lcdc0_gpio>;
 770                 status = "disabled";
 771                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 772                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 773         };
 774
 775         lcdc1: lcdc@ff940000 {
 776                 compatible = "rockchip,rk3288-lcdc";
 777                 rockchip,prop = <EXTEND>;
 778                 rockchip,pwr18 = <0>;
 779                 rockchip,iommu-enabled = <0>;
 780                 reg = <0xff940000 0x10000>;
 781                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 782                 status = "disabled";
 783                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 784                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 785         };
 786
 787         adc: adc@ff100000 {
 788                 compatible = "rockchip,saradc";
 789                 reg = <0xff100000 0x100>;
 790                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 791                 #io-channel-cells = <1>;
 792                 io-channel-ranges;
 793                 rockchip,adc-vref = <1800>;
 794                 clock-frequency = <1000000>;
 795                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 796                 clock-names = "saradc", "pclk_saradc";
 797                 status = "disabled";
 798         };
 799
 800         rga@ff920000 {
 801                 compatible = "rockchip,rga2";
 802                 reg = <0xff920000 0x1000>;
 803                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 804                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 805                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 806         };
 807
 808         i2s: rockchip-i2s@0xff890000 {
 809                 compatible = "rockchip-i2s";
 810                 reg = <0xff890000 0x10000>;
 811                 i2s-id = <0>;
 812                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 813                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 814                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 815                 dmas = <&pdma0 0>, <&pdma0 1>;
 816                 //#dma-cells = <2>;
 817                 dma-names = "tx", "rx";
 818                 pinctrl-names = "default", "sleep";
 819                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 820                 pinctrl-1 = <&i2s_gpio>;
 821         };
 822
 823         spdif: rockchip-spdif@0xff8b0000 {
 824                 compatible = "rockchip-spdif";
 825                 reg = <0xff8b0000 0x10000>;     //8channel
 826                 //reg = <ff880000 0x10000>;//2channel
 827                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 828                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 829                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 830                 dmas = <&pdma0 3>;
 831                 //dmas = <&pdma0 2>; //2channel
 832                 //#dma-cells = <1>;
 833                 dma-names = "tx";
 834                 pinctrl-names = "default";
 835                 pinctrl-0 = <&spdif_tx>;
 836         };
 837
 838         vop1pwm: pwm@ff9401a0 {
 839                 compatible = "rockchip,vop-pwm";
 840                 reg = <0xff9401a0 0x10>;
 841
 842                 /* used by driver on remotectl'pwm */
 843                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 844                 #pwm-cells = <2>;
 845                 pinctrl-names = "default";
 846                 pinctrl-0 = <&vop1_pwm_pin>;
 847                 clocks = <&clk_gates13 11>, <&clk_gates15 7>, <&clk_gates15 8>;
 848                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 849                 status = "disabled";
 850         };
 851
 852         vop0pwm: pwm@ff9301a0 {
 853                 compatible = "rockchip,vop-pwm";
 854                 reg = <0xff9301a0 0x10>;
 855
 856                 /* used by driver on remotectl'pwm */
 857                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 858                 #pwm-cells = <2>;
 859                 pinctrl-names = "default";
 860                 pinctrl-0 = <&vop0_pwm_pin>;
 861                 clocks = <&clk_gates13 10>, <&clk_gates15 5>, <&clk_gates15 6>;
 862                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 863                 status = "disabled";
 864         };
 865
 866         pwm0: pwm@ff680000 {
 867                 compatible = "rockchip,rk-pwm";
 868                 reg = <0xff680000 0x10>;
 869
 870                 /* used by driver on remotectl'pwm */
 871                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 872                 #pwm-cells = <2>;
 873                 pinctrl-names = "default";
 874                 pinctrl-0 = <&pwm0_pin>;
 875                 clocks = <&clk_gates11 11>;
 876                 clock-names = "pclk_pwm";
 877                 status = "disabled";
 878         };
 879
 880         pwm1: pwm@ff680010 {
 881                 compatible = "rockchip,rk-pwm";
 882                 reg = <0xff680010 0x10>;
 883
 884                 /* used by driver on remotectl'pwm */
 885                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 886                 #pwm-cells = <2>;
 887                 pinctrl-names = "default";
 888                 pinctrl-0 = <&pwm1_pin>;
 889                 clocks = <&clk_gates11 11>;
 890                 clock-names = "pclk_pwm";
 891                 status = "disabled";
 892         };
 893
 894         pwm2: pwm@ff680020 {
 895                 compatible = "rockchip,rk-pwm";
 896                 reg = <0xff680020 0x10>;
 897
 898                 /* used by driver on remotectl'pwm */
 899                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 900                 #pwm-cells = <2>;
 901                 pinctrl-names = "default";
 902                 pinctrl-0 = <&pwm2_pin>;
 903                 clocks = <&clk_gates11 11>;
 904                 clock-names = "pclk_pwm";
 905                 status = "disabled";
 906         };
 907
 908         pwm3: pwm@ff680030 {
 909                 compatible = "rockchip,rk-pwm";
 910                 reg = <0xff680030 0x10>;
 911
 912                 /* used by driver on remotectl'pwm */
 913                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 914                 #pwm-cells = <2>;
 915                 pinctrl-names = "default";
 916                 pinctrl-0 = <&pwm3_pin>;
 917                 clocks = <&clk_gates11 11>;
 918                 clock-names = "pclk_pwm";
 919                 status = "disabled";
 920         };
 921
 922         dvfs {
 923
 924                 vd_arm: vd_arm {
 925                         regulator_name = "vdd_arm";
 926                         suspend_volt = <1000>; //mV
 927                         pd_core {
 928                                 clk_core_dvfs_table: clk_core {
 929                                         operating-points = <
 930                                                 /* KHz    uV */
 931                                                 312000 1100000
 932                                                 504000 1100000
 933                                                 816000 1100000
 934                                                 1008000 1100000
 935                                                 >;
 936                                         channel = <0>;
 937                                         temp-limit-enable = <1>;
 938                                         target-temp = <80>;
 939                                         min_temp_limit = <48>;
 940                                         normal-temp-limit = <
 941                                         /*delta-temp    delta-freq*/
 942                                                 3       96000
 943                                                 6       144000
 944                                                 9       192000
 945                                                 15      384000
 946                                                 >;
 947                                         performance-temp-limit = <
 948                                                 /*temp    freq*/
 949                                                 100     816000
 950                                                 >;
 951                                         status = "okay";
 952                                         regu-mode-table = <
 953                                                 /*freq     mode*/
 954                                                 1008000    4
 955                                                 0          3
 956                                         >;
 957                                         regu-mode-en = <0>;
 958                                 };
 959                         };
 960                 };
 961
 962                 vd_logic: vd_logic {
 963                         regulator_name = "vdd_logic";
 964                         suspend_volt = <1000>; //mV
 965                         pd_ddr {
 966                                 clk_ddr_dvfs_table: clk_ddr {
 967                                         operating-points = <
 968                                                 /* KHz    uV */
 969                                                 200000 1200000
 970                                                 300000 1200000
 971                                                 400000 1200000
 972                                                 >;
 973                                         bd-freq-table = <
 974                                                 /* bandwidth   freq */
 975                                                 5000           800000
 976                                                 3500           456000
 977                                                 2600           396000
 978                                                 2000           324000
 979                                                 >;
 980                                         channel = <2>;
 981                                         status = "disabled";
 982                                 };
 983                         };
 984
 985                         pd_vio {
 986                                 aclk_vio1_dvfs_table: aclk_vio1 {
 987                                         operating-points = <
 988                                                 /* KHz    uV */
 989                                                 100000 1100000
 990                                                 500000 1100000
 991                                                 >;
 992                                         status = "okay";
 993                                 };
 994                         };
 995                 };
 996
 997                 vd_gpu: vd_gpu {
 998                         regulator_name = "vdd_gpu";
 999                         suspend_volt = <1000>; //mV
1000                         pd_gpu {
1001                                 clk_gpu_dvfs_table: clk_gpu {
1002                                         operating-points = <
1003                                                 /* KHz    uV */
1004                                                 200000 1200000
1005                                                 300000 1200000
1006                                                 400000 1200000
1007                                                 >;
1008                                         channel = <1>;
1009                                         temp-limit-enable = <0>;
1010                                         target-temp = <90>;
1011                                         min_temp_limit = <200>;
1012                                         normal-temp-limit = <
1013                                         /*delta-temp    delta-freq*/
1014                                                 3       50000
1015                                                 6       150000
1016                                                 15      250000
1017                                                 >;
1018                                         status = "okay";
1019                                         regu-mode-table = <
1020                                                 /*freq     mode*/
1021                                                 200000     4
1022                                                 0          3
1023                                         >;
1024                                         regu-mode-en = <0>;
1025                                 };
1026                         };
1027                 };
1028         };
1029
1030         ion {
1031                 compatible = "rockchip,ion";
1032                 #address-cells = <1>;
1033                 #size-cells = <0>;
1034
1035                 ion_drm: rockchip,ion-heap@5 {
1036                         compatible = "rockchip,ion-heap";
1037                         rockchip,ion_heap = <5>;
1038                         reg = <0x00000000 0x00000000>;
1039                 };
1040                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1041                         compatible = "rockchip,ion-heap";
1042                         rockchip,ion_heap = <4>;
1043                         reg = <0x00000000 0x28000000>; /* 640MB */
1044                 };
1045                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1046                         compatible = "rockchip,ion-heap";
1047                         rockchip,ion_heap = <0>;
1048                 };
1049         };
1050
1051         vpu: vpu_service@ff9a0000 {
1052                 compatible = "vpu_service";
1053                 iommu_enabled = <0>;
1054                 reg = <0xff9a0000 0x800>;
1055                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "irq_enc", "irq_dec";
1057                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1058                 clock-names = "aclk_vcodec", "hclk_vcodec";
1059                 resets = <&reset RK3288_SOFT_RST_VCODEC_H>, <&reset RK3288_SOFT_RST_VCODEC_A>;
1060                 reset-names = "video_h", "video_a";
1061                 name = "vpu_service";
1062                 dev_mode = <0>;
1063                 //status = "disabled";
1064         };
1065
1066         hevc: hevc_service@ff9c0000 {
1067                 compatible = "rockchip,hevc_service";
1068                 iommu_enabled = <0>;
1069                 reg = <0xff9c0000 0x800>;
1070                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1071                 interrupt-names = "irq_dec";
1072                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1073                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1074                 resets = <&reset RK3288_SOFT_RST_VCODEC_H>, <&reset RK3288_SOFT_RST_VCODEC_A>,
1075                         <&reset RK3288_SOFT_RST_HEVC>;
1076                 reset-names = "video_h", "video_a", "video";
1077                 dev_mode = <1>;
1078                 name = "hevc_service";
1079                 //status = "disabled";
1080         };
1081
1082         iep: iep@ff900000 {
1083                 compatible = "rockchip,iep";
1084                 iommu_enabled = <0>;
1085                 reg = <0xff900000 0x800>;
1086                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1087                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1088                 clock-names = "aclk_iep", "hclk_iep";
1089                 status = "okay";
1090         };
1091
1092         dwc_control_usb: dwc-control-usb@ff770284 {
1093                 compatible = "rockchip,rk3288-dwc-control-usb";
1094                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1095                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1096                       <0xff770320 0x14>, <0xff770334 0x14>,
1097                       <0xff770348 0x10>, <0xff770358 0x08>,
1098                       <0xff770360 0x08>;
1099                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1100                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1101                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1102                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1103                             "GRF_UOC4_BASE";
1104                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1105                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1106                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1107                 interrupt-names = "otg_id", "otg_bvalid",
1108                                   "otg_linestate", "host0_linestate",
1109                                   "host1_linestate";
1110                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1111                          <&otgphy1_480m>, <&otgphy2_480m>;
1112                 clock-names = "hclk_usb_peri", "usbphy_480m",
1113                               "usbphy1_480m", "usbphy2_480m";
1114
1115                 usb_bc {
1116                         compatible = "synopsys,phy";
1117                                         /* offset bit mask */
1118                         rk_usb,bvalid     = <0x288 14 1>;
1119                         rk_usb,iddig      = <0x288 17 1>;
1120                         rk_usb,dcdenb     = <0x328 14 1>;
1121                         rk_usb,vdatsrcenb = <0x328  7 1>;
1122                         rk_usb,vdatdetenb = <0x328  6 1>;
1123                         rk_usb,chrgsel    = <0x328  5 1>;
1124                         rk_usb,chgdet     = <0x2cc 23 1>;
1125                         rk_usb,fsvminus   = <0x2cc 25 1>;
1126                         rk_usb,fsvplus    = <0x2cc 24 1>;
1127                 };
1128         };
1129
1130         usb0: usb@ff580000 {
1131                 compatible = "rockchip,rk3288_usb20_otg";
1132                 reg = <0xff580000 0x40000>;
1133                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1134                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1135                 clock-names = "clk_usbphy0", "hclk_usb0";
1136                 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1137                                 <&reset RK3288_SOFT_RST_USBOTGC>;
1138                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1139                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1140                 rockchip,usb-mode = <0>;
1141         };
1142
1143         usb1: usb@ff540000 {
1144                 compatible = "rockchip,rk3288_usb20_host";
1145                 reg = <0xff540000 0x40000>;
1146                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1147                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1148                          <&usbphy_480m>;
1149                 clock-names = "clk_usbphy1", "hclk_usb1",
1150                               "usbphy_480m";
1151                 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1152                                 <&reset RK3288_SOFT_RST_USBHOST1C>;
1153                 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1154         };
1155
1156         usb2: usb@ff500000 {
1157                 compatible = "rockchip,rk3288_rk_ehci_host";
1158                 reg = <0xff500000 0x20000>;
1159                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1160                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1161                 clock-names = "clk_usbphy2", "hclk_usb2";
1162                 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1163                                 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1164                 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1165         };
1166
1167         usb3: usb@ff520000 {
1168                 compatible = "rockchip,rk3288_rk_ohci_host";
1169                 reg = <0xff520000 0x20000>;
1170                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1171                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1172                 clock-names = "clk_usbphy3", "hclk_usb3";
1173                 status = "disabled";
1174         };
1175
1176         usb4: usb@ff5c0000 {
1177                 compatible = "rockchip,rk3288_rk_ehci1_host";
1178                 reg = <0xff5c0000 0x40000>;
1179                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1180                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1181                          <&ehci1phy_12m>, <&usbphy_480m>,
1182                          <&otgphy1_480m>, <&otgphy2_480m>;
1183                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1184                               "ehci1phy_12m", "usbphy_480m",
1185                               "ehci1_usbphy1", "ehci1_usbphy2";
1186                 resets = <&reset RK3288_SOFT_RST_EHCI1>, <&reset RK3288_SOFT_RST_EHCI1_AUX>,
1187                                 <&reset RK3288_SOFT_RST_EHCI1PHY>;
1188                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1189         };
1190
1191         gmac: eth@ff290000 {
1192                 compatible = "rockchip,rk3288-gmac";
1193                 reg = <0xff290000 0x10000>;
1194                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1195                 interrupt-names = "macirq";
1196                 clocks = <&clk_mac>, <&clk_gates5 0>,
1197                          <&clk_gates5 1>, <&clk_gates5 2>,
1198                          <&clk_gates5 3>, <&clk_gates8 0>,
1199                          <&clk_gates8 1>;
1200                 clock-names = "clk_mac", "mac_clk_rx",
1201                               "mac_clk_tx", "clk_mac_ref",
1202                               "clk_mac_refout", "aclk_mac",
1203                               "pclk_mac";
1204                 phy-mode = "rgmii";
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1207         };
1208
1209         gpu {
1210                 compatible = "arm,malit764",
1211                              "arm,malit76x",
1212                              "arm,malit7xx",
1213                              "arm,mali-midgard";
1214                 reg = <0xffa30000 0x10000>;
1215                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1216                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1217                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1218                 interrupt-names = "JOB", "MMU", "GPU";
1219         };
1220
1221         iep_mmu {
1222                 dbgname = "iep";
1223                 compatible = "rockchip,iep_mmu";
1224                 reg = <0xff900800 0x100>;
1225                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226                 interrupt-names = "iep_mmu";
1227         };
1228
1229         vip_mmu {
1230                 dbgname = "vip";
1231                 compatible = "rockchip,vip_mmu";
1232                 reg = <0xff950800 0x100>;
1233                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1234                 interrupt-names = "vip_mmu";
1235         };
1236
1237         vopb_mmu {
1238                 dbgname = "vopb";
1239                 compatible = "rockchip,vopb_mmu";
1240                 reg = <0xff930300 0x100>;
1241                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1242                 interrupt-names = "vopb_mmu";
1243         };
1244
1245         vopl_mmu {
1246                 dbgname = "vopl";
1247                 compatible = "rockchip,vopl_mmu";
1248                 reg = <0xff940300 0x100>;
1249                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1250                 interrupt-names = "vopl_mmu";
1251         };
1252
1253         hevc_mmu {
1254                 dbgname = "hevc";
1255                 compatible = "rockchip,hevc_mmu";
1256                 reg = <0xff9c0440 0x40>,
1257                       <0xff9c0480 0x40>;
1258                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1259                 interrupt-names = "hevc_mmu";
1260         };
1261
1262         vpu_mmu {
1263                 dbgname = "vpu";
1264                 compatible = "rockchip,vpu_mmu";
1265                 reg = <0xff9a0800 0x100>;
1266                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1267                 interrupt-names = "vpu_mmu";
1268         };
1269
1270         isp_mmu {
1271                 dbgname = "isp_mmu";
1272                 compatible = "rockchip,isp_mmu";
1273                 reg = <0xff914000 0x100>,
1274                       <0xff915000 0x100>;
1275                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1276                 interrupt-names = "isp_mmu";
1277         };
1278
1279         rockchip_suspend {
1280                 rockchip,ctrbits = <
1281                         (0
1282                          |RKPM_CTR_PWR_DMNS
1283                          |RKPM_CTR_GTCLKS
1284                          |RKPM_CTR_PLLS
1285                  //      |RKPM_CTR_GPIOS
1286                 //       |RKPM_CTR_SYSCLK_DIV
1287                 //       |RKPM_CTR_IDLEAUTO_MD
1288                 //       |RKPM_CTR_ARMOFF_LPMD
1289                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1290                         )
1291                         >;
1292                 rockchip,pmic-suspend_gpios = <
1293                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1294                         >;
1295                 rockchip,pmic-resume_gpios = <
1296                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1297                         >;
1298         };
1299
1300         isp: isp@ff910000{
1301                 compatible = "rockchip,isp";
1302                 reg = <0xff910000 0x10000>;
1303                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1304                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1305                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1306                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1307                 pinctrl-0 = <&isp_mipi>;
1308                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1309                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1310                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1311                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1312                 pinctrl-5 = <&isp_mipi>;
1313                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1314                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1315                 pinctrl-8 = <&isp_flash_trigger>;
1316                 rockchip,isp,mipiphy = <2>;
1317                 rockchip,isp,cifphy = <1>;
1318                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1319                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1320                 rockchip,isp,iommu_enable = <1>;
1321                 status = "okay";
1322         };
1323         cif: cif@ff950000 {
1324              compatible = "rockchip,cif";
1325              reg = <0xff950000 0x10000>;
1326              interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1327              clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
1328              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out";
1329              pinctrl-names = "cif_pin_all";
1330              pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1331              status = "okay";
1332              };
1333
1334         tsadc: tsadc@ff280000 {
1335                 compatible = "rockchip,tsadc";
1336                 reg = <0xff280000 0x100>;
1337                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1338                 #io-channel-cells = <1>;
1339                 io-channel-ranges;
1340                 clock-frequency = <10000>;
1341                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1342                 clock-names = "tsadc", "pclk_tsadc";
1343                 pinctrl-names = "default", "tsadc_int";
1344                 pinctrl-0 = <&tsadc_gpio>;
1345                 pinctrl-1 = <&tsadc_int>;
1346                 tsadc-ht-temp = <120>;
1347                 tsadc-ht-reset-cru = <1>;
1348                 tsadc-ht-pull-gpio = <0>;
1349                 status = "okay";
1350         };
1351
1352         lcdc_vdd_domain: lcdc-vdd-domain {
1353                 compatible = "rockchip,io_vol_domain";
1354                 pinctrl-names = "default", "1.8V", "3.3V";
1355                 pinctrl-0 = <&lcdc_vcc>;
1356                 pinctrl-1 = <&lcdc_vcc_18>;
1357                 pinctrl-2 = <&lcdc_vcc_33>;
1358         };
1359
1360         dpio_vdd_domain: dpio-vdd-domain {
1361                 compatible = "rockchip,io_vol_domain";
1362                 pinctrl-names = "default", "1.8V", "3.3V";
1363                 pinctrl-0 = <&dvp_vcc>;
1364                 pinctrl-1 = <&dvp_vcc_18>;
1365                 pinctrl-2 = <&dvp_vcc_33>;
1366         };
1367
1368         flash0_vdd_domain: flash0-vdd-domain {
1369                 compatible = "rockchip,io_vol_domain";
1370                 pinctrl-names = "default", "1.8V", "3.3V";
1371                 pinctrl-0 = <&flash0_vcc>;
1372                 pinctrl-1 = <&flash0_vcc_18>;
1373                 pinctrl-2 = <&flash0_vcc_33>;
1374         };
1375
1376         flash1_vdd_domain: flash1-vdd-domain {
1377                 compatible = "rockchip,io_vol_domain";
1378                 pinctrl-names = "default", "1.8V", "3.3V";
1379                 pinctrl-0 = <&flash1_vcc>;
1380                 pinctrl-1 = <&flash1_vcc_18>;
1381                 pinctrl-2 = <&flash1_vcc_33>;
1382         };
1383
1384         apio3_vdd_domain: apio3-vdd-domain {
1385                 compatible = "rockchip,io_vol_domain";
1386                 pinctrl-names = "default", "1.8V", "3.3V";
1387                 pinctrl-0 = <&wifi_vcc>;
1388                 pinctrl-1 = <&wifi_vcc_18>;
1389                 pinctrl-2 = <&wifi_vcc_33>;
1390         };
1391
1392         apio5_vdd_domain: apio5-vdd-domain {
1393                 compatible = "rockchip,io_vol_domain";
1394                 pinctrl-names = "default", "1.8V", "3.3V";
1395                 pinctrl-0 = <&bb_vcc>;
1396                 pinctrl-1 = <&bb_vcc_18>;
1397                 pinctrl-2 = <&bb_vcc_33>;
1398         };
1399
1400         apio4_vdd_domain: apio4-vdd-domain {
1401                 compatible = "rockchip,io_vol_domain";
1402                 pinctrl-names = "default", "1.8V", "3.3V";
1403                 pinctrl-0 = <&audio_vcc>;
1404                 pinctrl-1 = <&audio_vcc_18>;
1405                 pinctrl-2 = <&audio_vcc_33>;
1406         };
1407
1408         apio1_vdd_domain: apio0-vdd-domain {
1409                 compatible = "rockchip,io_vol_domain";
1410                 pinctrl-names = "default", "1.8V", "3.3V";
1411                 pinctrl-0 = <&gpio30_vcc>;
1412                 pinctrl-1 = <&gpio30_vcc_18>;
1413                 pinctrl-2 = <&gpio30_vcc_33>;
1414         };
1415
1416         apio2_vdd_domain: apio2-vdd-domain {
1417                 compatible = "rockchip,io_vol_domain";
1418                 pinctrl-names = "default", "1.8V", "3.3V";
1419                 pinctrl-0 = <&gpio1830_vcc>;
1420                 pinctrl-1 = <&gpio1830_vcc_18>;
1421                 pinctrl-2 = <&gpio1830_vcc_33>;
1422         };
1423
1424         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1425                 compatible = "rockchip,io_vol_domain";
1426                 pinctrl-names = "default", "1.8V", "3.3V";
1427                 pinctrl-0 = <&sdcard_vcc>;
1428                 pinctrl-1 = <&sdcard_vcc_18>;
1429                 pinctrl-2 = <&sdcard_vcc_33>;
1430         };
1431
1432         chosen {
1433                 bootargs = "vmalloc=496M";
1434         };
1435 };